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ARMV7: OMAP: Configure Overo's second network chip

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Confiures GPMC timings for both chips and also configures pinmux
for GPIO_65, which is used as the interrupt signal for the second chip

Signed-off-by: Scott Ellis <scott@jumpnowtek.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
master
Steve Sakoman 15 years ago committed by Sandeep Paulraj
parent 06b95bd50d
commit ba9a11e4ea
2 changed files with 19 additions and 9 deletions
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  1. 26
      board/overo/overo.c
  2. 2
      board/overo/overo.h

26
board/overo/overo.c
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@ -43,6 +43,17 @@
static void setup_net_chip(void);
#endif
/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/*
* Routine: board_init
* Description: Early hardware init.
@ -131,14 +142,13 @@ static void setup_net_chip(void)
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
/* first lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
/* second lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
GPMC_SIZE_16M);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

2
board/overo/overo.h
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@ -138,7 +138,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\

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