Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

stm32f1: remove stm32f1 support

Browse Source 
A few years ago STM32F1 SoCs support has been added :
0144caf22c  gpio: stm32: add stm32f1 support
2d18ef2364  ARMv7M: add STM32F1 support

But neither STM32F1 dedicated defconfig nor board was
associated to these commits.

Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]

[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
master
Patrice Chotard 8 years ago committed by Tom Rini
parent 7b07a20c5e
commit bc5d038445
12 changed files with 0 additions and 892 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 118
      arch/arm/include/asm/arch-stm32f1/gpio.h
  2. 124
      arch/arm/include/asm/arch-stm32f1/stm32.h
  3. 4
      arch/arm/mach-stm32/Kconfig
  4. 1
      arch/arm/mach-stm32/Makefile
  5. 3
      arch/arm/mach-stm32/stm32f1/Kconfig
  6. 14
      arch/arm/mach-stm32/stm32f1/Makefile
  7. 196
      arch/arm/mach-stm32/stm32f1/clock.c
  8. 180
      arch/arm/mach-stm32/stm32f1/flash.c
  9. 36
      arch/arm/mach-stm32/stm32f1/soc.c
  10. 121
      arch/arm/mach-stm32/stm32f1/timer.c
  11. 94
      drivers/gpio/stm32_gpio.c
  12. 1
      include/flash.h

118
arch/arm/include/asm/arch-stm32f1/gpio.h
Unescape View File

@ -1,118 +0,0 @@
/*
* (C) Copyright 2011
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
enum stm32_gpio_port {
STM32_GPIO_PORT_A = 0,
STM32_GPIO_PORT_B,
STM32_GPIO_PORT_C,
STM32_GPIO_PORT_D,
STM32_GPIO_PORT_E,
STM32_GPIO_PORT_F,
STM32_GPIO_PORT_G,
};
enum stm32_gpio_pin {
STM32_GPIO_PIN_0 = 0,
STM32_GPIO_PIN_1,
STM32_GPIO_PIN_2,
STM32_GPIO_PIN_3,
STM32_GPIO_PIN_4,
STM32_GPIO_PIN_5,
STM32_GPIO_PIN_6,
STM32_GPIO_PIN_7,
STM32_GPIO_PIN_8,
STM32_GPIO_PIN_9,
STM32_GPIO_PIN_10,
STM32_GPIO_PIN_11,
STM32_GPIO_PIN_12,
STM32_GPIO_PIN_13,
STM32_GPIO_PIN_14,
STM32_GPIO_PIN_15
};
enum stm32_gpio_icnf {
STM32_GPIO_ICNF_AN = 0,
STM32_GPIO_ICNF_IN_FLT,
STM32_GPIO_ICNF_IN_PUD,
STM32_GPIO_ICNF_RSVD
};
enum stm32_gpio_ocnf {
STM32_GPIO_OCNF_GP_PP = 0,
STM32_GPIO_OCNF_GP_OD,
STM32_GPIO_OCNF_AF_PP,
STM32_GPIO_OCNF_AF_OD
};
enum stm32_gpio_pupd {
STM32_GPIO_PUPD_DOWN = 0,
STM32_GPIO_PUPD_UP,
};
enum stm32_gpio_mode {
STM32_GPIO_MODE_IN = 0,
STM32_GPIO_MODE_OUT_10M,
STM32_GPIO_MODE_OUT_2M,
STM32_GPIO_MODE_OUT_50M
};
enum stm32_gpio_af {
STM32_GPIO_AF0 = 0,
STM32_GPIO_AF1,
STM32_GPIO_AF2,
STM32_GPIO_AF3,
STM32_GPIO_AF4,
STM32_GPIO_AF5,
STM32_GPIO_AF6,
STM32_GPIO_AF7,
STM32_GPIO_AF8,
STM32_GPIO_AF9,
STM32_GPIO_AF10,
STM32_GPIO_AF11,
STM32_GPIO_AF12,
STM32_GPIO_AF13,
STM32_GPIO_AF14,
STM32_GPIO_AF15
};
struct stm32_gpio_dsc {
enum stm32_gpio_port port;
enum stm32_gpio_pin pin;
};
struct stm32_gpio_ctl {
enum stm32_gpio_icnf icnf;
enum stm32_gpio_ocnf ocnf;
enum stm32_gpio_mode mode;
enum stm32_gpio_pupd pupd;
enum stm32_gpio_af af;
};
static inline unsigned stm32_gpio_to_port(unsigned gpio)
{
return gpio / 16;
}
static inline unsigned stm32_gpio_to_pin(unsigned gpio)
{
return gpio % 16;
}
int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
const struct stm32_gpio_ctl *gpio_ctl);
int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
#endif /* _STM32_GPIO_H_ */

124
arch/arm/include/asm/arch-stm32f1/stm32.h
Unescape View File

@ -1,124 +0,0 @@
/*
* (C) Copyright 2011
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
/*
* Peripheral memory map
*/
#define STM32_PERIPH_BASE 0x40000000
#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000)
#define STM32_BUS_MASK 0xFFFF0000
#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
/*
* Register maps
*/
struct stm32_des_regs {
u16 flash_size;
u16 pad1;
u32 pad2;
u32 uid0;
u32 uid1;
u32 uid2;
};
struct stm32_rcc_regs {
u32 cr; /* RCC clock control */
u32 cfgr; /* RCC clock configuration */
u32 cir; /* RCC clock interrupt */
u32 apb2rstr; /* RCC APB2 peripheral reset */
u32 apb1rstr; /* RCC APB1 peripheral reset */
u32 ahbenr; /* RCC AHB peripheral clock enable */
u32 apb2enr; /* RCC APB2 peripheral clock enable */
u32 apb1enr; /* RCC APB1 peripheral clock enable */
u32 bdcr; /* RCC Backup domain control */
u32 csr; /* RCC clock control & status */
};
struct stm32_pwr_regs {
u32 cr;
u32 csr;
};
struct stm32_flash_regs {
u32 acr;
u32 keyr;
u32 optkeyr;
u32 sr;
u32 cr;
u32 ar;
u32 rsvd1; /* Reserved */
u32 obr;
u32 wrpr;
u32 rsvd2[8]; /* Reserved */
u32 keyr2;
u32 rsvd3;
u32 sr2;
u32 cr2;
u32 ar2;
};
/* Per bank register set for XL devices */
struct stm32_flash_bank_regs {
u32 keyr;
u32 rsvd; /* Reserved */
u32 sr;
u32 cr;
u32 ar;
};
/*
* Registers access macros
*/
#define STM32_DES_BASE (0x1ffff7e0)
#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE)
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000)
#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000)
#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
#define STM32_FLASH_SR_BSY (1 << 0)
#define STM32_FLASH_CR_PG (1 << 0)
#define STM32_FLASH_CR_PER (1 << 1)
#define STM32_FLASH_CR_STRT (1 << 6)
#define STM32_FLASH_CR_LOCK (1 << 7)
enum clock {
CLOCK_CORE,
CLOCK_AHB,
CLOCK_APB1,
CLOCK_APB2
};
int configure_clocks(void);
unsigned long clock_get(enum clock clck);
#endif /* _MACH_STM32_H_ */

4
arch/arm/mach-stm32/Kconfig
Unescape View File

@ -3,9 +3,6 @@ if STM32
config STM32F4
bool "stm32f4 family"
config STM32F1
bool "stm32f1 family"
config STM32F7
bool "stm32f7 family"
select SUPPORT_SPL
@ -29,7 +26,6 @@ config STM32F7
select SPL_XIP_SUPPORT
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f1/Kconfig"
source "arch/arm/mach-stm32/stm32f7/Kconfig"
endif

1
arch/arm/mach-stm32/Makefile
Unescape View File

@ -5,6 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_STM32F1) += stm32f1/
obj-$(CONFIG_STM32F4) += stm32f4/
obj-$(CONFIG_STM32F7) += stm32f7/

3
arch/arm/mach-stm32/stm32f1/Kconfig
Unescape View File

@ -1,3 +0,0 @@
if STM32F1
endif

14
arch/arm/mach-stm32/stm32f1/Makefile
Unescape View File

@ -1,14 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2015
# Kamil Lulko, <kamil.lulko@gmail.com>
#
# Copyright 2015 ATS Advanced Telematics Systems GmbH
# Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o clock.o timer.o flash.o

196
arch/arm/mach-stm32/stm32f1/clock.c
Unescape View File

@ -1,196 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* (C) Copyright 2014
* STMicroelectronics
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#define RCC_CR_HSION (1 << 0)
#define RCC_CR_HSEON (1 << 16)
#define RCC_CR_HSERDY (1 << 17)
#define RCC_CR_HSEBYP (1 << 18)
#define RCC_CR_CSSON (1 << 19)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CFGR_PLLMUL_MASK 0x3C0000
#define RCC_CFGR_PLLMUL_SHIFT 18
#define RCC_CFGR_PLLSRC_HSE (1 << 16)
#define RCC_CFGR_AHB_PSC_MASK 0xF0
#define RCC_CFGR_APB1_PSC_MASK 0x700
#define RCC_CFGR_APB2_PSC_MASK 0x3800
#define RCC_CFGR_SW0 (1 << 0)
#define RCC_CFGR_SW1 (1 << 1)
#define RCC_CFGR_SW_MASK 0x3
#define RCC_CFGR_SW_HSI 0
#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
#define RCC_CFGR_SWS0 (1 << 2)
#define RCC_CFGR_SWS1 (1 << 3)
#define RCC_CFGR_SWS_MASK 0xC
#define RCC_CFGR_SWS_HSI 0
#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_PPRE1_SHIFT 8
#define RCC_CFGR_PPRE2_SHIFT 11
#define RCC_APB1ENR_PWREN (1 << 28)
#define PWR_CR_VOS0 (1 << 14)
#define PWR_CR_VOS1 (1 << 15)
#define PWR_CR_VOS_MASK 0xC000
#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
#define FLASH_ACR_WS(n) n
#define FLASH_ACR_PRFTEN (1 << 8)
#define FLASH_ACR_ICEN (1 << 9)
#define FLASH_ACR_DCEN (1 << 10)
struct psc {
u8 ahb_psc;
u8 apb1_psc;
u8 apb2_psc;
};
#define AHB_PSC_1 0
#define AHB_PSC_2 0x8
#define AHB_PSC_4 0x9
#define AHB_PSC_8 0xA
#define AHB_PSC_16 0xB
#define AHB_PSC_64 0xC
#define AHB_PSC_128 0xD
#define AHB_PSC_256 0xE
#define AHB_PSC_512 0xF
#define APB_PSC_1 0
#define APB_PSC_2 0x4
#define APB_PSC_4 0x5
#define APB_PSC_8 0x6
#define APB_PSC_16 0x7
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
#if (CONFIG_STM32_HSE_HZ == 8000000)
#define RCC_CFGR_PLLMUL_CFG 0x7
struct psc psc_hse = {
.ahb_psc = AHB_PSC_1,
.apb1_psc = APB_PSC_2,
.apb2_psc = APB_PSC_1
};
#else
#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
#endif
#endif
int configure_clocks(void)
{
/* Reset RCC configuration */
setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
| RCC_CR_PLLON));
clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
writel(0, &STM32_RCC->cir); /* Disable all interrupts */
/* Configure for HSE+PLL operation */
setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
;
/* Enable high performance mode, System frequency up to 168 MHz */
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
setbits_le32(&STM32_RCC->cfgr,
RCC_CFGR_PLLMUL_CFG << RCC_CFGR_PLLMUL_SHIFT);
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_PLLSRC_HSE);
setbits_le32(&STM32_RCC->cfgr, ((
psc_hse.ahb_psc << RCC_CFGR_HPRE_SHIFT)
| (psc_hse.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
| (psc_hse.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
;
/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
| FLASH_ACR_DCEN, &STM32_FLASH->acr);
clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
return 0;
}
unsigned long clock_get(enum clock clck)
{
u32 sysclk = 0;
u32 shift = 0;
/* PLL table lookups for clock computation */
u8 pll_mul_table[16] = {
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16
};
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
};
u8 apb_psc_table[8] = {
0, 0, 0, 0, 1, 2, 3, 4
};
if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
u16 pll;
pll = ((readl(&STM32_RCC->cfgr) & RCC_CFGR_PLLMUL_MASK)
>> RCC_CFGR_PLLMUL_SHIFT);
sysclk = CONFIG_STM32_HSE_HZ * pll_mul_table[pll];
}
switch (clck) {
case CLOCK_CORE:
return sysclk;
break;
case CLOCK_AHB:
shift = ahb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
break;
case CLOCK_APB1:
shift = apb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
break;
case CLOCK_APB2:
shift = apb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
break;
default:
return 0;
break;
}
}

180
arch/arm/mach-stm32/stm32f1/flash.c
Unescape View File

@ -1,180 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#define STM32_FLASH_KEY1 0x45670123
#define STM32_FLASH_KEY2 0xcdef89ab
#define STM32_NUM_BANKS 2
#define STM32_MAX_BANK 0x200
flash_info_t flash_info[STM32_NUM_BANKS];
static struct stm32_flash_bank_regs *flash_bank[STM32_NUM_BANKS];
static void stm32f1_flash_lock(u8 bank, u8 lock)
{
if (lock) {
setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_LOCK);
} else {
writel(STM32_FLASH_KEY1, &flash_bank[bank]->keyr);
writel(STM32_FLASH_KEY2, &flash_bank[bank]->keyr);
}
}
/* Only XL devices are supported (2 KiB sector size) */
unsigned long flash_init(void)
{
u8 i, banks;
u16 j, size;
/* Set up accessors for XL devices with wonky register layout */
flash_bank[0] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr;
flash_bank[1] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr2;
/*
* Get total flash size (in KiB) and configure number of banks
* present and sector count per bank.
*/
size = readw(&STM32_DES->flash_size);
if (size <= STM32_MAX_BANK) {
banks = 1;
flash_info[0].sector_count = size >> 1;
} else {
banks = 2;
flash_info[0].sector_count = STM32_MAX_BANK >> 1;
flash_info[1].sector_count = (size - STM32_MAX_BANK) >> 1;
}
/* Configure start/size for all sectors */
for (i = 0; i < banks; i++) {
flash_info[i].flash_id = FLASH_STM32F1;
flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 19);
flash_info[i].size = 2048;
for (j = 1; (j < flash_info[i].sector_count); j++) {
flash_info[i].start[j] = flash_info[i].start[j - 1]
+ 2048;
flash_info[i].size += 2048;
}
}
return size << 10;
}
void flash_print_info(flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("Missing or unknown FLASH type\n");
return;
} else if (info->flash_id == FLASH_STM32F1) {
printf("STM32F1 Embedded Flash\n");
}
printf(" Size: %ld MB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf("\n");
return;
}
int flash_erase(flash_info_t *info, int first, int last)
{
u8 bank = 0xff;
int i;
for (i = 0; i < STM32_NUM_BANKS; i++) {
if (info == &flash_info[i]) {
bank = i;
break;
}
}
if (bank == 0xff)
return -1;
stm32f1_flash_lock(bank, 0);
for (i = first; i <= last; i++) {
while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
;
setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER);
writel(info->start[i], &flash_bank[bank]->ar);
setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_STRT);
while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
;
}
clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER);
stm32f1_flash_lock(bank, 1);
return 0;
}
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong i;
u8 bank = 0xff;
if (addr & 1) {
printf("Flash address must be half word aligned\n");
return -1;
}
if (cnt & 1) {
printf("Flash length must be half word aligned\n");
return -1;
}
for (i = 0; i < 2; i++) {
if (info == &flash_info[i]) {
bank = i;
break;
}
}
if (bank == 0xff)
return -1;
while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
;
stm32f1_flash_lock(bank, 0);
setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG);
/* STM32F1 requires half word writes */
for (i = 0; i < cnt >> 1; i++) {
*(u16 *)(addr + i * 2) = ((u16 *)src)[i];
while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY)
;
}
clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG);
stm32f1_flash_lock(bank, 1);
return 0;
}

36
arch/arm/mach-stm32/stm32f1/soc.c
Unescape View File

@ -1,36 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
u32 get_cpu_rev(void)
{
return 0;
}
int arch_cpu_init(void)
{
configure_clocks();
/*
* Configure the memory protection unit (MPU) to allow full access to
* the whole 4GB address space.
*/
writel(0, &V7M_MPU->rnr);
writel(0, &V7M_MPU->rbar);
writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
| V7M_MPU_RASR_EN), &V7M_MPU->rasr);
writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
return 0;
}

121
arch/arm/mach-stm32/stm32f1/timer.c
Unescape View File

@ -1,121 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* Copyright 2015 ATS Advanced Telematics Systems GmbH
* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000)
#define RCC_APB1ENR_TIM2EN (1 << 0)
struct stm32_tim2_5 {
u32 cr1;
u32 cr2;
u32 smcr;
u32 dier;
u32 sr;
u32 egr;
u32 ccmr1;
u32 ccmr2;
u32 ccer;
u32 cnt;
u32 psc;
u32 arr;
u32 reserved1;
u32 ccr1;
u32 ccr2;
u32 ccr3;
u32 ccr4;
u32 reserved2;
u32 dcr;
u32 dmar;
u32 or;
};
#define TIM_CR1_CEN (1 << 0)
#define TIM_EGR_UG (1 << 0)
int timer_init(void)
{
struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
&tim->psc);
else
writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
&tim->psc);
writel(0xFFFFFFFF, &tim->arr);
writel(TIM_CR1_CEN, &tim->cr1);
setbits_le32(&tim->egr, TIM_EGR_UG);
gd->arch.tbl = 0;
gd->arch.tbu = 0;
gd->arch.lastinc = 0;
return 0;
}
ulong get_timer(ulong base)
{
return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
}
unsigned long long get_ticks(void)
{
struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
u32 now;
now = readl(&tim->cnt);
if (now >= gd->arch.lastinc)
gd->arch.tbl += (now - gd->arch.lastinc);
else
gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
gd->arch.lastinc = now;
return gd->arch.tbl;
}
void reset_timer(void)
{
struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
gd->arch.lastinc = readl(&tim->cnt);
gd->arch.tbl = 0;
}
/* delay x useconds */
void __udelay(ulong usec)
{
unsigned long long start;
start = get_ticks(); /* get current timestamp */
while ((get_ticks() - start) < usec)
; /* loop till time has passed */
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ_CLOCK;
}

94
drivers/gpio/stm32_gpio.c
Unescape View File

@ -19,7 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@ -74,81 +73,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
out:
return rv;
}
#elif defined(CONFIG_STM32F1)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
STM32_GPIOG_BASE
};
#define STM32_GPIO_CR_MODE_MASK 0x3
#define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4)
#define STM32_GPIO_CR_CNF_MASK 0x3
#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
struct stm32_gpio_regs {
u32 crl; /* GPIO port configuration low */
u32 crh; /* GPIO port configuration high */
u32 idr; /* GPIO port input data */
u32 odr; /* GPIO port output data */
u32 bsrr; /* GPIO port bit set/reset */
u32 brr; /* GPIO port bit reset */
u32 lckr; /* GPIO port configuration lock */
};
#define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
#define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
x->pupd > 1)
int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
const struct stm32_gpio_ctl *ctl)
{
struct stm32_gpio_regs *gpio_regs;
u32 *cr;
int p, crp;
int rv;
if (CHECK_DSC(dsc)) {
rv = -EINVAL;
goto out;
}
if (CHECK_CTL(ctl)) {
rv = -EINVAL;
goto out;
}
p = dsc->pin;
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
if (p < 8) {
cr = &gpio_regs->crl;
crp = p;
} else {
cr = &gpio_regs->crh;
crp = p - 8;
}
clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
/* Inputs set the optional pull up / pull down */
if (ctl->mode == STM32_GPIO_MODE_IN) {
setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
clrbits_le32(&gpio_regs->odr, 0x1 << p);
setbits_le32(&gpio_regs->odr, ctl->pupd << p);
} else {
setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
}
rv = 0;
out:
return rv;
}
#else
#error STM32 family not supported
#endif
int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
{
@ -207,20 +131,11 @@ int gpio_direction_input(unsigned gpio)
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
#elif defined(CONFIG_STM32F1)
ctl.mode = STM32_GPIO_MODE_IN;
ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
ctl.ocnf = STM32_GPIO_OCNF_GP_PP; /* ignored for input */
ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for floating */
#else
#error STM32 family not supported
#endif
return stm32_gpio_config(&dsc, &ctl);
}
@ -233,19 +148,10 @@ int gpio_direction_output(unsigned gpio, int value)
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_OUT;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
#elif defined(CONFIG_STM32F1)
ctl.mode = STM32_GPIO_MODE_OUT_50M;
ctl.ocnf = STM32_GPIO_OCNF_GP_PP;
ctl.icnf = STM32_GPIO_ICNF_IN_FLT; /* ignored for output */
ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for output */
#else
#error STM32 family not supported
#endif
res = stm32_gpio_config(&dsc, &ctl);
if (res < 0)

1
include/flash.h
Unescape View File

@ -467,7 +467,6 @@ extern flash_info_t *flash_get_info(ulong base);
#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
#define FLASH_STM32 0x00F2 /* STM32 Embedded Flash */
#define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */

Write Preview
Loading…
Cancel
Save