Enabled support for Rev 1.3 SPD for DDR2 DIMMs

SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.

This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c

@@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
  * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
  * Not certain if any good value exists for CL=2
  */
-				 /* CL2   CL3   CL4   CL5   CL6 */
-unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500 };
+				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
+unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };
 
 unsigned int
 compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)

common/ddr_spd.c

@@ -20,11 +20,15 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum)
 	 * Check SPD revision supported
 	 * Rev 1.2 or less supported by this code
 	 */
-	if (spd_rev > 0x12) {
+	if (spd_rev >= 0x20) {
 		printf("SPD revision %02X not supported by this code\n",
 		       spd_rev);
 		return 1;
 	}
+	if (spd_rev > 0x13) {
+		printf("SPD revision %02X not verified by this code\n",
+		       spd_rev);
+	}
 
 	/*
 	 * Calculate checksum