Signed-off-by: Graeme Russ <graeme.russ@gmail.com>master
Graeme Russ
16 years ago
committed by
Tom Rix
parent
5aaeb2a3d4
commit
bd9806d696
@ -0,0 +1,271 @@ |
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/*
|
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* |
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* (C) Copyright 2002 |
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <pci.h> |
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#include <asm/io.h> |
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#include <asm/pci.h> |
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#include <asm/ic/sc520.h> |
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#include <asm/ic/pci.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#undef SC520_CDP_DEBUG |
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#ifdef SC520_CDP_DEBUG |
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#define PRINTF(fmt,args...) printf (fmt ,##args) |
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#else |
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#define PRINTF(fmt,args...) |
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#endif |
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static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
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{ |
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/* a configurable lists of irqs to steal
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* when we need one (a board with more pci interrupt pins |
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* would use a larger table */ |
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static int irq_list[] = { |
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CONFIG_SYS_FIRST_PCI_IRQ, |
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CONFIG_SYS_SECOND_PCI_IRQ, |
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CONFIG_SYS_THIRD_PCI_IRQ, |
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CONFIG_SYS_FORTH_PCI_IRQ |
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}; |
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static int next_irq_index=0; |
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uchar tmp_pin; |
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int pin; |
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); |
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pin = tmp_pin; |
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pin-=1; /* pci config space use 1-based numbering */ |
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if (-1 == pin) { |
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return; /* device use no irq */ |
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} |
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|
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/* map device number + pin to a pin on the sc520 */ |
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switch (PCI_DEV(dev)) { |
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case 20: |
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pin+=SC520_PCI_INTA; |
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break; |
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case 19: |
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pin+=SC520_PCI_INTB; |
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break; |
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case 18: |
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pin+=SC520_PCI_INTC; |
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break; |
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case 17: |
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pin+=SC520_PCI_INTD; |
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break; |
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default: |
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return; |
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} |
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pin&=3; /* wrap around */ |
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if (sc520_pci_ints[pin] == -1) { |
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/* re-route one interrupt for us */ |
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if (next_irq_index > 3) { |
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return; |
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} |
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if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { |
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return; |
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} |
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next_irq_index++; |
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} |
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if (-1 != sc520_pci_ints[pin]) { |
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, |
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sc520_pci_ints[pin]); |
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} |
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PRINTF("fixup_irq: device %d pin %c irq %d\n", |
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PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); |
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} |
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static struct pci_controller sc520_cdp_hose = { |
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fixup_irq: pci_sc520_cdp_fixup_irq, |
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}; |
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void pci_init_board(void) |
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{ |
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pci_sc520_init(&sc520_cdp_hose); |
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} |
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/*
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* This function should map a chunk of size bytes |
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* of the system address space to the ISA bus |
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* |
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* The function will return the memory address |
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* as seen by the host (which may very will be the |
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* same as the bus address) |
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*/ |
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u32 isa_map_rom(u32 bus_addr, int size) |
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{ |
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u32 par; |
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PRINTF("isa_map_rom asked to map %d bytes at %x\n", |
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size, bus_addr); |
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par = size; |
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if (par < 0x80000) { |
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par = 0x80000; |
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} |
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par >>= 12; |
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par--; |
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par&=0x7f; |
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par <<= 18; |
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par |= (bus_addr>>12); |
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par |= 0x50000000; |
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PRINTF ("setting PAR11 to %x\n", par); |
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/* Map rom 0x10000 with PAR1 */ |
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sc520_mmcr->par[11] = par; |
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return bus_addr; |
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} |
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/*
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* this function removed any mapping created |
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* with pci_get_rom_window() |
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*/ |
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void isa_unmap_rom(u32 addr) |
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{ |
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PRINTF("isa_unmap_rom asked to unmap %x", addr); |
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if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { |
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sc520_mmcr->par[11] = 0; |
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PRINTF(" done\n"); |
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return; |
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} |
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PRINTF(" not ours\n"); |
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} |
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#define PCI_ROM_TEMP_SPACE 0x10000 |
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/*
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* This function should map a chunk of size bytes |
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* of the system address space to the PCI bus, |
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* suitable to map PCI ROMS (bus address < 16M) |
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* the function will return the host memory address |
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* which should be converted into a bus address |
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* before used to configure the PCI rom address |
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* decoder |
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*/ |
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u32 pci_get_rom_window(struct pci_controller *hose, int size) |
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{ |
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u32 par; |
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par = size; |
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if (par < 0x80000) { |
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par = 0x80000; |
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} |
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par >>= 16; |
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par--; |
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par&=0x7ff; |
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par <<= 14; |
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par |= (PCI_ROM_TEMP_SPACE>>16); |
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par |= 0x72000000; |
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PRINTF ("setting PAR1 to %x\n", par); |
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/* Map rom 0x10000 with PAR1 */ |
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sc520_mmcr->par[1] = par; |
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return PCI_ROM_TEMP_SPACE; |
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} |
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/*
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* this function removed any mapping created |
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* with pci_get_rom_window() |
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*/ |
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void pci_remove_rom_window(struct pci_controller *hose, u32 addr) |
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{ |
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PRINTF("pci_remove_rom_window: %x", addr); |
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if (addr == PCI_ROM_TEMP_SPACE) { |
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sc520_mmcr->par[1] = 0; |
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PRINTF(" done\n"); |
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return; |
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} |
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PRINTF(" not ours\n"); |
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} |
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/*
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* This function is called in order to provide acces to the |
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* legacy video I/O ports on the PCI bus. |
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* After this function accesses to I/O ports 0x3b0-0x3bb and |
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* 0x3c0-0x3df shuld result in transactions on the PCI bus. |
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* |
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*/ |
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int pci_enable_legacy_video_ports(struct pci_controller *hose) |
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{ |
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/* Map video memory to 0xa0000*/ |
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sc520_mmcr->par[0] = 0x7200400a; |
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/* forward all I/O accesses to PCI */ |
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sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; |
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/* so we map away all io ports to pci (only way to access pci io
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* below 0x400. But then we have to map back the portions that we dont |
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* use so that the generate cycles on the GPIO bus where the sio and |
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* ISA slots are connected, this requre the use of several PAR registers |
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*/ |
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/* bring 0x100 - 0x1ef back to ISA using PAR5 */ |
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sc520_mmcr->par[5] = 0x30ef0100; |
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/* IDE use 1f0-1f7 */ |
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/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ |
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sc520_mmcr->par[6] = 0x30ff01f8; |
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/* com2 use 2f8-2ff */ |
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/* bring 0x300 - 0x3af back to ISA using PAR7 */ |
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sc520_mmcr->par[7] = 0x30af0300; |
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/* vga use 3b0-3bb */ |
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/* bring 0x3bc - 0x3bf back to ISA using PAR8 */ |
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sc520_mmcr->par[8] = 0x300303bc; |
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/* vga use 3c0-3df */ |
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/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ |
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sc520_mmcr->par[9] = 0x301503e0; |
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/* ide use 3f6 */ |
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/* bring 0x3f7 back to ISA using PAR10 */ |
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sc520_mmcr->par[10] = 0x300003f7; |
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/* com1 use 3f8-3ff */ |
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return 0; |
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} |
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@ -0,0 +1,323 @@ |
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/*
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* |
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* (C) Copyright 2002 |
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <ds1722.h> |
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#include <asm/io.h> |
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#include <asm/pci.h> |
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#include <asm/ic/sc520.h> |
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#include <asm/ic/pci.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
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{ |
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int version = sc520_mmcr->sysinfo; |
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/* a configurable lists of irqs to steal
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* when we need one (a board with more pci interrupt pins |
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* would use a larger table */ |
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static int irq_list[] = { |
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CONFIG_SYS_FIRST_PCI_IRQ, |
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CONFIG_SYS_SECOND_PCI_IRQ, |
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CONFIG_SYS_THIRD_PCI_IRQ, |
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CONFIG_SYS_FORTH_PCI_IRQ |
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}; |
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static int next_irq_index=0; |
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uchar tmp_pin; |
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int pin; |
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); |
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pin = tmp_pin; |
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pin-=1; /* pci config space use 1-based numbering */ |
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if (-1 == pin) { |
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return; /* device use no irq */ |
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} |
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/* map device number + pin to a pin on the sc520 */ |
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switch (PCI_DEV(dev)) { |
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case 6: /* ETH0 */ |
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pin+=SC520_PCI_INTA; |
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break; |
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case 7: /* ETH1 */ |
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pin+=SC520_PCI_INTB; |
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break; |
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case 8: /* Crypto */ |
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pin+=SC520_PCI_INTC; |
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break; |
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case 9: /* PMC slot */ |
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pin+=SC520_PCI_INTD; |
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break; |
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case 10: /* PC-Card */ |
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if (version < 10) { |
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pin+=SC520_PCI_INTD; |
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} else { |
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pin+=SC520_PCI_INTC; |
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} |
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break; |
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default: |
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return; |
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} |
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pin&=3; /* wrap around */ |
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if (sc520_pci_ints[pin] == -1) { |
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/* re-route one interrupt for us */ |
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if (next_irq_index > 3) { |
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return; |
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} |
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if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { |
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return; |
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} |
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next_irq_index++; |
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} |
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if (-1 != sc520_pci_ints[pin]) { |
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, |
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sc520_pci_ints[pin]); |
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} |
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#if 0 |
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printf("fixup_irq: device %d pin %c irq %d\n", |
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PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); |
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#endif |
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} |
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static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, |
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pci_dev_t dev, struct pci_config_table *te) |
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{ |
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u32 io_base; |
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u32 temp; |
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pciauto_config_device(hose, dev); |
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ |
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pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ |
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pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ |
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pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ |
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pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ |
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pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ |
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pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ |
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pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ |
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pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ |
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/* route MF0 to ~INT and MF3 to IRQ7
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* reserve all others */ |
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pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); |
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pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ |
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pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ |
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if (te->device != 0xac56) { |
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pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ |
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pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ |
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pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ |
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pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ |
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pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ |
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} else { |
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pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ |
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} |
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pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ |
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pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); |
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io_base &= ~0xfL; |
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writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ |
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writel(0, io_base+0x10); /* CLKRUN default */ |
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writel(0, io_base+0x20); /* CLKRUN default */ |
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} |
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static struct pci_config_table pci_sc520_spunk_config_table[] = { |
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{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, |
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{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, |
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{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} |
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}; |
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static struct pci_controller sc520_spunk_hose = { |
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fixup_irq: pci_sc520_spunk_fixup_irq, |
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config_table: pci_sc520_spunk_config_table, |
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first_busno: 0x00, |
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last_busno: 0xff, |
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}; |
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void pci_init_board(void) |
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{ |
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pci_sc520_init(&sc520_spunk_hose); |
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} |
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|
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/*
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* This function should map a chunk of size bytes |
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* of the system address space to the ISA bus |
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* |
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* The function will return the memory address |
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* as seen by the host (which may very will be the |
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* same as the bus address) |
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*/ |
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u32 isa_map_rom(u32 bus_addr, int size) |
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{ |
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u32 par; |
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printf("isa_map_rom asked to map %d bytes at %x\n", |
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size, bus_addr); |
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par = size; |
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if (par < 0x80000) { |
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par = 0x80000; |
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} |
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par >>= 12; |
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par--; |
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par&=0x7f; |
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par <<= 18; |
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par |= (bus_addr>>12); |
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par |= 0x50000000; |
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printf ("setting PAR11 to %x\n", par); |
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/* Map rom 0x10000 with PAR1 */ |
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sc520_mmcr->par[11] = par; |
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return bus_addr; |
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} |
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|
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/*
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* this function removed any mapping created |
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* with pci_get_rom_window() |
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*/ |
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void isa_unmap_rom(u32 addr) |
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{ |
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printf("isa_unmap_rom asked to unmap %x", addr); |
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if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) { |
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sc520_mmcr->par[11] = 0; |
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printf(" done\n"); |
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return; |
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} |
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printf(" not ours\n"); |
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} |
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|
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#define PCI_ROM_TEMP_SPACE 0x10000 |
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/*
|
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* This function should map a chunk of size bytes |
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* of the system address space to the PCI bus, |
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* suitable to map PCI ROMS (bus address < 16M) |
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* the function will return the host memory address |
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* which should be converted into a bus address |
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* before used to configure the PCI rom address |
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* decoder |
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*/ |
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u32 pci_get_rom_window(struct pci_controller *hose, int size) |
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{ |
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u32 par; |
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|
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par = size; |
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if (par < 0x80000) { |
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par = 0x80000; |
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} |
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par >>= 16; |
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par--; |
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par&=0x7ff; |
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par <<= 14; |
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par |= (PCI_ROM_TEMP_SPACE>>16); |
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par |= 0x72000000; |
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|
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printf ("setting PAR1 to %x\n", par); |
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|
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/* Map rom 0x10000 with PAR1 */ |
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sc520_mmcr->par[1] = par; |
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|
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return PCI_ROM_TEMP_SPACE; |
||||
} |
||||
|
||||
/*
|
||||
* this function removed any mapping created |
||||
* with pci_get_rom_window() |
||||
*/ |
||||
void pci_remove_rom_window(struct pci_controller *hose, u32 addr) |
||||
{ |
||||
printf("pci_remove_rom_window: %x", addr); |
||||
if (addr == PCI_ROM_TEMP_SPACE) { |
||||
sc520_mmcr->par[1] = 0; |
||||
printf(" done\n"); |
||||
return; |
||||
} |
||||
printf(" not ours\n"); |
||||
|
||||
} |
||||
|
||||
/*
|
||||
* This function is called in order to provide acces to the |
||||
* legacy video I/O ports on the PCI bus. |
||||
* After this function accesses to I/O ports 0x3b0-0x3bb and |
||||
* 0x3c0-0x3df shuld result in transactions on the PCI bus. |
||||
* |
||||
*/ |
||||
int pci_enable_legacy_video_ports(struct pci_controller *hose) |
||||
{ |
||||
/* Map video memory to 0xa0000*/ |
||||
sc520_mmcr->par[0] = 0x7200400a; |
||||
|
||||
/* forward all I/O accesses to PCI */ |
||||
sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI; |
||||
|
||||
|
||||
/* so we map away all io ports to pci (only way to access pci io
|
||||
* below 0x400. But then we have to map back the portions that we dont |
||||
* use so that the generate cycles on the GPIO bus where the sio and |
||||
* ISA slots are connected, this requre the use of several PAR registers |
||||
*/ |
||||
|
||||
/* bring 0x100 - 0x2f7 back to ISA using PAR5 */ |
||||
sc520_mmcr->par[5] = 0x31f70100; |
||||
|
||||
/* com2 use 2f8-2ff */ |
||||
|
||||
/* bring 0x300 - 0x3af back to ISA using PAR7 */ |
||||
sc520_mmcr->par[7] = 0x30af0300; |
||||
|
||||
/* vga use 3b0-3bb */ |
||||
|
||||
/* bring 0x3bc - 0x3bf back to ISA using PAR8 */ |
||||
sc520_mmcr->par[8] = 0x300303bc; |
||||
|
||||
/* vga use 3c0-3df */ |
||||
|
||||
/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ |
||||
sc520_mmcr->par[9] = 0x301703e0; |
||||
|
||||
/* com1 use 3f8-3ff */ |
||||
|
||||
return 0; |
||||
} |
||||
Loading…
Reference in new issue