@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
}
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
static void set_ddr_wrlvl_cntl ( fsl_ddr_cfg_regs_t * ddr ,
unsigned int wrlvl_en )
static void set_ddr_wrlvl_cntl ( fsl_ddr_cfg_regs_t * ddr , unsigned int wrlvl_en ,
const memctl_options_t * popts )
{
/*
* First DQS pulse rising edge after margining mode
@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
/* tWL_DQSEN min = 25 nCK, we set it 32 */
wrlvl_dqsen = 0x5 ;
/*
* Write leveling sample time at least need 14 clocks
* due to tWLO = 9 , we set it 15 clocks
* Write leveling sample time at least need 6 clocks
* higher than tWLO to allow enough time for progagation
* delay and sampling the prime data bits .
*/
wrlvl_smpl = 0xf ;
/*
@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
* Write leveling start time
* The value use for the DQS_ADJUST for the first sample
* when write leveling is enabled .
* we set it 1 clock delay
*/
wrlvl_start = 0x8 ;
/*
* Override the write leveling sample and start time
* according to specific board
*/
if ( popts - > wrlvl_override ) {
wrlvl_smpl = popts - > wrlvl_sample ;
wrlvl_start = popts - > wrlvl_start ;
}
}
ddr - > ddr_wrlvl_cntl = ( 0
@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_timing_cfg_5 ( ddr ) ;
set_ddr_zq_cntl ( ddr , zq_en ) ;
set_ddr_wrlvl_cntl ( ddr , wrlvl_en ) ;
set_ddr_wrlvl_cntl ( ddr , wrlvl_en , popts ) ;
set_ddr_sr_cntr ( ddr , sr_it ) ;