Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>master
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#
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# (C) Copyright 2016 Google, Inc
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# Written by Simon Glass <sjg@chromium.org>
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#
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obj-y += cpu.o
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obj-y += interrupt.o
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@ -0,0 +1,534 @@ |
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/*
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* (C) Copyright 2008-2011 |
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* Graeme Russ, <graeme.russ@gmail.com> |
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* |
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* (C) Copyright 2002 |
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* Part of this file is adapted from coreboot |
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* src/arch/x86/lib/cpu.c |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <asm/control_regs.h> |
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#include <asm/cpu.h> |
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#include <asm/mp.h> |
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#include <asm/msr.h> |
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#include <asm/mtrr.h> |
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#include <asm/processor-flags.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Constructor for a conventional segment GDT (or LDT) entry |
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* This is a macro so it can be used in initialisers |
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*/ |
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#define GDT_ENTRY(flags, base, limit) \ |
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((((base) & 0xff000000ULL) << (56-24)) | \
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(((flags) & 0x0000f0ffULL) << 40) | \
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(((limit) & 0x000f0000ULL) << (48-16)) | \
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(((base) & 0x00ffffffULL) << 16) | \
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(((limit) & 0x0000ffffULL))) |
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struct gdt_ptr { |
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u16 len; |
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u32 ptr; |
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} __packed; |
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struct cpu_device_id { |
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unsigned vendor; |
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unsigned device; |
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}; |
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struct cpuinfo_x86 { |
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uint8_t x86; /* CPU family */ |
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uint8_t x86_vendor; /* CPU vendor */ |
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uint8_t x86_model; |
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uint8_t x86_mask; |
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}; |
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/*
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* List of cpu vendor strings along with their normalized |
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* id values. |
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*/ |
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static const struct { |
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int vendor; |
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const char *name; |
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} x86_vendors[] = { |
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{ X86_VENDOR_INTEL, "GenuineIntel", }, |
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{ X86_VENDOR_CYRIX, "CyrixInstead", }, |
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{ X86_VENDOR_AMD, "AuthenticAMD", }, |
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{ X86_VENDOR_UMC, "UMC UMC UMC ", }, |
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{ X86_VENDOR_NEXGEN, "NexGenDriven", }, |
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{ X86_VENDOR_CENTAUR, "CentaurHauls", }, |
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{ X86_VENDOR_RISE, "RiseRiseRise", }, |
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{ X86_VENDOR_TRANSMETA, "GenuineTMx86", }, |
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{ X86_VENDOR_TRANSMETA, "TransmetaCPU", }, |
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{ X86_VENDOR_NSC, "Geode by NSC", }, |
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{ X86_VENDOR_SIS, "SiS SiS SiS ", }, |
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}; |
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static void load_ds(u32 segment) |
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{ |
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asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); |
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} |
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static void load_es(u32 segment) |
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{ |
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asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); |
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} |
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static void load_fs(u32 segment) |
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{ |
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asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); |
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} |
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static void load_gs(u32 segment) |
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{ |
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asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); |
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} |
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static void load_ss(u32 segment) |
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{ |
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asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); |
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} |
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static void load_gdt(const u64 *boot_gdt, u16 num_entries) |
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{ |
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struct gdt_ptr gdt; |
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gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; |
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gdt.ptr = (ulong)boot_gdt; |
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asm volatile("lgdtl %0\n" : : "m" (gdt)); |
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} |
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void arch_setup_gd(gd_t *new_gd) |
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{ |
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u64 *gdt_addr; |
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gdt_addr = new_gd->arch.gdt; |
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/*
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* CS: code, read/execute, 4 GB, base 0 |
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* |
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* Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS |
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*/ |
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gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); |
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gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); |
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/* DS: data, read/write, 4 GB, base 0 */ |
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gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); |
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/* FS: data, read/write, 4 GB, base (Global Data Pointer) */ |
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new_gd->arch.gd_addr = new_gd; |
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gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, |
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(ulong)&new_gd->arch.gd_addr, 0xfffff); |
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/* 16-bit CS: code, read/execute, 64 kB, base 0 */ |
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gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); |
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/* 16-bit DS: data, read/write, 64 kB, base 0 */ |
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gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); |
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gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); |
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gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); |
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load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); |
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load_ds(X86_GDT_ENTRY_32BIT_DS); |
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load_es(X86_GDT_ENTRY_32BIT_DS); |
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load_gs(X86_GDT_ENTRY_32BIT_DS); |
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load_ss(X86_GDT_ENTRY_32BIT_DS); |
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load_fs(X86_GDT_ENTRY_32BIT_FS); |
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} |
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#ifdef CONFIG_HAVE_FSP |
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/*
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* Setup FSP execution environment GDT |
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* |
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* Per Intel FSP external architecture specification, before calling any FSP |
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* APIs, we need make sure the system is in flat 32-bit mode and both the code |
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* and data selectors should have full 4GB access range. Here we reuse the one |
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* we used in arch/x86/cpu/start16.S, and reload the segement registers. |
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*/ |
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void setup_fsp_gdt(void) |
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{ |
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load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); |
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load_ds(X86_GDT_ENTRY_32BIT_DS); |
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load_ss(X86_GDT_ENTRY_32BIT_DS); |
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load_es(X86_GDT_ENTRY_32BIT_DS); |
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load_fs(X86_GDT_ENTRY_32BIT_DS); |
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load_gs(X86_GDT_ENTRY_32BIT_DS); |
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} |
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#endif |
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected |
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* by the fact that they preserve the flags across the division of 5/2. |
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* PII and PPro exhibit this behavior too, but they have cpuid available. |
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*/ |
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/*
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* Perform the Cyrix 5/2 test. A Cyrix won't change |
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* the flags, while other 486 chips will. |
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*/ |
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static inline int test_cyrix_52div(void) |
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{ |
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unsigned int test; |
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__asm__ __volatile__( |
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"sahf\n\t" /* clear flags (%eax = 0x0005) */ |
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"div %b2\n\t" /* divide 5 by 2 */ |
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"lahf" /* store flags into %ah */ |
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: "=a" (test) |
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: "0" (5), "q" (2) |
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: "cc"); |
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/* AH is 0x02 on Cyrix after the divide.. */ |
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return (unsigned char) (test >> 8) == 0x02; |
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} |
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/*
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* Detect a NexGen CPU running without BIOS hypercode new enough |
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* to have CPUID. (Thanks to Herbert Oppmann) |
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*/ |
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static int deep_magic_nexgen_probe(void) |
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{ |
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int ret; |
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__asm__ __volatile__ ( |
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" movw $0x5555, %%ax\n" |
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" xorw %%dx,%%dx\n" |
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" movw $2, %%cx\n" |
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" divw %%cx\n" |
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" movl $0, %%eax\n" |
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" jnz 1f\n" |
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" movl $1, %%eax\n" |
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"1:\n" |
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: "=a" (ret) : : "cx", "dx"); |
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return ret; |
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} |
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static bool has_cpuid(void) |
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{ |
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return flag_is_changeable_p(X86_EFLAGS_ID); |
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} |
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static bool has_mtrr(void) |
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{ |
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return cpuid_edx(0x00000001) & (1 << 12) ? true : false; |
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} |
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static int build_vendor_name(char *vendor_name) |
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{ |
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struct cpuid_result result; |
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result = cpuid(0x00000000); |
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unsigned int *name_as_ints = (unsigned int *)vendor_name; |
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name_as_ints[0] = result.ebx; |
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name_as_ints[1] = result.edx; |
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name_as_ints[2] = result.ecx; |
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return result.eax; |
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} |
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static void identify_cpu(struct cpu_device_id *cpu) |
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{ |
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char vendor_name[16]; |
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int i; |
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vendor_name[0] = '\0'; /* Unset */ |
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cpu->device = 0; /* fix gcc 4.4.4 warning */ |
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/* Find the id and vendor_name */ |
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if (!has_cpuid()) { |
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/* Its a 486 if we can modify the AC flag */ |
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if (flag_is_changeable_p(X86_EFLAGS_AC)) |
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cpu->device = 0x00000400; /* 486 */ |
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else |
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cpu->device = 0x00000300; /* 386 */ |
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if ((cpu->device == 0x00000400) && test_cyrix_52div()) { |
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memcpy(vendor_name, "CyrixInstead", 13); |
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/* If we ever care we can enable cpuid here */ |
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} |
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/* Detect NexGen with old hypercode */ |
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else if (deep_magic_nexgen_probe()) |
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memcpy(vendor_name, "NexGenDriven", 13); |
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} |
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if (has_cpuid()) { |
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int cpuid_level; |
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cpuid_level = build_vendor_name(vendor_name); |
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vendor_name[12] = '\0'; |
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/* Intel-defined flags: level 0x00000001 */ |
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if (cpuid_level >= 0x00000001) { |
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cpu->device = cpuid_eax(0x00000001); |
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} else { |
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/* Have CPUID level 0 only unheard of */ |
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cpu->device = 0x00000400; |
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} |
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} |
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cpu->vendor = X86_VENDOR_UNKNOWN; |
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for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { |
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if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { |
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cpu->vendor = x86_vendors[i].vendor; |
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break; |
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} |
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} |
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} |
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static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) |
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{ |
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c->x86 = (tfms >> 8) & 0xf; |
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c->x86_model = (tfms >> 4) & 0xf; |
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c->x86_mask = tfms & 0xf; |
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if (c->x86 == 0xf) |
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c->x86 += (tfms >> 20) & 0xff; |
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if (c->x86 >= 0x6) |
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c->x86_model += ((tfms >> 16) & 0xF) << 4; |
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} |
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u32 cpu_get_family_model(void) |
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{ |
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return gd->arch.x86_device & 0x0fff0ff0; |
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} |
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u32 cpu_get_stepping(void) |
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{ |
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return gd->arch.x86_mask; |
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} |
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int x86_cpu_init_f(void) |
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{ |
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const u32 em_rst = ~X86_CR0_EM; |
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const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; |
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if (ll_boot_init()) { |
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/* initialize FPU, reset EM, set MP and NE */ |
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asm ("fninit\n" \
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"movl %%cr0, %%eax\n" \
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"andl %0, %%eax\n" \
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"orl %1, %%eax\n" \
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"movl %%eax, %%cr0\n" \
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: : "i" (em_rst), "i" (mp_ne_set) : "eax"); |
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} |
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/* identify CPU via cpuid and store the decoded info into gd->arch */ |
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if (has_cpuid()) { |
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struct cpu_device_id cpu; |
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struct cpuinfo_x86 c; |
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identify_cpu(&cpu); |
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get_fms(&c, cpu.device); |
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gd->arch.x86 = c.x86; |
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gd->arch.x86_vendor = cpu.vendor; |
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gd->arch.x86_model = c.x86_model; |
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gd->arch.x86_mask = c.x86_mask; |
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gd->arch.x86_device = cpu.device; |
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gd->arch.has_mtrr = has_mtrr(); |
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} |
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/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ |
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gd->pci_ram_top = 0x80000000U; |
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/* Configure fixed range MTRRs for some legacy regions */ |
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if (gd->arch.has_mtrr) { |
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u64 mtrr_cap; |
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mtrr_cap = native_read_msr(MTRR_CAP_MSR); |
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if (mtrr_cap & MTRR_CAP_FIX) { |
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/* Mark the VGA RAM area as uncacheable */ |
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native_write_msr(MTRR_FIX_16K_A0000_MSR, |
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MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), |
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MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); |
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/*
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* Mark the PCI ROM area as cacheable to improve ROM |
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* execution performance. |
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*/ |
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native_write_msr(MTRR_FIX_4K_C0000_MSR, |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); |
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native_write_msr(MTRR_FIX_4K_C8000_MSR, |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); |
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native_write_msr(MTRR_FIX_4K_D0000_MSR, |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); |
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native_write_msr(MTRR_FIX_4K_D8000_MSR, |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), |
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); |
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/* Enable the fixed range MTRRs */ |
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msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); |
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} |
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} |
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#ifdef CONFIG_I8254_TIMER |
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/* Set up the i8254 timer if required */ |
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i8254_init(); |
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#endif |
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return 0; |
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} |
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void x86_enable_caches(void) |
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{ |
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unsigned long cr0; |
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cr0 = read_cr0(); |
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cr0 &= ~(X86_CR0_NW | X86_CR0_CD); |
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write_cr0(cr0); |
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wbinvd(); |
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} |
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void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); |
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|
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void x86_disable_caches(void) |
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{ |
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unsigned long cr0; |
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cr0 = read_cr0(); |
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cr0 |= X86_CR0_NW | X86_CR0_CD; |
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wbinvd(); |
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write_cr0(cr0); |
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wbinvd(); |
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} |
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void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); |
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|
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int dcache_status(void) |
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{ |
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return !(read_cr0() & X86_CR0_CD); |
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} |
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|
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void cpu_enable_paging_pae(ulong cr3) |
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{ |
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__asm__ __volatile__( |
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/* Load the page table address */ |
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"movl %0, %%cr3\n" |
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/* Enable pae */ |
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"movl %%cr4, %%eax\n" |
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"orl $0x00000020, %%eax\n" |
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"movl %%eax, %%cr4\n" |
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/* Enable paging */ |
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"movl %%cr0, %%eax\n" |
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"orl $0x80000000, %%eax\n" |
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"movl %%eax, %%cr0\n" |
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: |
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: "r" (cr3) |
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: "eax"); |
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} |
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|
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void cpu_disable_paging_pae(void) |
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{ |
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/* Turn off paging */ |
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__asm__ __volatile__ ( |
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/* Disable paging */ |
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"movl %%cr0, %%eax\n" |
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"andl $0x7fffffff, %%eax\n" |
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"movl %%eax, %%cr0\n" |
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/* Disable pae */ |
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"movl %%cr4, %%eax\n" |
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"andl $0xffffffdf, %%eax\n" |
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"movl %%eax, %%cr4\n" |
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: |
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: |
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: "eax"); |
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} |
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|
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static bool can_detect_long_mode(void) |
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{ |
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return cpuid_eax(0x80000000) > 0x80000000UL; |
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} |
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|
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static bool has_long_mode(void) |
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{ |
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return cpuid_edx(0x80000001) & (1 << 29) ? true : false; |
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} |
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|
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int cpu_has_64bit(void) |
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{ |
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return has_cpuid() && can_detect_long_mode() && |
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has_long_mode(); |
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} |
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|
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#define PAGETABLE_SIZE (6 * 4096) |
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|
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/**
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* build_pagetable() - build a flat 4GiB page table structure for 64-bti mode |
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* |
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* @pgtable: Pointer to a 24iKB block of memory |
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*/ |
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static void build_pagetable(uint32_t *pgtable) |
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{ |
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uint i; |
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|
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memset(pgtable, '\0', PAGETABLE_SIZE); |
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|
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/* Level 4 needs a single entry */ |
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pgtable[0] = (ulong)&pgtable[1024] + 7; |
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|
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/* Level 3 has one 64-bit entry for each GiB of memory */ |
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for (i = 0; i < 4; i++) |
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pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; |
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|
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/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ |
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for (i = 0; i < 2048; i++) |
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pgtable[2048 + i * 2] = 0x183 + (i << 21UL); |
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} |
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|
||||
int cpu_jump_to_64bit(ulong setup_base, ulong target) |
||||
{ |
||||
uint32_t *pgtable; |
||||
|
||||
pgtable = memalign(4096, PAGETABLE_SIZE); |
||||
if (!pgtable) |
||||
return -ENOMEM; |
||||
|
||||
build_pagetable(pgtable); |
||||
cpu_call64((ulong)pgtable, setup_base, target); |
||||
free(pgtable); |
||||
|
||||
return -EFAULT; |
||||
} |
||||
|
||||
#ifdef CONFIG_SMP |
||||
static int enable_smis(struct udevice *cpu, void *unused) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static struct mp_flight_record mp_steps[] = { |
||||
MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), |
||||
/* Wait for APs to finish initialization before proceeding */ |
||||
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), |
||||
}; |
||||
|
||||
int x86_mp_init(void) |
||||
{ |
||||
struct mp_params mp_params; |
||||
|
||||
mp_params.parallel_microcode_load = 0, |
||||
mp_params.flight_plan = &mp_steps[0]; |
||||
mp_params.num_records = ARRAY_SIZE(mp_steps); |
||||
mp_params.microcode_pointer = 0; |
||||
|
||||
if (mp_init(&mp_params)) { |
||||
printf("Warning: MP init failure\n"); |
||||
return -EIO; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
Loading…
Reference in new issue