Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>master
Timur Tabi
18 years ago
committed by
Kim Phillips
parent
d239d74b1c
commit
be5e61815d
@ -1,423 +0,0 @@ |
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/*
|
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* (C) Copyright 2006 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2003,Motorola Inc. |
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* Xianghua Xiao <x.xiao@motorola.com> |
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* Adapted for Motorola 85xx chip. |
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* |
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* (C) Copyright 2003 |
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* Gleb Natapov <gnatapov@mrv.com> |
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* Some bits are taken from linux driver writen by adrian@humboldt.co.uk |
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* |
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* Hardware I2C driver for MPC107 PCI bridge. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Change log: |
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* |
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* 20050101: Eran Liberty (liberty@freescale.com) |
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* Initial file creating (porting from 85XX & 8260) |
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* 20060601: Dave Liu (daveliu@freescale.com) |
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* Unified variable names for mpc83xx |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#ifdef CONFIG_HARD_I2C |
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#include <i2c.h> |
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#include <asm/i2c.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 1. This is necessary because the DDR initialization |
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* runs from ROM, and we can't switch buses because we can't modify |
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* the i2c_dev variable. Everything gets straightened out once i2c_init |
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* is called from RAM. */ |
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#ifndef CFG_SPD_BUS_NUM |
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#define CFG_SPD_BUS_NUM 1 |
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#endif |
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static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM; |
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#if CFG_SPD_BUS_NUM == 1 |
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static volatile i2c_t *i2c_dev = I2C_1; |
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#else |
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static volatile i2c_t *i2c_dev = I2C_2; |
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#endif |
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static int i2c_bus_speed[2] = {0, 0}; |
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/*
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* Map the frequency divider to the FDR. This data is taken from table 17-5 |
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* of the MPC8349EA reference manual, with duplicates removed. |
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*/ |
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static struct { |
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unsigned int divider; |
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u8 fdr; |
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} i2c_speed_map[] = |
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{ |
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{0, 0x20}, |
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{256, 0x20}, |
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{288, 0x21}, |
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{320, 0x22}, |
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{352, 0x23}, |
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{384, 0x24}, |
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{416, 0x01}, |
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{448, 0x25}, |
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{480, 0x02}, |
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{512, 0x26}, |
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{576, 0x27}, |
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{640, 0x28}, |
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{704, 0x05}, |
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{768, 0x29}, |
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{832, 0x06}, |
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{896, 0x2A}, |
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{1024, 0x2B}, |
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{1152, 0x08}, |
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{1280, 0x2C}, |
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{1536, 0x2D}, |
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{1792, 0x2E}, |
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{1920, 0x0B}, |
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{2048, 0x2F}, |
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{2304, 0x0C}, |
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{2560, 0x30}, |
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{3072, 0x31}, |
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{3584, 0x32}, |
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{3840, 0x0F}, |
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{4096, 0x33}, |
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{4608, 0x10}, |
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{5120, 0x34}, |
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{6144, 0x35}, |
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{7168, 0x36}, |
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{7680, 0x13}, |
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{8192, 0x37}, |
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{9216, 0x14}, |
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{10240, 0x38}, |
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{12288, 0x39}, |
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{14336, 0x3A}, |
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{15360, 0x17}, |
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{16384, 0x3B}, |
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{18432, 0x18}, |
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{20480, 0x3C}, |
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{24576, 0x3D}, |
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{28672, 0x3E}, |
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{30720, 0x1B}, |
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{32768, 0x3F}, |
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{36864, 0x1C}, |
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{40960, 0x1D}, |
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{49152, 0x1E}, |
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{61440, 0x1F}, |
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{-1, 0x1F} |
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}; |
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#define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0])) |
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static int set_speed(unsigned int speed) |
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{ |
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unsigned long i2c_clk; |
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unsigned int divider, i; |
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u8 fdr = 0x3F; |
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i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk; |
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divider = i2c_clk / speed; |
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/* Scan i2c_speed_map[] for the closest matching divider.*/ |
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for (i = 0; i < NUM_I2C_SPEEDS-1; i++) { |
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/* Locate our divider in between two entries in i2c_speed_map[] */ |
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if ((divider >= i2c_speed_map[i].divider) && |
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(divider <= i2c_speed_map[i+1].divider)) { |
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/* Which one is closer? */ |
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if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) { |
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fdr = i2c_speed_map[i].fdr; |
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} else { |
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fdr = i2c_speed_map[i+1].fdr; |
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} |
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break; |
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} |
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} |
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writeb(fdr, &i2c_dev->fdr); |
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i2c_bus_speed[i2c_bus_num - 1] = speed; |
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return 0; |
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} |
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static void _i2c_init(int speed, int slaveadd) |
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{ |
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/* stop I2C controller */ |
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writeb(0x00 , &i2c_dev->cr); |
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/* set clock */ |
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set_speed(speed); |
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/* set default filter */ |
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writeb(IC2_FDR,&i2c_dev->dfsrr); |
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/* write slave address */ |
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writeb(slaveadd, &i2c_dev->adr); |
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/* clear status register */ |
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writeb(I2C_CR_MTX, &i2c_dev->sr); |
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/* start I2C controller */ |
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writeb(I2C_CR_MEN, &i2c_dev->cr); |
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} |
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void i2c_init(int speed, int slaveadd) |
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{ |
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/* Set both interfaces to the same speed and slave address */ |
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/* Note: This function gets called twice - before and after
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* relocation to RAM. The first time it's called, we are unable |
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* to change buses, so whichever one 'i2c_dev' was initialized to |
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* gets set twice. When run from RAM both buses get set properly */ |
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i2c_set_bus_num(1); |
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_i2c_init(speed, slaveadd); |
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#ifdef CFG_I2C2_OFFSET |
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i2c_set_bus_num(2); |
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_i2c_init(speed, slaveadd); |
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i2c_set_bus_num(1); |
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#endif /* CFG_I2C2_OFFSET */ |
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} |
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static __inline__ int |
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i2c_wait4bus (void) |
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{ |
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ulong timeval = get_timer (0); |
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while (readb(&i2c_dev->sr) & I2C_SR_MBB) { |
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if (get_timer (timeval) > I2C_TIMEOUT) { |
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return -1; |
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} |
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} |
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return 0; |
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} |
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static __inline__ int |
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i2c_wait (int write) |
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{ |
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u32 csr; |
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ulong timeval = get_timer(0); |
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do { |
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csr = readb(&i2c_dev->sr); |
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if (!(csr & I2C_SR_MIF)) |
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continue; |
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writeb(0x0, &i2c_dev->sr); |
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if (csr & I2C_SR_MAL) { |
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debug("i2c_wait: MAL\n"); |
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return -1; |
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} |
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if (!(csr & I2C_SR_MCF)) { |
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debug("i2c_wait: unfinished\n"); |
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return -1; |
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} |
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if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { |
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debug("i2c_wait: No RXACK\n"); |
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return -1; |
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} |
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return 0; |
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} while (get_timer (timeval) < I2C_TIMEOUT); |
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debug("i2c_wait: timed out\n"); |
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return -1; |
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} |
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static __inline__ int |
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i2c_write_addr (u8 dev, u8 dir, int rsta) |
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{ |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | |
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(rsta?I2C_CR_RSTA:0), |
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&i2c_dev->cr); |
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writeb((dev << 1) | dir, &i2c_dev->dr); |
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if (i2c_wait (I2C_WRITE) < 0) |
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return 0; |
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return 1; |
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} |
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static __inline__ int |
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__i2c_write (u8 *data, int length) |
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{ |
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int i; |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, |
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&i2c_dev->cr); |
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for (i=0; i < length; i++) { |
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writeb(data[i], &i2c_dev->dr); |
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if (i2c_wait (I2C_WRITE) < 0) |
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break; |
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} |
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return i; |
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} |
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static __inline__ int |
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__i2c_read (u8 *data, int length) |
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{ |
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int i; |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | |
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((length == 1) ? I2C_CR_TXAK : 0), |
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&i2c_dev->cr); |
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/* dummy read */ |
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readb(&i2c_dev->dr); |
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for (i=0; i < length; i++) { |
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if (i2c_wait (I2C_READ) < 0) |
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break; |
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/* Generate ack on last next to last byte */ |
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if (i == length - 2) |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | |
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I2C_CR_TXAK, |
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&i2c_dev->cr); |
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/* Generate stop on last byte */ |
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if (i == length - 1) |
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writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr); |
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data[i] = readb(&i2c_dev->dr); |
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} |
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return i; |
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} |
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int |
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i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) |
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{ |
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int i = 0; |
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u8 *a = (u8*)&addr; |
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if (i2c_wait4bus () < 0) |
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goto exit; |
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if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
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goto exit; |
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if (__i2c_write (&a[4 - alen], alen) != alen) |
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goto exit; |
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if (i2c_write_addr (dev, I2C_READ, 1) == 0) |
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goto exit; |
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i = __i2c_read (data, length); |
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exit: |
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writeb(I2C_CR_MEN, &i2c_dev->cr); |
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return !(i == length); |
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} |
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int |
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i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) |
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{ |
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int i = 0; |
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u8 *a = (u8*)&addr; |
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if (i2c_wait4bus () < 0) |
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goto exit; |
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if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
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goto exit; |
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if (__i2c_write (&a[4 - alen], alen) != alen) |
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goto exit; |
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i = __i2c_write (data, length); |
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exit: |
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writeb(I2C_CR_MEN, &i2c_dev->cr); |
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return !(i == length); |
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} |
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int i2c_probe (uchar chip) |
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{ |
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int tmp; |
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/*
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* Try to read the first location of the chip. The underlying |
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* driver doesn't appear to support sending just the chip address |
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* and looking for an <ACK> back. |
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*/ |
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udelay(10000); |
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return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); |
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} |
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uchar i2c_reg_read (uchar i2c_addr, uchar reg) |
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{ |
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uchar buf[1]; |
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i2c_read (i2c_addr, reg, 1, buf, 1); |
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return (buf[0]); |
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} |
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void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) |
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{ |
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i2c_write (i2c_addr, reg, 1, &val, 1); |
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} |
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int i2c_set_bus_num(unsigned int bus) |
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{ |
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if(bus == 1) |
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{ |
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i2c_dev = I2C_1; |
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} |
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#ifdef CFG_I2C2_OFFSET |
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else if(bus == 2) |
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{ |
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i2c_dev = I2C_2; |
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} |
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#endif |
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else |
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{ |
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return -1; |
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} |
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i2c_bus_num = bus; |
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return 0; |
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} |
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int i2c_set_bus_speed(unsigned int speed) |
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{ |
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return set_speed(speed); |
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} |
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unsigned int i2c_get_bus_num(void) |
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{ |
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return i2c_bus_num; |
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} |
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unsigned int i2c_get_bus_speed(void) |
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{ |
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return i2c_bus_speed[i2c_bus_num - 1]; |
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} |
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#endif /* CONFIG_HARD_I2C */ |
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@ -1,100 +0,0 @@ |
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/*
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* Freescale I2C Controller |
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* |
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* This software may be used and distributed according to the |
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* terms of the GNU Public License, Version 2, incorporated |
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* herein by reference. |
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* |
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* Copyright 2004 Freescale Semiconductor. |
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* (C) Copyright 2003, Motorola, Inc. |
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* author: Eran Liberty (liberty@freescale.com) |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef _ASM_I2C_H_ |
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#define _ASM_I2C_H_ |
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|
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#include <asm/types.h> |
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|
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typedef struct i2c |
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{ |
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u8 adr; /**< I2C slave address */ |
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#define I2C_ADR 0xFE |
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#define I2C_ADR_SHIFT 1 |
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#define I2C_ADR_RES ~(I2C_ADR) |
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u8 res0[3]; |
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u8 fdr; /**< I2C frequency divider register */ |
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#define IC2_FDR 0x3F |
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#define IC2_FDR_SHIFT 0 |
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#define IC2_FDR_RES ~(IC2_FDR) |
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u8 res1[3]; |
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u8 cr; /**< I2C control redister */ |
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#define I2C_CR_MEN 0x80 |
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#define I2C_CR_MIEN 0x40 |
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#define I2C_CR_MSTA 0x20 |
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#define I2C_CR_MTX 0x10 |
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#define I2C_CR_TXAK 0x08 |
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#define I2C_CR_RSTA 0x04 |
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#define I2C_CR_BCST 0x01 |
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u8 res2[3]; |
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u8 sr; /**< I2C status register */ |
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#define I2C_SR_MCF 0x80 |
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#define I2C_SR_MAAS 0x40 |
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#define I2C_SR_MBB 0x20 |
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#define I2C_SR_MAL 0x10 |
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#define I2C_SR_BCSTM 0x08 |
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#define I2C_SR_SRW 0x04 |
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#define I2C_SR_MIF 0x02 |
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#define I2C_SR_RXAK 0x01 |
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u8 res3[3]; |
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u8 dr; /**< I2C data register */ |
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#define I2C_DR 0xFF |
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#define I2C_DR_SHIFT 0 |
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#define I2C_DR_RES ~(I2C_DR) |
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u8 res4[3]; |
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u8 dfsrr; /**< I2C digital filter sampling rate register */ |
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#define I2C_DFSRR 0x3F |
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#define I2C_DFSRR_SHIFT 0 |
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#define I2C_DFSRR_RES ~(I2C_DR) |
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u8 res5[3]; |
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u8 res6[0xE8]; |
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} i2c_t; |
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|
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#ifndef CFG_HZ |
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#error CFG_HZ is not defined in /include/configs/${BOARD}.h |
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#endif |
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#define I2C_TIMEOUT (CFG_HZ/4) |
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|
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#ifndef CFG_IMMR |
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#error CFG_IMMR is not defined in /include/configs/${BOARD}.h |
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#endif |
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|
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#ifndef CFG_I2C_OFFSET |
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#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h |
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#endif |
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|
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#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET)) |
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|
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/* Optional support for second I2C bus */ |
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#ifdef CFG_I2C2_OFFSET |
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#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET)) |
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#endif /* CFG_I2C2_OFFSET */ |
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|
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#define I2C_READ 1 |
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#define I2C_WRITE 0 |
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|
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#endif /* _ASM_I2C_H_ */ |
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