Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

ARMV7: Restructure OMAP mmc driver to allow code sharing between OMAP3 and OMAP4

Browse Source 
The architecture independent header is moved to drivers/mmc, and the architecture
dependent headers reside in asm/arch-omap3 and asm/arch-omap4

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
master
Steve Sakoman 15 years ago committed by Sandeep Paulraj
parent d34efc767d
commit bec3dc7599
3 changed files with 181 additions and 5 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 171
      arch/arm/include/asm/arch-omap4/mmc_host_def.h
  2. 13
      drivers/mmc/omap3_mmc.c
  3. 2
      drivers/mmc/omap3_mmc.h

171
arch/arm/include/asm/arch-omap4/mmc_host_def.h
Unescape View File

@ -0,0 +1,171 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x4809C100
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
typedef struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
} hsmmc_t;
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define DATI_CMDDIS (0x1 << 1)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
typedef struct {
unsigned int card_type;
unsigned int version;
unsigned int mode;
unsigned int size;
unsigned int RCA;
} mmc_card_data;
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
#endif /* MMC_HOST_DEF_H */

13
drivers/mmc/omap3_mmc.c
Unescape View File

@ -30,7 +30,8 @@
#include <i2c.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc.h>
#include "omap3_mmc.h"
const unsigned short mmc_transspeed_val[15][4] = {
{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
@ -81,13 +82,14 @@ block_dev_desc_t *mmc_get_dev(int dev)
unsigned char mmc_board_init(void)
{
t2_t *t2_base = (t2_t *)T2_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
#endif
#if defined(CONFIG_OMAP34XX)
t2_t *t2_base = (t2_t *)T2_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
@ -105,6 +107,9 @@ unsigned char mmc_board_init(void)
writel(readl(&prcm_base->iclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->iclken1_core);
#endif
/* TODO add appropriate OMAP4 init */
return 1;
}

2
arch/arm/include/asm/arch-omap3/mmc.h → drivers/mmc/omap3_mmc.h
Unescape View File

@ -25,7 +25,7 @@
#ifndef MMC_H
#define MMC_H
#include "mmc_host_def.h"
#include <asm/arch/mmc_host_def.h>
/* Responses */
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
Write Preview
Loading…
Cancel
Save