Graeme Russ
15 years ago
committed by
Wolfgang Denk
parent
167cdad137
commit
bf16500f79
@ -1,506 +0,0 @@ |
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/*
|
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* (C) Copyright 2002 |
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*------------------------------------------------------------------------------+ */ |
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|
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/*
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* This source code is dual-licensed. You may use it under the terms of the |
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* GNU General Public License version 2, or under the license below. |
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* |
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* This source code has been made available to you by IBM on an AS-IS |
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* basis. Anyone receiving this source is licensed under IBM |
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* copyrights to use it in any way he or she deems fit, including |
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* copying it, modifying it, compiling it, and redistributing it either |
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* with or without modifications. No license under IBM patents or |
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* patent applications is to be implied by the copyright license. |
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* |
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* Any user of this software should understand that IBM cannot provide |
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* technical support for this software and will not be responsible for |
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* any consequences resulting from the use of this software. |
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* |
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* Any person who transfers this source code or any derivative work |
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* must include the IBM copyright notice, this paragraph, and the |
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* preceding two paragraphs in the transferred software. |
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* |
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* COPYRIGHT I B M CORPORATION 1995 |
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
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*/ |
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/*------------------------------------------------------------------------------- */ |
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#include <common.h> |
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#include <watchdog.h> |
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#include <asm/io.h> |
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#include <asm/ibmpc.h> |
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
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#include <malloc.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_RBR 0x00 |
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#define UART_THR 0x00 |
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#define UART_IER 0x01 |
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#define UART_IIR 0x02 |
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#define UART_FCR 0x02 |
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#define UART_LCR 0x03 |
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#define UART_MCR 0x04 |
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#define UART_LSR 0x05 |
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#define UART_MSR 0x06 |
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#define UART_SCR 0x07 |
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#define UART_DLL 0x00 |
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#define UART_DLM 0x01 |
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/*-----------------------------------------------------------------------------+
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| Line Status Register. |
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+-----------------------------------------------------------------------------*/ |
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#define asyncLSRDataReady1 0x01 |
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#define asyncLSROverrunError1 0x02 |
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#define asyncLSRParityError1 0x04 |
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#define asyncLSRFramingError1 0x08 |
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#define asyncLSRBreakInterrupt1 0x10 |
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#define asyncLSRTxHoldEmpty1 0x20 |
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#define asyncLSRTxShiftEmpty1 0x40 |
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#define asyncLSRRxFifoError1 0x80 |
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
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/*-----------------------------------------------------------------------------+
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| Fifo |
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+-----------------------------------------------------------------------------*/ |
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typedef struct { |
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char *rx_buffer; |
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ulong rx_put; |
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ulong rx_get; |
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int cts; |
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} serial_buffer_t; |
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volatile serial_buffer_t buf_info; |
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static int serial_buffer_active=0; |
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#endif |
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static int serial_div(int baudrate) |
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{ |
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switch (baudrate) { |
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case 1200: |
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return 96; |
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case 9600: |
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return 12; |
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case 19200: |
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return 6; |
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case 38400: |
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return 3; |
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case 57600: |
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return 2; |
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case 115200: |
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return 1; |
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} |
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return 12; |
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} |
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/*
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* Minimal serial functions needed to use one of the SMC ports |
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* as serial console interface. |
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*/ |
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int serial_init(void) |
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{ |
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volatile char val; |
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int bdiv = serial_div(gd->baudrate); |
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outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ |
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outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */ |
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outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ |
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outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ |
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outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */ |
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outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */ |
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val = inb(UART0_BASE + UART_LSR); /* clear line status */ |
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val = inb(UART0_BASE + UART_RBR); /* read receive buffer */ |
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outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */ |
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outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */ |
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return 0; |
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} |
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void serial_setbrg(void) |
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{ |
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unsigned short bdiv; |
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bdiv = serial_div(gd->baudrate); |
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outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ |
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outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */ |
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outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ |
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outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ |
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} |
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void serial_putc(const char c) |
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{ |
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int i; |
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if (c == '\n') |
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serial_putc ('\r'); |
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/* check THRE bit, wait for transmiter available */ |
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for (i = 1; i < 3500; i++) { |
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if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) { |
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break; |
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} |
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udelay(100); |
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} |
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outb(c, UART0_BASE + UART_THR); /* put character out */ |
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} |
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void serial_puts(const char *s) |
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{ |
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while (*s) { |
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serial_putc(*s++); |
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} |
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} |
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int serial_getc(void) |
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{ |
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unsigned char status = 0; |
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
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if (serial_buffer_active) { |
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return serial_buffered_getc(); |
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} |
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#endif |
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while (1) { |
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#if defined(CONFIG_HW_WATCHDOG) |
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WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ |
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#endif /* CONFIG_HW_WATCHDOG */ |
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status = inb(UART0_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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break; |
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} |
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if ((status & ( asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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outb(asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); |
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} |
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} |
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return (0x000000ff & (int) inb (UART0_BASE)); |
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} |
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int serial_tstc(void) |
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{ |
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unsigned char status; |
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
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if (serial_buffer_active) { |
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return serial_buffered_tstc(); |
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} |
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#endif |
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status = inb(UART0_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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return (1); |
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} |
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if ((status & ( asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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outb(asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); |
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} |
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return 0; |
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} |
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
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void serial_isr(void *arg) |
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{ |
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int space; |
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int c; |
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int rx_put = buf_info.rx_put; |
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if (buf_info.rx_get <= rx_put) { |
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space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get); |
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} else { |
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space = buf_info.rx_get - rx_put; |
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} |
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while (inb(UART0_BASE + UART_LSR) & 1) { |
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c = inb(UART0_BASE); |
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if (space) { |
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buf_info.rx_buffer[rx_put++] = c; |
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space--; |
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if (rx_put == buf_info.rx_get) { |
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buf_info.rx_get++; |
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if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { |
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buf_info.rx_get = 0; |
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} |
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} |
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if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { |
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rx_put = 0; |
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if (0 == buf_info.rx_get) { |
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buf_info.rx_get = 1; |
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} |
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} |
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} |
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if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { |
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/* Stop flow by setting RTS inactive */ |
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outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02), |
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UART0_BASE + UART_MCR); |
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} |
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} |
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buf_info.rx_put = rx_put; |
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} |
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void serial_buffered_init(void) |
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{ |
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serial_puts ("Switching to interrupt driven serial input mode.\n"); |
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buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); |
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buf_info.rx_put = 0; |
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buf_info.rx_get = 0; |
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if (inb (UART0_BASE + UART_MSR) & 0x10) { |
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serial_puts ("Check CTS signal present on serial port: OK.\n"); |
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buf_info.cts = 1; |
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} else { |
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serial_puts ("WARNING: CTS signal not present on serial port.\n"); |
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buf_info.cts = 0; |
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} |
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irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , |
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serial_isr /*interrupt_handler_t *handler */ , |
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(void *) &buf_info /*void *arg */ ); |
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/* Enable "RX Data Available" Interrupt on UART */ |
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/* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */ |
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outb(0x01, UART0_BASE + UART_IER); |
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/* Set DTR and RTS active, enable interrupts */ |
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outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR); |
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/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ |
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outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR); |
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serial_buffer_active = 1; |
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} |
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void serial_buffered_putc (const char c) |
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{ |
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int i; |
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/* Wait for CTS */ |
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#if defined(CONFIG_HW_WATCHDOG) |
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while (!(inb (UART0_BASE + UART_MSR) & 0x10)) |
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WATCHDOG_RESET (); |
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#else |
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if (buf_info.cts) { |
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for (i=0;i<1000;i++) { |
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if ((inb (UART0_BASE + UART_MSR) & 0x10)) { |
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break; |
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} |
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} |
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if (i!=1000) { |
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buf_info.cts = 0; |
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} |
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} else { |
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if ((inb (UART0_BASE + UART_MSR) & 0x10)) { |
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buf_info.cts = 1; |
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} |
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} |
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#endif |
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serial_putc (c); |
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} |
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void serial_buffered_puts(const char *s) |
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{ |
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serial_puts (s); |
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} |
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int serial_buffered_getc(void) |
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{ |
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int space; |
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int c; |
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int rx_get = buf_info.rx_get; |
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int rx_put; |
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#if defined(CONFIG_HW_WATCHDOG) |
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while (rx_get == buf_info.rx_put) |
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WATCHDOG_RESET (); |
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#else |
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while (rx_get == buf_info.rx_put); |
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#endif |
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c = buf_info.rx_buffer[rx_get++]; |
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if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) { |
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rx_get = 0; |
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} |
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buf_info.rx_get = rx_get; |
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rx_put = buf_info.rx_put; |
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if (rx_get <= rx_put) { |
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space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); |
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} else { |
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space = rx_get - rx_put; |
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} |
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if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { |
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/* Start flow by setting RTS active */ |
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outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR); |
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} |
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return c; |
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} |
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int serial_buffered_tstc(void) |
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{ |
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return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; |
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} |
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#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ |
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#if defined(CONFIG_CMD_KGDB) |
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/*
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AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port |
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number 0 or number 1 |
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- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : |
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configuration has been already done |
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- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : |
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configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE |
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*/ |
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#if (CONFIG_KGDB_SER_INDEX & 2) |
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void kgdb_serial_init(void) |
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{ |
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volatile char val; |
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bdiv = serial_div (CONFIG_KGDB_BAUDRATE); |
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/*
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* Init onboard 16550 UART |
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*/ |
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outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ |
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outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ |
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outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ |
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outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ |
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outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ |
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outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ |
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val = inb(UART1_BASE + UART_LSR); /* clear line status */ |
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val = inb(UART1_BASE + UART_RBR); /* read receive buffer */ |
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outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */ |
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outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */ |
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} |
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void putDebugChar(const char c) |
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{ |
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if (c == '\n') |
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serial_putc ('\r'); |
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outb(c, UART1_BASE + UART_THR); /* put character out */ |
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/* check THRE bit, wait for transfer done */ |
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while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20); |
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} |
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void putDebugStr(const char *s) |
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{ |
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while (*s) { |
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serial_putc(*s++); |
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} |
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} |
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int getDebugChar(void) |
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{ |
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unsigned char status = 0; |
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while (1) { |
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status = inb(UART1_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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break; |
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} |
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if ((status & ( asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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outb(asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR); |
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} |
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} |
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return (0x000000ff & (int) inb(UART1_BASE)); |
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} |
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void kgdb_interruptible(int yes) |
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{ |
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return; |
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} |
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#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ |
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void kgdb_serial_init(void) |
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{ |
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serial_printf ("[on serial] "); |
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} |
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void putDebugChar(int c) |
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{ |
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serial_putc (c); |
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} |
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void putDebugStr(const char *str) |
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{ |
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serial_puts (str); |
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} |
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int getDebugChar(void) |
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{ |
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return serial_getc (); |
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} |
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void kgdb_interruptible(int yes) |
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{ |
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return; |
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} |
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#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ |
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#endif |
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