This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a board definition for ODROID-C2. This initial submission only supports UART and Ethernet (through the existing Designware driver). DTS files are the ones submitted to Linux arm-soc for 4.7 [1]. [1] https://patchwork.ozlabs.org/patch/603583/ Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
Beniamino Galvani
9 years ago
committed by
Tom Rini
parent
0e1a3e30de
commit
bfcef28ae4
@ -0,0 +1,69 @@ |
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/* |
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* Copyright (c) 2016 Andreas Färber |
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* Copyright (c) 2016 BayLibre, Inc. |
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* Author: Kevin Hilman <khilman@kernel.org> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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|
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#include "meson-gxbb.dtsi" |
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|
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/ { |
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compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; |
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model = "Hardkernel ODROID-C2"; |
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|
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aliases { |
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serial0 = &uart_AO; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>; |
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}; |
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}; |
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|
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&uart_AO { |
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status = "okay"; |
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}; |
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@ -0,0 +1,178 @@ |
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/* |
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* Copyright (c) 2016 Andreas Färber |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This library is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This library is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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|
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/ { |
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compatible = "amlogic,meson-gxbb"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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|
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cpus { |
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#address-cells = <0x2>; |
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#size-cells = <0x0>; |
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|
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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}; |
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|
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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}; |
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|
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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}; |
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|
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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}; |
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}; |
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|
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arm-pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
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}; |
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|
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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|
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 |
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, |
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<GIC_PPI 14 |
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, |
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<GIC_PPI 11 |
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, |
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<GIC_PPI 10 |
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; |
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}; |
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|
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xtal: xtal-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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clock-output-names = "xtal"; |
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#clock-cells = <0>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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|
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cbus: cbus@c1100000 { |
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compatible = "simple-bus"; |
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reg = <0x0 0xc1100000 0x0 0x100000>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; |
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uart_A: serial@84c0 { |
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compatible = "amlogic,meson-uart"; |
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reg = <0x0 0x084c0 0x0 0x14>; |
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&xtal>; |
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status = "disabled"; |
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}; |
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}; |
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gic: interrupt-controller@c4301000 { |
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compatible = "arm,gic-400"; |
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reg = <0x0 0xc4301000 0 0x1000>, |
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<0x0 0xc4302000 0 0x2000>, |
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<0x0 0xc4304000 0 0x2000>, |
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<0x0 0xc4306000 0 0x2000>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 |
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
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#interrupt-cells = <3>; |
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#address-cells = <0>; |
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}; |
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aobus: aobus@c8100000 { |
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compatible = "simple-bus"; |
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reg = <0x0 0xc8100000 0x0 0x100000>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; |
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uart_AO: serial@4c0 { |
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compatible = "amlogic,meson-uart"; |
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reg = <0x0 0x004c0 0x0 0x14>; |
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&xtal>; |
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status = "disabled"; |
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}; |
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}; |
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apb: apb@d0000000 { |
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compatible = "simple-bus"; |
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reg = <0x0 0xd0000000 0x0 0x200000>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; |
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}; |
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}; |
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}; |
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@ -0,0 +1,52 @@ |
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef __GXBB_H__ |
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#define __GXBB_H__ |
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#define GXBB_PERIPHS_BASE 0xc8834400 |
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#define GXBB_HIU_BASE 0xc883c000 |
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#define GXBB_ETH_BASE 0xc9410000 |
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|
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/* Peripherals registers */ |
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#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) |
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|
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/* GPIO registers 0 to 6 */ |
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#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) |
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#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) |
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#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) |
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#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) |
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|
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/* Pinmux registers 0 to 12 */ |
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#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n)) |
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#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) |
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#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) |
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#define GXBB_ETH_REG_0_PHY_INTF BIT(0) |
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#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) |
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#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) |
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#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) |
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#define GXBB_ETH_REG_0_CLK_EN BIT(12) |
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|
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/* HIU registers */ |
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#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) |
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#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) |
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/* Ethernet memory power domain */ |
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#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) |
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|
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/* Clock gates */ |
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#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) |
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#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) |
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#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) |
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#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) |
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#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) |
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#define GXBB_GCLK_MPEG_1_ETH BIT(3) |
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#endif /* __GXBB_H__ */ |
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@ -0,0 +1,31 @@ |
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if ARCH_MESON |
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config MESON_GXBB |
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bool "Support Meson GXBaby" |
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select ARM64 |
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select DM |
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select DM_SERIAL |
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help |
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The Amlogic Meson GXBaby (S905) is an ARM SoC with a |
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quad-core Cortex-A53 CPU and a Mali-450 GPU. |
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if MESON_GXBB |
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config TARGET_ODROID_C2 |
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bool "ODROID-C2" |
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help |
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ODROID-C2 is a single board computer based on Meson GXBaby |
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with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD |
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slot, eMMC, IR receiver and a 40-pin GPIO header. |
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endif |
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config SYS_SOC |
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default "meson" |
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config SYS_MALLOC_F_LEN |
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default 0x1000 |
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source "board/hardkernel/odroid-c2/Kconfig" |
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endif |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += board.o
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@ -0,0 +1,66 @@ |
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/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <libfdt.h> |
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#include <linux/err.h> |
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#include <asm/arch/gxbb.h> |
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#include <asm/armv8/mmu.h> |
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#include <asm/unaligned.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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const fdt64_t *val; |
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int offset; |
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int len; |
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offset = fdt_path_offset(gd->fdt_blob, "/memory"); |
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if (offset < 0) |
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return -EINVAL; |
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val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); |
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if (len < sizeof(*val) * 2) |
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return -EINVAL; |
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/* Use unaligned access since cache is still disabled */ |
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gd->ram_size = get_unaligned_be64(&val[1]); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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/* Reserve first 16 MiB of RAM for firmware */ |
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); |
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gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024); |
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} |
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void reset_cpu(ulong addr) |
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{ |
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psci_system_reset(true); |
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} |
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static struct mm_region gxbb_mem_map[] = { |
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{ |
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.base = 0x0UL, |
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.size = 0x80000000UL, |
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_INNER_SHARE |
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}, { |
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.base = 0x80000000UL, |
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.size = 0x80000000UL, |
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE | |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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}, { |
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/* List terminator */ |
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0, |
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} |
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}; |
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struct mm_region *mem_map = gxbb_mem_map; |
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@ -0,0 +1,12 @@ |
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if TARGET_ODROID_C2 |
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config SYS_BOARD |
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default "odroid-c2" |
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config SYS_VENDOR |
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default "hardkernel" |
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config SYS_CONFIG_NAME |
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default "odroid-c2" |
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endif |
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@ -0,0 +1,6 @@ |
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ODROID-C2 |
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M: Beniamino Galvani <b.galvani@gmail.com> |
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S: Maintained |
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F: board/hardkernel/odroid-c2/ |
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F: include/configs/odroid-c2.h |
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F: configs/odroid-c2_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
|
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y := odroid-c2.o
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@ -0,0 +1,60 @@ |
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U-Boot for ODROID-C2 |
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==================== |
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|
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ODROID-C2 is a single board computer manufactured by Hardkernel |
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Co. Ltd with the following specifications: |
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|
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- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz |
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- ARM Mali 450 GPU |
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- 2GB DDR3 SDRAM |
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- Gigabit Ethernet |
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- HDMI 2.0 4K/60Hz display |
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- 40-pin GPIO header |
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- 4 x USB 2.0 Host, 1 x USB OTG |
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- eMMC, microSD |
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- Infrared receiver |
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|
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Schematics are available on the manufacturer website. |
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|
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Currently the u-boot port supports the following devices: |
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- serial |
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- Ethernet |
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|
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u-boot compilation |
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================== |
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|
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> export ARCH=arm |
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> export CROSS_COMPILE=aarch64-none-elf- |
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> make odroid-c2_defconfig |
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> make |
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|
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Image creation |
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============== |
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|
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Amlogic doesn't provide sources for the firmware and for tools needed |
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to create the bootloader image, so it is necessary to obtain them from |
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the git tree published by the board vendor: |
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|
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> DIR=odroid-c2 |
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> git clone --depth 1 \ |
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https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ |
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$DIR |
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> $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ |
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--bl301 $DIR/fip/gxb/bl301.bin \ |
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--bl31 $DIR/fip/gxb/bl31.bin \ |
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--bl33 u-boot.bin \ |
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$DIR/fip.bin |
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> $DIR/fip/fip_create --dump $DIR/fip.bin |
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> cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin |
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> $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ |
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--input $DIR/boot_new.bin \ |
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--output $DIR/u-boot.img |
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> dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 |
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|
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and then write the image to SD with: |
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|
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> DEV=/dev/your_sd_device |
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> BL1=$DIR/sd_fuse/bl1.bin.hardkernel |
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> dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 |
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> dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 |
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> dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 |
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@ -0,0 +1,51 @@ |
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/*
|
||||
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/gxbb.h> |
||||
#include <dm/platdata.h> |
||||
#include <phy.h> |
||||
|
||||
int board_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static const struct eth_pdata gxbb_eth_pdata = { |
||||
.iobase = GXBB_ETH_BASE, |
||||
.phy_interface = PHY_INTERFACE_MODE_RGMII, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(meson_eth) = { |
||||
.name = "eth_designware", |
||||
.platdata = &gxbb_eth_pdata, |
||||
}; |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
/* Select Ethernet function */ |
||||
setbits_le32(GXBB_PINMUX(6), 0x3fff); |
||||
|
||||
/* Set RGMII mode */ |
||||
setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | |
||||
GXBB_ETH_REG_0_TX_PHASE(1) | |
||||
GXBB_ETH_REG_0_TX_RATIO(4) | |
||||
GXBB_ETH_REG_0_PHY_CLK_EN | |
||||
GXBB_ETH_REG_0_CLK_EN); |
||||
|
||||
/* Enable power and clock gate */ |
||||
setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); |
||||
clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); |
||||
|
||||
/* Reset PHY on GPIOZ_14 */ |
||||
clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); |
||||
clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); |
||||
mdelay(10); |
||||
setbits_le32(GXBB_GPIO_OUT(3), BIT(14)); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,23 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MESON=y |
||||
CONFIG_MESON_GXBB=y |
||||
CONFIG_TARGET_ODROID_C2=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" |
||||
# CONFIG_CMD_BDI is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_CMD_SOURCE is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_MESON=y |
||||
CONFIG_DEBUG_UART_BASE=0xc81004c0 |
||||
CONFIG_DEBUG_UART_CLOCK=24000000 |
||||
CONFIG_DEBUG_UART_ANNOUNCE=y |
||||
CONFIG_DEBUG_UART_SKIP_INIT=y |
||||
CONFIG_MESON_SERIAL=y |
||||
@ -0,0 +1,162 @@ |
||||
/*
|
||||
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <linux/compiler.h> |
||||
#include <serial.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct meson_uart { |
||||
u32 wfifo; |
||||
u32 rfifo; |
||||
u32 control; |
||||
u32 status; |
||||
u32 misc; |
||||
}; |
||||
|
||||
struct meson_serial_platdata { |
||||
struct meson_uart *reg; |
||||
}; |
||||
|
||||
/* AML_UART_STATUS bits */ |
||||
#define AML_UART_PARITY_ERR BIT(16) |
||||
#define AML_UART_FRAME_ERR BIT(17) |
||||
#define AML_UART_TX_FIFO_WERR BIT(18) |
||||
#define AML_UART_RX_EMPTY BIT(20) |
||||
#define AML_UART_TX_FULL BIT(21) |
||||
#define AML_UART_TX_EMPTY BIT(22) |
||||
#define AML_UART_XMIT_BUSY BIT(25) |
||||
#define AML_UART_ERR (AML_UART_PARITY_ERR | \ |
||||
AML_UART_FRAME_ERR | \
|
||||
AML_UART_TX_FIFO_WERR) |
||||
|
||||
/* AML_UART_CONTROL bits */ |
||||
#define AML_UART_TX_EN BIT(12) |
||||
#define AML_UART_RX_EN BIT(13) |
||||
#define AML_UART_TX_RST BIT(22) |
||||
#define AML_UART_RX_RST BIT(23) |
||||
#define AML_UART_CLR_ERR BIT(24) |
||||
|
||||
static void meson_serial_init(struct meson_uart *uart) |
||||
{ |
||||
u32 val; |
||||
|
||||
val = readl(&uart->control); |
||||
val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); |
||||
writel(val, &uart->control); |
||||
val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); |
||||
writel(val, &uart->control); |
||||
val |= (AML_UART_RX_EN | AML_UART_TX_EN); |
||||
writel(val, &uart->control); |
||||
} |
||||
|
||||
static int meson_serial_probe(struct udevice *dev) |
||||
{ |
||||
struct meson_serial_platdata *plat = dev->platdata; |
||||
struct meson_uart *const uart = plat->reg; |
||||
|
||||
meson_serial_init(uart); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_serial_getc(struct udevice *dev) |
||||
{ |
||||
struct meson_serial_platdata *plat = dev->platdata; |
||||
struct meson_uart *const uart = plat->reg; |
||||
|
||||
if (readl(&uart->status) & AML_UART_RX_EMPTY) |
||||
return -EAGAIN; |
||||
|
||||
return readl(&uart->rfifo) & 0xff; |
||||
} |
||||
|
||||
static int meson_serial_putc(struct udevice *dev, const char ch) |
||||
{ |
||||
struct meson_serial_platdata *plat = dev->platdata; |
||||
struct meson_uart *const uart = plat->reg; |
||||
|
||||
if (readl(&uart->status) & AML_UART_TX_FULL) |
||||
return -EAGAIN; |
||||
|
||||
writel(ch, &uart->wfifo); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int meson_serial_pending(struct udevice *dev, bool input) |
||||
{ |
||||
struct meson_serial_platdata *plat = dev->platdata; |
||||
struct meson_uart *const uart = plat->reg; |
||||
uint32_t status = readl(&uart->status); |
||||
|
||||
if (input) |
||||
return !(status & AML_UART_RX_EMPTY); |
||||
else |
||||
return !(status & AML_UART_TX_FULL); |
||||
} |
||||
|
||||
static int meson_serial_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct meson_serial_platdata *plat = dev->platdata; |
||||
fdt_addr_t addr; |
||||
|
||||
addr = dev_get_addr(dev); |
||||
if (addr == FDT_ADDR_T_NONE) |
||||
return -EINVAL; |
||||
|
||||
plat->reg = (struct meson_uart *)addr; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_serial_ops meson_serial_ops = { |
||||
.putc = meson_serial_putc, |
||||
.pending = meson_serial_pending, |
||||
.getc = meson_serial_getc, |
||||
}; |
||||
|
||||
static const struct udevice_id meson_serial_ids[] = { |
||||
{ .compatible = "amlogic,meson-uart" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(serial_meson) = { |
||||
.name = "serial_meson", |
||||
.id = UCLASS_SERIAL, |
||||
.of_match = meson_serial_ids, |
||||
.probe = meson_serial_probe, |
||||
.ops = &meson_serial_ops, |
||||
.flags = DM_FLAG_PRE_RELOC, |
||||
.ofdata_to_platdata = meson_serial_ofdata_to_platdata, |
||||
.platdata_auto_alloc_size = sizeof(struct meson_serial_platdata), |
||||
}; |
||||
|
||||
#ifdef CONFIG_DEBUG_UART_MESON |
||||
|
||||
#include <debug_uart.h> |
||||
|
||||
static inline void _debug_uart_init(void) |
||||
{ |
||||
} |
||||
|
||||
static inline void _debug_uart_putc(int ch) |
||||
{ |
||||
struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE; |
||||
|
||||
while (readl(®s->status) & AML_UART_TX_FULL) |
||||
; |
||||
|
||||
writel(ch, ®s->wfifo); |
||||
} |
||||
|
||||
DEBUG_UART_FUNCS |
||||
|
||||
#endif |
||||
@ -0,0 +1,51 @@ |
||||
/*
|
||||
* Configuration for ODROID-C2 |
||||
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_CPU_ARMV8 |
||||
#define CONFIG_REMAKE_ELF |
||||
#define CONFIG_SYS_CACHELINE_SIZE 64 |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define CONFIG_ENV_IS_NOWHERE 1 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_SYS_MAXARGS 32 |
||||
#define CONFIG_SYS_MALLOC_LEN (32 << 20) |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0 |
||||
#define CONFIG_SYS_TEXT_BASE 0x01000000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE |
||||
|
||||
/* Generic Interrupt Controller Definitions */ |
||||
#define GICD_BASE 0xc4301000 |
||||
#define GICC_BASE 0xc4302000 |
||||
|
||||
#define CONFIG_IDENT_STRING " odroid-c2" |
||||
|
||||
/* Serial setup */ |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_CMD_ENV |
||||
|
||||
/* Monitor Command Prompt */ |
||||
/* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#include <config_distro_defaults.h> |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue