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@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) |
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* modify it. |
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*/ |
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if (temp == 1) { |
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mfcpr(CPR0_PLLD, reg); |
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/* Get current value of fbdv. */ |
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temp = (reg & PLLD_FBDV_MASK) >> 24; |
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fbdv = temp ? temp : 32; |
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/* Get current value of lfbdv. */ |
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temp = (reg & PLLD_LFBDV_MASK); |
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lfbdv = temp ? temp : 64; |
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/*
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* Load register that contains current boot strapping option. |
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*/ |
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mfcpr(CPR0_ICFG, reg); |
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/* Shift strapping option into low 3 bits.*/ |
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reg = (reg >> 28); |
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/*
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* Strapping option bits (ICS) are already in correct position, |
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* only masking needed. |
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*/ |
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reg &= CPR0_ICFG_ICS_MASK; |
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if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || |
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(reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { |
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mfcpr(CPR0_PLLD, reg); |
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/* Get current value of fbdv. */ |
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temp = (reg & PLLD_FBDV_MASK) >> 24; |
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fbdv = temp ? temp : 32; |
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/* Get current value of lfbdv. */ |
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temp = (reg & PLLD_LFBDV_MASK); |
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lfbdv = temp ? temp : 64; |
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/*
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* Get current value of FWDVA. Assign current FWDVA to |
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* new FWDVB. |
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@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) |
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mfcpr(CPR0_PLLD, reg); |
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target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; |
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fwdvb = target_fwdvb ? target_fwdvb : 8; |
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/*
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* Get current value of FWDVB. Assign current FWDVB to |
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* new FWDVA. |
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*/ |
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target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; |
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fwdva = target_fwdva ? target_fwdva : 16; |
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/*
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* Update CPR0_PLLD with switched FWDVA and FWDVB. |
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*/ |
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@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) |
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((fbdv == 32 ? 0 : fbdv) << 24) | |
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(lfbdv == 64 ? 0 : lfbdv); |
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mtcpr(CPR0_PLLD, reg); |
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/* Acknowledge that a reset is required. */ |
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reset_needed = 1; |
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} |
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