Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>master
Andre Schwarz
17 years ago
committed by
Kim Phillips
parent
f9023afbdf
commit
c005b93925
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Matrix Vision mvBlueLYNX-M7 (mvBL-M7) |
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------------------------------------- |
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1. Board Description |
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The mvBL-M7 is a 120x120mm single board computing platform |
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with strong focus on stereo image processing applications. |
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Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) |
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on any port (requires add-on board). |
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2 System Components |
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2.1 CPU |
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Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. |
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512MByte DDR-II memory @ 133MHz. |
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8 MByte Nor Flash on local bus. |
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2 Vitesse VSC8601 RGMII ethernet Phys. |
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1 USB host controller over ULPI I/F. |
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2 serial ports. Console running on ttyS0 @ 115200 8N1. |
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1 SD-Card slot connected to SPI. |
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System configuration (HRCW) is taken from I2C EEPROM. |
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2.2 PCI |
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A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. |
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2.3 FPGA |
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Altera Cyclone-II EP2C20/35 with PCI DMA engines. |
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Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. |
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Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. |
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2.3.1 I/O @ FPGA |
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2x8 Outputs : Infineon High-Side Switches to Main Supply. |
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2x8 Inputs : Programmable input threshold + trigger capabilities |
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2 dedicated flash interfaces for illuminator boards. |
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Cross trigger for chaining several boards. |
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2.4 I2C |
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Bus1: |
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MAX5381 DAC @ 0x60 for 1st digital input threshold. |
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LM75 @ 0x90 for temperature monitoring. |
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EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. |
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1st image sensor interface (slave adresses depend on sensor) |
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Bus2: |
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MAX5381 DAC @ 0x60 for 2nd digital input threshold. |
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2nd image sensor interface (slave adresses depend on sensor) |
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3 Flash layout. |
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reset vector is 0xFFF00100, i.e. "HIGHBOOT". |
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FF800000 environment |
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FF802000 redundant environment |
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FF804000 u-boot script image |
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FF806000 redundant u-boot script image |
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FF808000 device tree blob |
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FF80A000 redundant device tree blob |
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FF80C000 tbd. |
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FF80E000 tbd. |
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FF810000 kernel |
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FFC00000 root FS |
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FFF00000 u-boot |
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FFF80000 FPGA raw bit file |
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mtd partitions are propagated to linux kernel via device tree blob. |
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4 Booting |
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On startup the bootscript @ FF804000 is executed. This script can be |
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exchanged easily. Default boot mode is "boot from flash", i.e. system |
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works stand-alone. |
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This behaviour depends on some environment variables : |
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"netboot" : yes ->try dhcp/bootp and boot from network. |
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A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for |
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DHCP server configuration, e.g. to provide different images to |
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different devices. |
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During netboot the system tries to get 3 image files: |
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1. Kernel - name + data is given during BOOTP. |
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2. Initrd - name is stored in "initrd_name" |
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3. device tree blob - name is stored in "dtb_name" |
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Fallback files are the flash versions. |
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@ -0,0 +1,479 @@ |
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/*
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* Copyright (C) Matrix Vision GmbH 2008 |
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* |
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* Matrix Vision mvBlueLYNX-M7 configuration file |
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* based on Freescale's MPC8349ITX. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define MV_VERSION "v1.0.1" |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_E300 1 |
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#define CONFIG_MPC83XX 1 |
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#define CONFIG_MPC834X 1 |
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#define CONFIG_MPC8343 1 |
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#define CFG_IMMR 0xE0000000 |
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#define CONFIG_PCI |
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#define CONFIG_83XX_GENERIC_PCI |
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#define CONFIG_PCI_SKIP_HOST_BRIDGE |
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#define CONFIG_HARD_I2C |
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#define CONFIG_TSEC_ENET |
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#define CONFIG_MPC8XXX_SPI |
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#define CONFIG_HARD_SPI |
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#define MVBLM7_MMC_CS 0x04000000 |
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/* I2C */ |
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#undef CONFIG_SOFT_I2C |
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#define CONFIG_FSL_I2C |
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#define CONFIG_I2C_MULTI_BUS |
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#define CONFIG_I2C_CMD_TREE |
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#define CFG_I2C_OFFSET 0x3000 |
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#define CFG_I2C2_OFFSET 0x3100 |
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#define CFG_I2C_SPEED 100000 |
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#define CFG_I2C_SLAVE 0x7F |
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/*
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* DDR Setup |
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*/ |
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#define CFG_DDR_BASE 0x00000000 |
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#define CFG_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_83XX_DDR_USES_CS0 1 |
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#define CFG_MEMTEST_START (60<<20) |
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#define CFG_MEMTEST_END (70<<20) |
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#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
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#define CFG_DDR_SIZE 256 |
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/* HC, 75Ohm, DDR-II, DRQ */ |
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#define CFG_DDRCDR 0x80000001 |
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/* EN, ODT_WR, 3BA, 14row, 10col */ |
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#define CFG_DDR_CS0_CONFIG 0x80014102 |
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#define CFG_DDR_CS1_CONFIG 0x0 |
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#define CFG_DDR_CS2_CONFIG 0x0 |
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#define CFG_DDR_CS3_CONFIG 0x0 |
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#define CFG_DDR_CS0_BNDS 0x0000000f |
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#define CFG_DDR_CS1_BNDS 0x0 |
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#define CFG_DDR_CS2_BNDS 0x0 |
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#define CFG_DDR_CS3_BNDS 0x0 |
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#define CFG_DDR_CLK_CNTL 0x02000000 |
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#define CFG_DDR_TIMING_0 0x00260802 |
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#define CFG_DDR_TIMING_1 0x2625b221 |
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#define CFG_DDR_TIMING_2 0x1f9820c7 |
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#define CFG_DDR_TIMING_3 0x00000000 |
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/* ~MEM_EN, SREN, DDR-II, 32_BE */ |
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#define CFG_DDR_SDRAM_CFG 0x43080000 |
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#define CFG_DDR_SDRAM_CFG2 0x00401000 |
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#define CFG_DDR_INTERVAL 0x04060100 |
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#define CFG_DDR_MODE 0x078e0232 |
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/* Flash */ |
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#define CFG_FLASH_CFI |
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#define CFG_FLASH_CFI_DRIVER |
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#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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#define CFG_FLASH_BASE 0xFF800000 |
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#define CFG_FLASH_SIZE 8 |
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#define CFG_FLASH_SIZE_SHIFT 3 |
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#define CFG_FLASH_EMPTY_INFO |
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#define CFG_FLASH_ERASE_TOUT 60000 |
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#define CFG_FLASH_WRITE_TOUT 500 |
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#define CFG_MAX_FLASH_BANKS 1 |
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#define CFG_MAX_FLASH_SECT 256 |
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) |
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS|\
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OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD) |
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE |
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#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) |
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/*
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* U-Boot memory configuration |
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*/ |
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#define CFG_MONITOR_BASE TEXT_BASE |
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#undef CFG_RAMBOOT |
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#define CONFIG_L1_INIT_RAM |
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#define CFG_INIT_RAM_LOCK |
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#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
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#define CFG_MONITOR_LEN (512 * 1024) |
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#define CFG_MALLOC_LEN (512 * 1024) |
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/*
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* Local Bus LCRR and LBCR regs |
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* LCRR: DLL bypass, Clock divider is 4 |
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* External Local Bus rate is |
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
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*/ |
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
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#define CFG_LBC_LBCR 0x00000000 |
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/* LB sdram refresh timer, about 6us */ |
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#define CFG_LBC_LSRT 0x32000000 |
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/* LB refresh timer prescal, 266MHz/32*/ |
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#define CFG_LBC_MRTPR 0x20000000 |
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/*
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* Serial Port |
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*/ |
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#define CONFIG_CONS_INDEX 1 |
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#undef CONFIG_SERIAL_SOFTWARE_FIFO |
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#define CFG_NS16550 |
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#define CFG_NS16550_SERIAL |
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#define CFG_NS16550_REG_SIZE 1 |
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#define CFG_NS16550_CLK get_bus_freq(0) |
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#define CFG_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
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#define CONFIG_CONSOLE ttyS0 |
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#define CONFIG_BAUDRATE 115200 |
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#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) |
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#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) |
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/* pass open firmware flat tree */ |
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#define CONFIG_OF_LIBFDT 1 |
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#define CONFIG_OF_BOARD_SETUP 1 |
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
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#define MV_DTB_NAME "mvblm7.dtb" |
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/*
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* PCI |
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*/ |
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#define CFG_PCI1_MEM_BASE 0x80000000 |
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
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#define CFG_PCI1_MEM_SIZE 0x10000000 |
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#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) |
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#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
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#define CFG_PCI1_MMIO_SIZE 0x10000000 |
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#define CFG_PCI1_IO_BASE 0x00000000 |
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#define CFG_PCI1_IO_PHYS 0xE2000000 |
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#define CFG_PCI1_IO_SIZE 0x01000000 |
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#define _IO_BASE 0x00000000 |
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#define CONFIG_NET_MULTI 1 |
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#define CONFIG_NET_RETRY_COUNT 3 |
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#define PCI_66M |
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#define CONFIG_83XX_CLKIN 66666667 |
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#define CONFIG_PCI_PNP |
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#define CONFIG_PCI_SCAN_SHOW |
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/* TSEC */ |
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#define CONFIG_GMII |
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#define CFG_VSC8601_SKEWFIX |
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#define CFG_VSC8601_SKEW_TX 3 |
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#define CFG_VSC8601_SKEW_RX 3 |
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#define CONFIG_TSEC1 |
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#define CONFIG_TSEC2 |
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#define CONFIG_HAS_ETH0 |
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#define CONFIG_TSEC1_NAME "TSEC0" |
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#define CONFIG_FEC1_PHY_NORXERR |
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#define CFG_TSEC1_OFFSET 0x24000 |
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) |
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#define TSEC1_PHY_ADDR 0x10 |
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#define TSEC1_PHYIDX 0 |
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#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) |
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#define CONFIG_HAS_ETH1 |
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#define CONFIG_TSEC2_NAME "TSEC1" |
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#define CONFIG_FEC2_PHY_NORXERR |
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#define CFG_TSEC2_OFFSET 0x25000 |
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#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) |
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#define TSEC2_PHY_ADDR 0x11 |
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#define TSEC2_PHYIDX 0 |
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#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) |
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#define CONFIG_ETHPRIME "TSEC0" |
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#define CONFIG_BOOTP_VENDOREX |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_NTPSERVER |
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#define CONFIG_BOOTP_RANDOM_DELAY |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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/* USB */ |
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#define CONFIG_HAS_FSL_DR_USB |
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/*
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* Environment |
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*/ |
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#undef CFG_FLASH_PROTECTION |
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#define CONFIG_ENV_OVERWRITE |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_ADDR 0xFF800000 |
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#define CFG_ENV_SIZE 0x2000 |
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#define CFG_ENV_SECT_SIZE 0x2000 |
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) |
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE |
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#define CONFIG_LOADS_ECHO |
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#define CFG_LOADS_BAUD_CHANGE |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_IRQ |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_SDRAM |
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#define CONFIG_CMD_PCI |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_FPGA |
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#undef CONFIG_WATCHDOG |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP |
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#define CONFIG_CMDLINE_EDITING |
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#define CFG_HUSH_PARSER |
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#define CFG_PROMPT_HUSH_PS2 "> " |
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/* default load address */ |
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#define CFG_LOAD_ADDR 0x2000000 |
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/* default location for tftp and bootm */ |
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#define CONFIG_LOADADDR 0x200000 |
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#define CFG_PROMPT "mvBL-M7> " |
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#define CFG_CBSIZE 256 |
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
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#define CFG_MAXARGS 16 |
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#define CFG_BARGSIZE CFG_CBSIZE |
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#define CFG_HZ 1000 |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
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#define CFG_HRCW_LOW 0x0 |
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#define CFG_HRCW_HIGH 0x0 |
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/*
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* System performance |
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*/ |
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#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
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#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
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#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
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#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ |
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/* clocking */ |
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#define CFG_SCCR_ENCCM 0 |
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#define CFG_SCCR_USBMPHCM 0 |
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#define CFG_SCCR_USBDRCM 2 |
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#define CFG_SCCR_TSEC1CM 1 |
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#define CFG_SCCR_TSEC2CM 1 |
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#define CFG_SICRH 0x1fff8003 |
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#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) |
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#define CFG_HID0_INIT 0x000000000 |
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#define CFG_HID0_FINAL CFG_HID0_INIT |
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#define CFG_HID2 HID2_HBE |
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/* DDR */ |
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
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/* PCI */ |
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#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
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#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
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#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ |
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BATL_GUARDEDSTORAGE) |
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#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
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/* no PCI2 */ |
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#define CFG_IBAT3L 0 |
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#define CFG_IBAT3U 0 |
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#define CFG_IBAT4L 0 |
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#define CFG_IBAT4U 0 |
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
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#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ |
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BATL_GUARDEDSTORAGE) |
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#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
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/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ |
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#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
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#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
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#define CFG_IBAT7L 0 |
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#define CFG_IBAT7U 0 |
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#define CFG_DBAT0L CFG_IBAT0L |
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#define CFG_DBAT0U CFG_IBAT0U |
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#define CFG_DBAT1L CFG_IBAT1L |
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#define CFG_DBAT1U CFG_IBAT1U |
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#define CFG_DBAT2L CFG_IBAT2L |
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#define CFG_DBAT2U CFG_IBAT2U |
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#define CFG_DBAT3L CFG_IBAT3L |
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#define CFG_DBAT3U CFG_IBAT3U |
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#define CFG_DBAT4L CFG_IBAT4L |
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#define CFG_DBAT4U CFG_IBAT4U |
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#define CFG_DBAT5L CFG_IBAT5L |
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#define CFG_DBAT5U CFG_IBAT5U |
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#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_NETDEV eth0 |
||||
|
||||
/* Default path and filenames */ |
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_AUTOBOOT_KEYED |
||||
#define CONFIG_AUTOBOOT_STOP_STR "s" |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
#define CONFIG_RESET_TO_RETRY 1000 |
||||
|
||||
#define MV_CI "mvBL-M7" |
||||
#define MV_VCI "mvBL-M7" |
||||
#define MV_FPGA_DATA "0xfff80000" |
||||
#define MV_FPGA_SIZE "0x76ca2" |
||||
#define MV_KERNEL_ADDR "0xff810000" |
||||
#define MV_INITRD_ADDR "0xffc00000" |
||||
#define MV_AUTOSCR_ADDR "0xff804000" |
||||
#define MV_AUTOSCR_ADDR2 "0xff806000" |
||||
#define MV_DTB_ADDR "0xff808000" |
||||
#define MV_INITRD_LENGTH "0x00300000" |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 |
||||
|
||||
#define MV_KERNEL_ADDR_RAM "0x00100000" |
||||
#define MV_DTB_ADDR_RAM "0x00600000" |
||||
#define MV_INITRD_ADDR_RAM "0x01000000" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ |
||||
then autoscr ${autoscr_addr}; \
|
||||
else autoscr ${autoscr_addr2}; \
|
||||
fi;" |
||||
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"console_nr=0\0" \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" \
|
||||
"fpga=0\0" \
|
||||
"fpgadata=" MV_FPGA_DATA "\0" \
|
||||
"fpgadatasize=" MV_FPGA_SIZE "\0" \
|
||||
"autoscr_addr=" MV_AUTOSCR_ADDR "\0" \
|
||||
"autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \
|
||||
"mv_kernel_addr=" MV_KERNEL_ADDR "\0" \
|
||||
"mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \
|
||||
"mv_initrd_addr=" MV_INITRD_ADDR "\0" \
|
||||
"mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \
|
||||
"mv_initrd_length=" MV_INITRD_LENGTH "\0" \
|
||||
"mv_dtb_addr=" MV_DTB_ADDR "\0" \
|
||||
"mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
|
||||
"dtb_name=" MV_DTB_NAME "\0" \
|
||||
"mv_version=" MV_VERSION "\0" \
|
||||
"dhcp_client_id=" MV_CI "\0" \
|
||||
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
|
||||
"netretry=no\0" \
|
||||
"use_static_ipaddr=no\0" \
|
||||
"static_ipaddr=192.168.90.10\0" \
|
||||
"static_netmask=255.255.255.0\0" \
|
||||
"static_gateway=0.0.0.0\0" \
|
||||
"initrd_name=uInitrd.mvblm7-xenorfs\0" \
|
||||
"zcip=no\0" \
|
||||
"netboot=yes\0" \
|
||||
"mvtest=Ff\0" \
|
||||
"tried_bootfromflash=no\0" \
|
||||
"tried_bootfromnet=no\0" \
|
||||
"bootfile=mvblm72625.boot\0" \
|
||||
"use_dhcp=yes\0" \
|
||||
"gev_start=yes\0" \
|
||||
"mvbcdma_debug=0\0" \
|
||||
"mvbcia_debug=0\0" \
|
||||
"propdev_debug=0\0" \
|
||||
"gevss_debug=0\0" \
|
||||
"watchdog=0\0" \
|
||||
"usb_dr_mode=host\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_FPGA_COUNT 1 |
||||
#define CONFIG_FPGA CFG_ALTERA_CYCLON2 |
||||
#define CONFIG_FPGA_ALTERA |
||||
#define CONFIG_FPGA_CYCLON2 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue