configs: ax25-ae350: Support cfi flash

Enable cfi flash driver and setup flash
parameters to support parallel nor flash
which type is JS28F00A-M29EWH.

Verification:
Size detection, data read, erase and write are all ok.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
lime2-spi
Rick Chen 6 years ago committed by Andes
parent cf3922dddc
commit c038fd0ea6
  1. 5
      configs/ax25-ae350_defconfig
  2. 38
      include/configs/ax25-ae350.h

@ -4,8 +4,10 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350"
CONFIG_TARGET_AX25_AE350=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
@ -25,6 +27,9 @@ CONFIG_MMC=y
CONFIG_DM_MMC=y
CONFIG_FTSDC010=y
CONFIG_FTSDC010_SDIO=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y

@ -79,6 +79,44 @@
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
/*
* FLASH and environment organization
*/
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
/* max number of memory banks */
/*
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0

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