* add's at91_emac (AT91RM9200) network driver (NET_MULTI api) * enable driver with CONFIG_DRIVER_AT91EMAC * generic PHY initialization * modify AT91RM9200 boards to use NET_MULTI driver * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII interface Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>master
Jens Scharsig
15 years ago
committed by
Ben Warren
parent
594d57d0cc
commit
c041e9d212
@ -0,0 +1,498 @@ |
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/*
|
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* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG |
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* Jens Scharsig (esw@bus-elektronik.de) |
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* |
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* (C) Copyright 2003 |
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* Author : Hamid Ikdoumi (Atmel) |
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|
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#ifndef CONFIG_AT91_LEGACY |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_emac.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_pio.h> |
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#else |
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/* remove next 5 lines, if all RM9200 boards convert to at91 arch */ |
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#include <asm/arch-at91/at91rm9200.h> |
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#include <asm/arch-at91/hardware.h> |
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#include <asm/arch-at91/at91_emac.h> |
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#include <asm/arch-at91/at91_pmc.h> |
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#include <asm/arch-at91/at91_pio.h> |
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#endif |
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#include <net.h> |
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#include <netdev.h> |
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#include <malloc.h> |
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#include <miiphy.h> |
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#include <linux/mii.h> |
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#undef MII_DEBUG |
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#undef ET_DEBUG |
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|
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#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) |
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#error AT91 EMAC supports max 1024 RX buffers. \ |
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Please decrease the CONFIG_SYS_RX_ETH_BUFFER value |
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#endif |
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|
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/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ |
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#if (AT91C_MASTER_CLOCK > 80000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_64 |
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#elif (AT91C_MASTER_CLOCK > 40000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_32 |
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#elif (AT91C_MASTER_CLOCK > 20000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_16 |
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#else |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_8 |
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#endif |
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|
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#ifdef ET_DEBUG |
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#define DEBUG_AT91EMAC(...) printf(__VA_ARGS__); |
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#else |
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#define DEBUG_AT91EMAC(...) |
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#endif |
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#ifdef MII_DEBUG |
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#define DEBUG_AT91PHY(...) printf(__VA_ARGS__); |
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#else |
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#define DEBUG_AT91PHY(...) |
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#endif |
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|
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#ifndef CONFIG_DRIVER_AT91EMAC_QUIET |
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#define VERBOSEP(...) printf(__VA_ARGS__); |
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#else |
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#define VERBOSEP(...) |
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#endif |
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#define RBF_ADDR 0xfffffffc |
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#define RBF_OWNER (1<<0) |
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#define RBF_WRAP (1<<1) |
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#define RBF_BROADCAST (1<<31) |
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#define RBF_MULTICAST (1<<30) |
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#define RBF_UNICAST (1<<29) |
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#define RBF_EXTERNAL (1<<28) |
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#define RBF_UNKOWN (1<<27) |
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#define RBF_SIZE 0x07ff |
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#define RBF_LOCAL4 (1<<26) |
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#define RBF_LOCAL3 (1<<25) |
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#define RBF_LOCAL2 (1<<24) |
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#define RBF_LOCAL1 (1<<23) |
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#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER |
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#define RBF_FRAMELEN 0x600 |
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typedef struct { |
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unsigned long addr, size; |
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} rbf_t; |
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typedef struct { |
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rbf_t rbfdt[RBF_FRAMEMAX]; |
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unsigned long rbindex; |
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} emac_device; |
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void at91emac_EnableMDIO(at91_emac_t *at91mac) |
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{ |
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/* Mac CTRL reg set for MDIO enable */ |
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writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); |
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} |
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void at91emac_DisableMDIO(at91_emac_t *at91mac) |
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{ |
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/* Mac CTRL reg set for MDIO disable */ |
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writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); |
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} |
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int at91emac_read(at91_emac_t *at91mac, unsigned char addr, |
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unsigned char reg, unsigned short *value) |
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{ |
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at91emac_EnableMDIO(at91mac); |
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | |
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AT91_EMAC_MAN_PHYA(addr), |
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&at91mac->man); |
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udelay(10000); |
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*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; |
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at91emac_DisableMDIO(at91mac); |
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DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value) |
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return 0; |
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} |
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int at91emac_write(at91_emac_t *at91mac, unsigned char addr, |
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unsigned char reg, unsigned short value) |
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{ |
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DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) |
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at91emac_EnableMDIO(at91mac); |
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | |
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AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), |
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&at91mac->man); |
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udelay(10000); |
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at91emac_DisableMDIO(at91mac); |
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return 0; |
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} |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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at91_emac_t *get_emacbase_by_name(char *devname) |
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{ |
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struct eth_device *netdev; |
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netdev = eth_get_dev_by_name(devname); |
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return (at91_emac_t *) netdev->iobase; |
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} |
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int at91emac_mii_read(char *devname, unsigned char addr, |
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unsigned char reg, unsigned short *value) |
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{ |
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at91_emac_t *emac; |
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emac = get_emacbase_by_name(devname); |
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at91emac_read(emac , addr, reg, value); |
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return 0; |
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} |
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int at91emac_mii_write(char *devname, unsigned char addr, |
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unsigned char reg, unsigned short value) |
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{ |
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at91_emac_t *emac; |
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emac = get_emacbase_by_name(devname); |
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at91emac_write(emac, addr, reg, value); |
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return 0; |
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} |
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#endif |
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static int at91emac_phy_reset(struct eth_device *netdev) |
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{ |
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int i; |
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u16 status, adv; |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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adv = ADVERTISE_CSMA | ADVERTISE_ALL; |
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at91emac_write(emac, 0, MII_ADVERTISE, adv); |
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VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); |
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at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); |
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for (i = 0; i < 100000 / 100; i++) { |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (status & BMSR_ANEGCOMPLETE) |
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break; |
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udelay(100); |
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} |
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if (status & BMSR_ANEGCOMPLETE) { |
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VERBOSEP("%s: Autonegotiation complete\n", netdev->name); |
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} else { |
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printf("%s: Autonegotiation timed out (status=0x%04x)\n", |
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netdev->name, status); |
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return 1; |
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} |
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return 0; |
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} |
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static int at91emac_phy_init(struct eth_device *netdev) |
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{ |
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u16 phy_id, status, adv, lpa; |
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int media, speed, duplex; |
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int i; |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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/* Check if the PHY is up to snuff... */ |
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at91emac_read(emac, 0, MII_PHYSID1, &phy_id); |
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if (phy_id == 0xffff) { |
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printf("%s: No PHY present\n", netdev->name); |
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return 1; |
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} |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (!(status & BMSR_LSTATUS)) { |
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/* Try to re-negotiate if we don't have link already. */ |
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if (at91emac_phy_reset(netdev)) |
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return 2; |
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for (i = 0; i < 100000 / 100; i++) { |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (status & BMSR_LSTATUS) |
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break; |
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udelay(100); |
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} |
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} |
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if (!(status & BMSR_LSTATUS)) { |
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VERBOSEP("%s: link down\n", netdev->name); |
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return 3; |
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} else { |
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at91emac_read(emac, 0, MII_ADVERTISE, &adv); |
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at91emac_read(emac, 0, MII_LPA, &lpa); |
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media = mii_nway_result(lpa & adv); |
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) |
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? 1 : 0); |
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duplex = (media & ADVERTISE_FULL) ? 1 : 0; |
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VERBOSEP("%s: link up, %sMbps %s-duplex\n", |
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netdev->name, |
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speed ? "100" : "10", |
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duplex ? "full" : "half"); |
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} |
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return 0; |
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} |
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int at91emac_UpdateLinkSpeed(at91_emac_t *emac) |
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{ |
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unsigned short stat1; |
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at91emac_read(emac, 0, MII_BMSR, &stat1); |
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if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ |
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return 1; |
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if (stat1 & BMSR_100FULL) { |
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/*set Emac for 100BaseTX and Full Duplex */ |
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writel(readl(&emac->cfg) | |
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AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_10FULL) { |
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/*set MII for 10BaseT and Full Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) |
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) | AT91_EMAC_CFG_FD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_100HALF) { |
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/*set MII for 100BaseTX and Half Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) |
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) | AT91_EMAC_CFG_SPD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_10HALF) { |
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/*set MII for 10BaseT and Half Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), |
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&emac->cfg); |
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return 0; |
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} |
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return 1; |
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} |
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static int at91emac_init(struct eth_device *netdev, bd_t *bd) |
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{ |
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int i; |
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u32 value; |
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emac_device *dev; |
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at91_emac_t *emac; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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emac = (at91_emac_t *) netdev->iobase; |
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dev = (emac_device *) netdev->priv; |
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/* PIO Disable Register */ |
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value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC | |
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AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 | |
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AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS | |
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AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 | |
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AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK; |
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writel(value, &pio->pioa.pdr); |
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writel(value, &pio->pioa.asr); |
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#ifdef CONFIG_RMII |
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value = AT91_PMX_BA_ERXCK; |
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#else |
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value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL | |
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AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 | |
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AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER | |
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AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2; |
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#endif |
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writel(value, &pio->piob.pdr); |
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writel(value, &pio->piob.bsr); |
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writel(1 << AT91_ID_EMAC, &pmc->pcer); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); |
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DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", |
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cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), |
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cpu_to_le32(*((u32 *)netdev->enetaddr))); |
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writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); |
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writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); |
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DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", |
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readl(&emac->sa2h), readl(&emac->sa2l)); |
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/* Init Ethernet buffers */ |
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for (i = 0; i < RBF_FRAMEMAX; i++) { |
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dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; |
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dev->rbfdt[i].size = 0; |
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} |
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dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; |
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dev->rbindex = 0; |
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writel((u32) &(dev->rbfdt[0]), &emac->rbqp); |
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writel(readl(&emac->rsr) & |
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~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), |
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&emac->rsr); |
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value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | |
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HCLK_DIV; |
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#ifdef CONFIG_RMII |
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value |= AT91C_EMAC_RMII; |
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#endif |
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writel(value, &emac->cfg); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, |
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&emac->ctl); |
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if (!at91emac_phy_init(netdev)) { |
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at91emac_UpdateLinkSpeed(emac); |
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return 0; |
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} |
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return 1; |
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} |
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static void at91emac_halt(struct eth_device *netdev) |
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{ |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), |
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&emac->ctl); |
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DEBUG_AT91EMAC("halt MAC\n"); |
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} |
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static int at91emac_send(struct eth_device *netdev, volatile void *packet, |
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int length) |
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{ |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) |
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; |
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writel((u32) packet, &emac->tar); |
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writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); |
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while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) |
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; |
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DEBUG_AT91EMAC("Send %d \n", length); |
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writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); |
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return 0; |
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} |
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static int at91emac_recv(struct eth_device *netdev) |
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{ |
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emac_device *dev; |
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at91_emac_t *emac; |
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rbf_t *rbfp; |
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int size; |
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emac = (at91_emac_t *) netdev->iobase; |
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dev = (emac_device *) netdev->priv; |
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rbfp = &dev->rbfdt[dev->rbindex]; |
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while (rbfp->addr & RBF_OWNER) { |
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size = rbfp->size & RBF_SIZE; |
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NetReceive(NetRxPackets[dev->rbindex], size); |
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DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n", |
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dev->rbindex, size, rbfp->addr); |
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rbfp->addr &= ~RBF_OWNER; |
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rbfp->size = 0; |
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if (dev->rbindex < (RBF_FRAMEMAX-1)) |
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dev->rbindex++; |
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else |
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dev->rbindex = 0; |
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|
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rbfp = &(dev->rbfdt[dev->rbindex]); |
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if (!(rbfp->addr & RBF_OWNER)) |
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writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, |
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&emac->rsr); |
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} |
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|
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if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { |
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/* EMAC silicon bug 41.3.1 workaround 1 */ |
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writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); |
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dev->rbindex = 0; |
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printf("%s: reset receiver (EMAC dead lock bug)\n", |
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netdev->name); |
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} |
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return 0; |
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} |
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|
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int at91emac_register(bd_t *bis, unsigned long iobase) |
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{ |
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emac_device *emac; |
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emac_device *emacfix; |
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struct eth_device *dev; |
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|
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if (iobase == 0) |
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iobase = AT91_EMAC_BASE; |
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emac = malloc(sizeof(*emac)+512); |
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if (emac == NULL) |
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return 1; |
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dev = malloc(sizeof(*dev)); |
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if (dev == NULL) { |
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free(emac); |
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return 1; |
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} |
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/* alignment as per Errata (64 bytes) is insufficient! */ |
||||
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); |
||||
memset(emacfix, 0, sizeof(emac_device)); |
||||
|
||||
memset(dev, 0, sizeof(*dev)); |
||||
#ifndef CONFIG_RMII |
||||
sprintf(dev->name, "AT91 EMAC"); |
||||
#else |
||||
sprintf(dev->name, "AT91 EMAC RMII"); |
||||
#endif |
||||
dev->iobase = iobase; |
||||
dev->priv = emacfix; |
||||
dev->init = at91emac_init; |
||||
dev->halt = at91emac_halt; |
||||
dev->send = at91emac_send; |
||||
dev->recv = at91emac_recv; |
||||
|
||||
eth_register(dev); |
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
||||
miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); |
||||
#endif |
||||
return 1; |
||||
} |
||||
@ -0,0 +1,145 @@ |
||||
/*
|
||||
* Memory Setup stuff - taken from blob memsetup.S |
||||
* |
||||
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
||||
* |
||||
* based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91_H |
||||
#define AT91_H |
||||
|
||||
typedef struct at91_emac { |
||||
u32 ctl; |
||||
u32 cfg; |
||||
u32 sr; |
||||
u32 tar; |
||||
u32 tcr; |
||||
u32 tsr; |
||||
u32 rbqp; |
||||
u32 reserved0; |
||||
u32 rsr; |
||||
u32 isr; |
||||
u32 ier; |
||||
u32 idr; |
||||
u32 imr; |
||||
u32 man; |
||||
u32 reserved1[2]; |
||||
u32 fra; |
||||
u32 scol; |
||||
u32 mocl; |
||||
u32 ok; |
||||
u32 seqe; |
||||
u32 ale; |
||||
u32 dte; |
||||
u32 lcol; |
||||
u32 ecol; |
||||
u32 cse; |
||||
u32 tue; |
||||
u32 cde; |
||||
u32 elr; |
||||
u32 rjb; |
||||
u32 usf; |
||||
u32 sqee; |
||||
u32 drfc; |
||||
u32 reserved2[3]; |
||||
u32 hsh; |
||||
u32 hsl; |
||||
u32 sh1l; |
||||
u32 sa1h; |
||||
u32 sa2l; |
||||
u32 sa2h; |
||||
u32 sa3l; |
||||
u32 sa3h; |
||||
u32 sa4l; |
||||
u32 sa4h; |
||||
} at91_emac_t; |
||||
|
||||
#define AT91_EMAC_CTL_LB 0x0001 |
||||
#define AT91_EMAC_CTL_LBL 0x0002 |
||||
#define AT91_EMAC_CTL_RE 0x0004 |
||||
#define AT91_EMAC_CTL_TE 0x0008 |
||||
#define AT91_EMAC_CTL_MPE 0x0010 |
||||
#define AT91_EMAC_CTL_CSR 0x0020 |
||||
#define AT91_EMAC_CTL_ISR 0x0040 |
||||
#define AT91_EMAC_CTL_WES 0x0080 |
||||
#define AT91_EMAC_CTL_BP 0x1000 |
||||
|
||||
#define AT91_EMAC_CFG_SPD 0x0001 |
||||
#define AT91_EMAC_CFG_FD 0x0002 |
||||
#define AT91_EMAC_CFG_BR 0x0004 |
||||
#define AT91_EMAC_CFG_CAF 0x0010 |
||||
#define AT91_EMAC_CFG_NBC 0x0020 |
||||
#define AT91_EMAC_CFG_MTI 0x0040 |
||||
#define AT91_EMAC_CFG_UNI 0x0080 |
||||
#define AT91_EMAC_CFG_BIG 0x0100 |
||||
#define AT91_EMAC_CFG_EAE 0x0200 |
||||
#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF |
||||
#define AT91_EMAC_CFG_MCLK_8 0x0000 |
||||
#define AT91_EMAC_CFG_MCLK_16 0x0400 |
||||
#define AT91_EMAC_CFG_MCLK_32 0x0800 |
||||
#define AT91_EMAC_CFG_MCLK_64 0x0C00 |
||||
#define AT91_EMAC_CFG_RTY 0x1000 |
||||
#define AT91_EMAC_CFG_RMII 0x2000 |
||||
|
||||
#define AT91_EMAC_SR_LINK 0x0001 |
||||
#define AT91_EMAC_SR_MDIO 0x0002 |
||||
#define AT91_EMAC_SR_IDLE 0x0004 |
||||
|
||||
#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) |
||||
#define AT91_EMAC_TCR_NCRC 0x8000 |
||||
|
||||
#define AT91_EMAC_TSR_OVR 0x0001 |
||||
#define AT91_EMAC_TSR_COL 0x0002 |
||||
#define AT91_EMAC_TSR_RLE 0x0004 |
||||
#define AT91_EMAC_TSR_TXIDLE 0x0008 |
||||
#define AT91_EMAC_TSR_BNQ 0x0010 |
||||
#define AT91_EMAC_TSR_COMP 0x0020 |
||||
#define AT91_EMAC_TSR_UND 0x0040 |
||||
|
||||
#define AT91_EMAC_RSR_BNA 0x0001 |
||||
#define AT91_EMAC_RSR_REC 0x0002 |
||||
#define AT91_EMAC_RSR_OVR 0x0004 |
||||
|
||||
/* ISR, IER, IDR, IMR use the same bits */ |
||||
#define AT91_EMAC_IxR_DONE 0x0001 |
||||
#define AT91_EMAC_IxR_RCOM 0x0002 |
||||
#define AT91_EMAC_IxR_RBNA 0x0004 |
||||
#define AT91_EMAC_IxR_TOVR 0x0008 |
||||
#define AT91_EMAC_IxR_TUND 0x0010 |
||||
#define AT91_EMAC_IxR_RTRY 0x0020 |
||||
#define AT91_EMAC_IxR_TBRE 0x0040 |
||||
#define AT91_EMAC_IxR_TCOM 0x0080 |
||||
#define AT91_EMAC_IxR_TIDLE 0x0100 |
||||
#define AT91_EMAC_IxR_LINK 0x0200 |
||||
#define AT91_EMAC_IxR_ROVR 0x0400 |
||||
#define AT91_EMAC_IxR_HRESP 0x0800 |
||||
|
||||
#define AT91_EMAC_MAN_DATA_MASK 0xFFFF |
||||
#define AT91_EMAC_MAN_CODE_802_3 0x00020000 |
||||
#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) |
||||
#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) |
||||
#define AT91_EMAC_MAN_RW_R 0x20000000 |
||||
#define AT91_EMAC_MAN_RW_W 0x10000000 |
||||
#define AT91_EMAC_MAN_HIGH 0x40000000 |
||||
#define AT91_EMAC_MAN_LOW 0x80000000 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue