Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>master
Minkyu Kang
16 years ago
parent
7074635021
commit
c0a1dfdec2
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := smdkc100.o
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COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(SOBJS) $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,16 @@ |
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#
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# Copyright (C) 2008 # Samsung Elecgtronics
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# Kyungmin Park <kyungmin.park@samsung.com>
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#
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# On S5PC100 we use the 128 MiB OneDRAM bank at
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#
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# 0x30000000 to 0x35000000 (80MiB)
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# 0x38000000 to 0x40000000 (128MiB)
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#
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# On S5PC110 we use the 128 MiB OneDRAM bank at
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#
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# 0x30000000 to 0x35000000 (80MiB)
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# 0x40000000 to 0x48000000 (128MiB)
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#
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TEXT_BASE = 0x34800000
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@ -0,0 +1,215 @@ |
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/* |
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* Copyright (C) 2009 Samsung Electronics |
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* Kyungmin Park <kyungmin.park@samsung.com>
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* Minkyu Kang <mk7.kang@samsung.com>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/power.h> |
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/* |
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* Register usages: |
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* |
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* r5 has zero always |
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*/ |
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_TEXT_BASE: |
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.word TEXT_BASE
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.globl lowlevel_init
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lowlevel_init: |
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mov r9, lr |
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/* r5 has always zero */ |
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mov r5, #0 |
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ldr r8, =S5PC100_GPIO_BASE |
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/* Disable Watchdog */ |
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ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
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orr r0, r0, #0x0 |
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str r5, [r0] |
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#ifndef CONFIG_ONENAND_IPL |
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/* setting SRAM */ |
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ldr r0, =S5PC100_SROMC_BASE |
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ldr r1, =0x9 |
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str r1, [r0] |
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#endif |
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/* S5PC100 has 3 groups of interrupt sources */ |
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ldr r0, =S5PC100_VIC0_BASE @0xE4000000
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ldr r1, =S5PC100_VIC1_BASE @0xE4000000
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ldr r2, =S5PC100_VIC2_BASE @0xE4000000
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/* Disable all interrupts (VIC0, VIC1 and VIC2) */ |
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mvn r3, #0x0 |
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str r3, [r0, #0x14] @INTENCLEAR
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str r3, [r1, #0x14] @INTENCLEAR
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str r3, [r2, #0x14] @INTENCLEAR
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#ifndef CONFIG_ONENAND_IPL |
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/* Set all interrupts as IRQ */ |
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str r5, [r0, #0xc] @INTSELECT
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str r5, [r1, #0xc] @INTSELECT
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str r5, [r2, #0xc] @INTSELECT
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/* Pending Interrupt Clear */ |
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str r5, [r0, #0xf00] @INTADDRESS
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str r5, [r1, #0xf00] @INTADDRESS
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str r5, [r2, #0xf00] @INTADDRESS
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#endif |
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#ifndef CONFIG_ONENAND_IPL |
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/* for UART */ |
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bl uart_asm_init |
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/* for TZPC */ |
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bl tzpc_asm_init |
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#endif |
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#ifdef CONFIG_ONENAND_IPL |
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/* init system clock */ |
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bl system_clock_init |
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bl mem_ctrl_asm_init |
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/* Wakeup support. Don't know if it's going to be used, untested. */ |
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ldr r0, =S5PC100_RST_STAT |
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ldr r1, [r0] |
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bic r1, r1, #0xfffffff7 |
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cmp r1, #0x8 |
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beq wakeup_reset |
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#endif |
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1: |
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mov lr, r9 |
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mov pc, lr |
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#ifdef CONFIG_ONENAND_IPL |
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wakeup_reset: |
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/* Clear wakeup status register */ |
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ldr r0, =S5PC100_WAKEUP_STAT |
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ldr r1, [r0] |
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str r1, [r0] |
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/* Load return address and jump to kernel */ |
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ldr r0, =S5PC100_INFORM0 |
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/* r1 = physical address of s5pc100_cpu_resume function */ |
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ldr r1, [r0] |
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/* Jump to kernel (sleep.S) */ |
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mov pc, r1 |
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nop |
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nop |
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#endif |
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/* |
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* system_clock_init: Initialize core clock and bus clock. |
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* void system_clock_init(void) |
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*/ |
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system_clock_init: |
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ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000
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/* Set Clock divider */ |
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ldr r1, =0x00011110 |
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str r1, [r8, #0x304] |
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ldr r1, =0x1 |
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str r1, [r8, #0x308] |
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ldr r1, =0x00011301 |
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str r1, [r8, #0x300] |
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/* Set Lock Time */ |
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ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
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str r1, [r8, #0x000] @ APLL_LOCK
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str r1, [r8, #0x004] @ MPLL_LOCK
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str r1, [r8, #0x008] @ EPLL_LOCK
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str r1, [r8, #0x00C] @ HPLL_LOCK
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/* APLL_CON */ |
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ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
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str r1, [r8, #0x100] |
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/* MPLL_CON */ |
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ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
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str r1, [r8, #0x104] |
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/* EPLL_CON */ |
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ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
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str r1, [r8, #0x108] |
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/* HPLL_CON */ |
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ldr r1, =0x80600603 |
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str r1, [r8, #0x10C] |
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/* Set Source Clock */ |
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ldr r1, =0x1111 @ A, M, E, HPLL Muxing
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str r1, [r8, #0x200] @ CLK_SRC0
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ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
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str r1, [r8, #0x204] @ CLK_SRC1
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ldr r1, =0x9000 @ ARMCLK/4
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str r1, [r8, #0x400] @ CLK_OUT
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/* wait at least 200us to stablize all clock */ |
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mov r2, #0x10000 |
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1: subs r2, r2, #1 |
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bne 1b |
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mov pc, lr |
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#ifndef CONFIG_ONENAND_IPL |
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/* |
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* uart_asm_init: Initialize UART's pins |
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*/ |
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uart_asm_init: |
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mov r0, r8 |
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ldr r1, =0x22222222 |
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str r1, [r0, #0x0] @ GPA0_CON
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ldr r1, =0x00022222 |
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str r1, [r0, #0x20] @ GPA1_CON
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mov pc, lr |
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/* |
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* tzpc_asm_init: Initialize TZPC |
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*/ |
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tzpc_asm_init: |
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ldr r0, =0xE3800000 |
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mov r1, #0x0 |
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str r1, [r0] |
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mov r1, #0xff |
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str r1, [r0, #0x804] |
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str r1, [r0, #0x810] |
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ldr r0, =0xE2800000 |
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str r1, [r0, #0x804] |
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str r1, [r0, #0x810] |
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str r1, [r0, #0x81C] |
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ldr r0, =0xE2900000 |
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str r1, [r0, #0x804] |
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str r1, [r0, #0x810] |
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mov pc, lr |
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#endif |
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@ -0,0 +1,197 @@ |
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/* |
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* Originates from Samsung's u-boot 1.1.6 port to S5PC1xx |
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* |
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* Copyright (C) 2009 Samsung Electrnoics |
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* Inki Dae <inki.dae@samsung.com>
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* Heungjun Kim <riverful.kim@samsung.com>
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* Minkyu Kang <mk7.kang@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init: |
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ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
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/* DLL parameter setting */ |
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ldr r1, =0x50101000 |
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str r1, [r6, #0x018] @ PHYCONTROL0
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ldr r1, =0xf4 |
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str r1, [r6, #0x01C] @ PHYCONTROL1
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ldr r1, =0x0 |
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str r1, [r6, #0x020] @ PHYCONTROL2
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/* DLL on */ |
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ldr r1, =0x50101002 |
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* DLL start */ |
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ldr r1, =0x50101003 |
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* Force value locking for DLL off */ |
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* DLL off */ |
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ldr r1, =0x50101001 |
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str r1, [r6, #0x018] @ PHYCONTROL0
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/* auto refresh off */ |
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ldr r1, =0xff001010 |
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str r1, [r6, #0x000] @ CONCONTROL
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/* |
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* Burst Length 4, 2 chips, 32-bit, LPDDR |
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* OFF: dynamic self refresh, force precharge, dynamic power down off |
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*/ |
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ldr r1, =0x00212100 |
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str r1, [r6, #0x004] @ MEMCONTROL
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/* |
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* Note: |
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* If Bank0 has OneDRAM we place it at 0x2800'0000 |
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* So finally Bank1 should address start at at 0x2000'0000 |
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*/ |
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mov r4, #0x0 |
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swap_memory: |
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/* |
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* Bank0 |
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* 0x30 -> 0x30000000 |
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* 0xf8 -> 0x37FFFFFF |
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* [15:12] 0: Linear |
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* [11:8 ] 2: 9 bits |
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* [ 7:4 ] 2: 14 bits |
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* [ 3:0 ] 2: 4 banks |
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*/ |
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ldr r1, =0x30f80222 |
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/* if r4 is 1, swap the bank */ |
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cmp r4, #0x1 |
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orreq r1, r1, #0x08000000 |
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str r1, [r6, #0x008] @ MEMCONFIG0
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/* |
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* Bank1 |
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* 0x38 -> 0x38000000 |
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* 0xf8 -> 0x3fFFFFFF |
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* [15:12] 0: Linear |
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* [11:8 ] 2: 9 bits |
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* [ 7:4 ] 2: 14 bits |
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* [ 3:0 ] 2: 4 banks |
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*/ |
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ldr r1, =0x38f80222 |
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/* if r4 is 1, swap the bank */ |
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cmp r4, #0x1 |
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biceq r1, r1, #0x08000000 |
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str r1, [r6, #0x00c] @ MEMCONFIG1
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ldr r1, =0x20000000 |
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str r1, [r6, #0x014] @ PRECHCONFIG
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/* |
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* FIXME: Please verify these values |
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* 7.8us * 166MHz %LE %LONG1294(0x50E) |
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* 7.8us * 133MHz %LE %LONG1038(0x40E), |
||||||
|
* 7.8us * 100MHz %LE %LONG780(0x30C), |
||||||
|
* 7.8us * 20MHz %LE %LONG156(0x9C), |
||||||
|
* 7.8us * 10MHz %LE %LONG78(0x4E) |
||||||
|
*/ |
||||||
|
ldr r1, =0x0000050e |
||||||
|
str r1, [r6, #0x030] @ TIMINGAREF
|
||||||
|
|
||||||
|
/* 166 MHz */ |
||||||
|
ldr r1, =0x0c233287 |
||||||
|
str r1, [r6, #0x034] @ TIMINGROW
|
||||||
|
|
||||||
|
/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */ |
||||||
|
ldr r1, =0x32330303 |
||||||
|
str r1, [r6, #0x038] @ TIMINGDATA
|
||||||
|
|
||||||
|
/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */ |
||||||
|
ldr r1, =0x04141433 |
||||||
|
str r1, [r6, #0x03C] @ TIMINGPOWER
|
||||||
|
|
||||||
|
/* chip0 Deselect */ |
||||||
|
ldr r1, =0x07000000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip0 PALL */ |
||||||
|
ldr r1, =0x01000000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip0 REFA */ |
||||||
|
ldr r1, =0x05000000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
/* chip0 REFA */ |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */ |
||||||
|
ldr r1, =0x00000032 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip1 Deselect */ |
||||||
|
ldr r1, =0x07100000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip1 PALL */ |
||||||
|
ldr r1, =0x01100000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip1 REFA */ |
||||||
|
ldr r1, =0x05100000 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
/* chip1 REFA */ |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */ |
||||||
|
ldr r1, =0x00100032 |
||||||
|
str r1, [r6, #0x010] @ DIRECTCMD
|
||||||
|
|
||||||
|
/* auto refresh on */ |
||||||
|
ldr r1, =0xff002030 |
||||||
|
str r1, [r6, #0x000] @ CONCONTROL
|
||||||
|
|
||||||
|
/* PwrdnConfig */ |
||||||
|
ldr r1, =0x00100002 |
||||||
|
str r1, [r6, #0x028] @ PWRDNCONFIG
|
||||||
|
|
||||||
|
/* BL%LE %LONG */ |
||||||
|
ldr r1, =0xff212100 |
||||||
|
str r1, [r6, #0x004] @ MEMCONTROL
|
||||||
|
|
||||||
|
|
||||||
|
/* Try to test memory area */ |
||||||
|
cmp r4, #0x1 |
||||||
|
beq 1f |
||||||
|
|
||||||
|
mov r4, #0x1 |
||||||
|
ldr r1, =0x37ffff00 |
||||||
|
str r4, [r1] |
||||||
|
str r4, [r1, #0x4] @ dummy write
|
||||||
|
ldr r0, [r1] |
||||||
|
cmp r0, r4 |
||||||
|
bne swap_memory |
||||||
|
|
||||||
|
1: |
||||||
|
mov pc, lr |
||||||
|
|
||||||
|
.ltorg |
||||||
@ -0,0 +1,83 @@ |
|||||||
|
/*
|
||||||
|
* Copyright (C) 2008-2009 Samsung Electronics |
||||||
|
* Kyungmin Park <kyungmin.park@samsung.com> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <linux/mtd/compat.h> |
||||||
|
#include <linux/mtd/mtd.h> |
||||||
|
#include <linux/mtd/onenand.h> |
||||||
|
#include <linux/mtd/samsung_onenand.h> |
||||||
|
|
||||||
|
#include <onenand_uboot.h> |
||||||
|
|
||||||
|
#include <asm/io.h> |
||||||
|
#include <asm/arch/clock.h> |
||||||
|
|
||||||
|
void onenand_board_init(struct mtd_info *mtd) |
||||||
|
{ |
||||||
|
struct onenand_chip *this = mtd->priv; |
||||||
|
struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; |
||||||
|
struct samsung_onenand *onenand; |
||||||
|
int value; |
||||||
|
|
||||||
|
this->base = (void *)S5PC100_ONENAND_BASE; |
||||||
|
onenand = (struct samsung_onenand *)this->base; |
||||||
|
|
||||||
|
/* D0 Domain memory clock gating */ |
||||||
|
value = readl(&clk->gate_d01); |
||||||
|
value &= ~(1 << 2); /* CLK_ONENANDC */ |
||||||
|
value |= (1 << 2); |
||||||
|
writel(value, &clk->gate_d01); |
||||||
|
|
||||||
|
value = readl(&clk->src0); |
||||||
|
value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ |
||||||
|
value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ |
||||||
|
writel(value, &clk->src0); |
||||||
|
|
||||||
|
value = readl(&clk->div1); |
||||||
|
value &= ~(3 << 16); /* PCLKD1_RATIO */ |
||||||
|
value |= (1 << 16); |
||||||
|
writel(value, &clk->div1); |
||||||
|
|
||||||
|
writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset); |
||||||
|
|
||||||
|
while (!(readl(&onenand->int_err_stat) & RST_CMP)) |
||||||
|
continue; |
||||||
|
|
||||||
|
writel(RST_CMP, &onenand->int_err_ack); |
||||||
|
|
||||||
|
/*
|
||||||
|
* Access_Clock [2:0] |
||||||
|
* 166 MHz, 134 Mhz : 3 |
||||||
|
* 100 Mhz, 60 Mhz : 2 |
||||||
|
*/ |
||||||
|
writel(0x3, &onenand->acc_clock); |
||||||
|
|
||||||
|
writel(INT_ERR_ALL, &onenand->int_err_mask); |
||||||
|
writel(1 << 0, &onenand->int_pin_en); /* Enable */ |
||||||
|
|
||||||
|
value = readl(&onenand->int_err_mask); |
||||||
|
value &= ~RDY_ACT; |
||||||
|
writel(value, &onenand->int_err_mask); |
||||||
|
|
||||||
|
s3c_onenand_init(mtd); |
||||||
|
} |
||||||
@ -0,0 +1,51 @@ |
|||||||
|
/*
|
||||||
|
* Copyright (C) 2008-2009 Samsung Electronics |
||||||
|
* Minkyu Kang <mk7.kang@samsung.com> |
||||||
|
* Kyungmin Park <kyungmin.park@samsung.com> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
|
||||||
|
int board_init(void) |
||||||
|
{ |
||||||
|
gd->bd->bi_arch_number = MACH_TYPE_SMDKC100; |
||||||
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
int dram_init(void) |
||||||
|
{ |
||||||
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||||
|
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, |
||||||
|
PHYS_SDRAM_1_SIZE); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
#ifdef CONFIG_DISPLAY_BOARDINFO |
||||||
|
int checkboard(void) |
||||||
|
{ |
||||||
|
printf("Board:\tSMDKC100\n"); |
||||||
|
return 0; |
||||||
|
} |
||||||
|
#endif |
||||||
@ -0,0 +1,56 @@ |
|||||||
|
|
||||||
|
Summary |
||||||
|
======= |
||||||
|
|
||||||
|
This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx |
||||||
|
family of SoCs (S5PC100 [1] and S5PC110). |
||||||
|
|
||||||
|
Currently the following board is supported: |
||||||
|
|
||||||
|
* SMDKC100 [2] |
||||||
|
|
||||||
|
Toolchain |
||||||
|
========= |
||||||
|
|
||||||
|
While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile |
||||||
|
with -march=armv5 to allow more compilers to work. For U-Boot code this has |
||||||
|
no performance impact. |
||||||
|
|
||||||
|
Build |
||||||
|
===== |
||||||
|
|
||||||
|
* SMDKC100 |
||||||
|
|
||||||
|
make smdkc100_config |
||||||
|
make |
||||||
|
|
||||||
|
|
||||||
|
Interfaces |
||||||
|
========== |
||||||
|
|
||||||
|
cpu |
||||||
|
|
||||||
|
To check SoC: |
||||||
|
|
||||||
|
if (cpu_is_s5pc100()) |
||||||
|
printf("cpu is s5pc100\n"); |
||||||
|
|
||||||
|
or |
||||||
|
|
||||||
|
if (cpu_is_s5pc110()) |
||||||
|
printf("cpu is s5pc110\n"); |
||||||
|
|
||||||
|
gpio |
||||||
|
not supported yet. |
||||||
|
|
||||||
|
Links |
||||||
|
===== |
||||||
|
|
||||||
|
[1] S5PC100: |
||||||
|
|
||||||
|
http://www.samsung.com/global/business/semiconductor/productInfo.do? |
||||||
|
fmly_id=229&partnum=S5PC100 |
||||||
|
|
||||||
|
[2] SMDKC100: |
||||||
|
|
||||||
|
http://meritech.co.kr/eng/products/product_view.php?num=28 |
||||||
@ -0,0 +1,242 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2009 Samsung Electronics |
||||||
|
* Minkyu Kang <mk7.kang@samsung.com> |
||||||
|
* HeungJun Kim <riverful.kim@samsung.com> |
||||||
|
* Inki Dae <inki.dae@samsung.com> |
||||||
|
* |
||||||
|
* Configuation settings for the SAMSUNG SMDKC100 board. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __CONFIG_H |
||||||
|
#define __CONFIG_H |
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options |
||||||
|
* (easy to change) |
||||||
|
*/ |
||||||
|
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ |
||||||
|
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ |
||||||
|
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ |
||||||
|
#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ |
||||||
|
#define CONFIG_SMDKC100 1 /* working with SMDKC100 */ |
||||||
|
|
||||||
|
#include <asm/arch/cpu.h> /* get chip and board defs */ |
||||||
|
|
||||||
|
#define CONFIG_ARCH_CPU_INIT |
||||||
|
|
||||||
|
#define CONFIG_DISPLAY_CPUINFO |
||||||
|
#define CONFIG_DISPLAY_BOARDINFO |
||||||
|
|
||||||
|
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||||
|
|
||||||
|
#define CONFIG_L2_OFF |
||||||
|
|
||||||
|
/* input clock of PLL: SMDKC100 has 12MHz input clock */ |
||||||
|
#define CONFIG_SYS_CLK_FREQ 12000000 |
||||||
|
|
||||||
|
/* DRAM Base */ |
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0x30000000 |
||||||
|
|
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS |
||||||
|
#define CONFIG_CMDLINE_TAG |
||||||
|
#define CONFIG_INITRD_TAG |
||||||
|
#define CONFIG_CMDLINE_EDITING |
||||||
|
|
||||||
|
/*
|
||||||
|
* Size of malloc() pool |
||||||
|
* 1MB = 0x100000, 0x100000 = 1024 * 1024 |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) |
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */ |
||||||
|
/* initial data */ |
||||||
|
/*
|
||||||
|
* select serial console configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */ |
||||||
|
#define CONFIG_SERIAL_MULTI 1 |
||||||
|
|
||||||
|
/* allow to overwrite serial and ethaddr */ |
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* Command definition |
||||||
|
***********************************************************/ |
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#undef CONFIG_CMD_FLASH |
||||||
|
#undef CONFIG_CMD_IMLS |
||||||
|
#undef CONFIG_CMD_NAND |
||||||
|
#undef CONFIG_CMD_NET |
||||||
|
|
||||||
|
#define CONFIG_CMD_CACHE |
||||||
|
#define CONFIG_CMD_REGINFO |
||||||
|
#define CONFIG_CMD_ONENAND |
||||||
|
#define CONFIG_CMD_ELF |
||||||
|
#define CONFIG_CMD_FAT |
||||||
|
#define CONFIG_CMD_MTDPARTS |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 3 |
||||||
|
|
||||||
|
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||||
|
|
||||||
|
#define CONFIG_MTD_DEVICE |
||||||
|
#define CONFIG_MTD_PARTITIONS |
||||||
|
|
||||||
|
#define MTDIDS_DEFAULT "onenand0=s3c-onenand" |
||||||
|
#define MTDPARTS_DEFAULT "mtdparts=s3c-onenand:256k(bootloader)"\ |
||||||
|
",128k@0x40000(params)"\
|
||||||
|
",3m@0x60000(kernel)"\
|
||||||
|
",16m@0x360000(test)"\
|
||||||
|
",-(UBI)" |
||||||
|
|
||||||
|
#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "run ubifsboot" |
||||||
|
|
||||||
|
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ |
||||||
|
" console=ttySAC0,115200n8" \
|
||||||
|
" mem=128M" |
||||||
|
|
||||||
|
#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \ |
||||||
|
" mem=128M " \
|
||||||
|
" " MTDPARTS_DEFAULT |
||||||
|
|
||||||
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \ |
||||||
|
" rootfstype=cramfs " CONFIG_COMMON_BOOT |
||||||
|
|
||||||
|
#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \ |
||||||
|
" onenand write 0x32008000 0x0 0x40000\0" |
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||||
|
CONFIG_UPDATEB \
|
||||||
|
"updatek=" \
|
||||||
|
"onenand erase 0x60000 0x300000;" \
|
||||||
|
"onenand write 0x31008000 0x60000 0x300000\0" \
|
||||||
|
"updateu=" \
|
||||||
|
"onenand erase block 147-4095;" \
|
||||||
|
"onenand write 0x32000000 0x1260000 0x8C0000\0" \
|
||||||
|
"bootk=" \
|
||||||
|
"onenand read 0x30007FC0 0x60000 0x300000;" \
|
||||||
|
"bootm 0x30007FC0\0" \
|
||||||
|
"flashboot=" \
|
||||||
|
"set bootargs root=/dev/mtdblock${bootblock} " \
|
||||||
|
"rootfstype=${rootfstype} " \
|
||||||
|
"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
|
||||||
|
"run bootk\0" \
|
||||||
|
"ubifsboot=" \
|
||||||
|
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
|
||||||
|
" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
|
||||||
|
"run bootk\0" \
|
||||||
|
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
|
||||||
|
"android=" \
|
||||||
|
"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
|
||||||
|
"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
|
||||||
|
"run bootk\0" \
|
||||||
|
"nfsboot=" \
|
||||||
|
"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
|
||||||
|
"nfsroot=${nfsroot},nolock " \
|
||||||
|
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||||
|
"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
|
||||||
|
"run bootk\0" \
|
||||||
|
"ramboot=" \
|
||||||
|
"set bootargs " CONFIG_RAMDISK_BOOT \
|
||||||
|
" initrd=0x33000000,8M ramdisk=8192\0" \
|
||||||
|
"rootfstype=cramfs\0" \
|
||||||
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||||
|
"meminfo=mem=128M\0" \
|
||||||
|
"nfsroot=/nfsroot/arm\0" \
|
||||||
|
"bootblock=5\0" \
|
||||||
|
"ubiblock=4\0" \
|
||||||
|
"ubi=enabled" |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||||
|
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||||
|
#define CONFIG_SYS_PROMPT "SMDKC100 # " |
||||||
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ |
||||||
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||||
|
/* Boot Argument Buffer Size */ |
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||||
|
/* memtest works on */ |
||||||
|
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
||||||
|
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000) |
||||||
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE |
||||||
|
|
||||||
|
#define CONFIG_SYS_HZ 1000 |
||||||
|
|
||||||
|
/* valid baudrates */ |
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Stack sizes |
||||||
|
* |
||||||
|
* The stack sizes are set up in start.S using the settings below |
||||||
|
*/ |
||||||
|
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ |
||||||
|
|
||||||
|
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ |
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 |
||||||
|
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ |
||||||
|
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_BASE 0x00000000 |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FLASH and environment organization |
||||||
|
*/ |
||||||
|
#define CONFIG_SYS_NO_FLASH 1 |
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ |
||||||
|
#define CONFIG_IDENT_STRING " for SMDKC100" |
||||||
|
|
||||||
|
#define CONFIG_SYS_64BIT_VSPRINTF |
||||||
|
|
||||||
|
#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000) |
||||||
|
#define CONFIG_ENABLE_MMU |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_ENABLE_MMU |
||||||
|
#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 |
||||||
|
#else |
||||||
|
#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE |
||||||
|
#endif |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Boot configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_ENV_IS_IN_ONENAND 1 |
||||||
|
#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */ |
||||||
|
#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */ |
||||||
|
#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */ |
||||||
|
|
||||||
|
#define CONFIG_USE_ONENAND_BOARD_INIT |
||||||
|
#define CONFIG_SAMSUNG_ONENAND 1 |
||||||
|
#define CONFIG_SYS_ONENAND_BASE 0xE7100000 |
||||||
|
|
||||||
|
#define CONFIG_DOS_PARTITION 1 |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue