Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>master
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d7a73038f5
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CONFIG_SPL=y |
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+S:CONFIG_ARM=y |
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+S:CONFIG_TARGET_SOCFPGA_ARRIA5=y |
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ |
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#define __CONFIG_SOCFPGA_ARRIA5_H__ |
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#include <asm/arch/socfpga_base_addrs.h> |
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#include "../../board/altera/socfpga/pinmux_config.h" |
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#include "../../board/altera/socfpga/iocsr_config.h" |
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#include "../../board/altera/socfpga/pll_config.h" |
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/* U-Boot Commands */ |
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#define CONFIG_SYS_NO_FLASH |
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#include <config_cmd_default.h> |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_FAT_WRITE |
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#define CONFIG_HW_WATCHDOG |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_BOOTZ |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_DFU |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_EXT4_WRITE |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_FPGA |
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#define CONFIG_CMD_FS_GENERIC |
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#define CONFIG_CMD_GREPENV |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_MMC |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_SETEXPR |
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#define CONFIG_CMD_USB |
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#define CONFIG_CMD_USB_MASS_STORAGE |
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#define CONFIG_REGEX /* Enable regular expression support */ |
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/* Memory configurations */ |
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
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/* Booting Linux */ |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_BOOTFILE "zImage" |
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#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) |
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
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#define CONFIG_BOOTCOMMAND "run ramboot" |
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#else |
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#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" |
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#endif |
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#define CONFIG_LOADADDR 0x8000 |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
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/* Ethernet on SoC (EMAC) */ |
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#if defined(CONFIG_CMD_NET) |
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#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS |
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#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
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/* PHY */ |
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#define CONFIG_PHY_MICREL |
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#define CONFIG_PHY_MICREL_KSZ9021 |
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#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" |
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#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 |
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#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" |
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#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 |
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#endif |
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/* USB */ |
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#ifdef CONFIG_CMD_USB |
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#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS |
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#endif |
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#define CONFIG_G_DNL_MANUFACTURER "Altera" |
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/* Extra Environment */ |
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#define CONFIG_HOSTNAME socfpga_arria5 |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"verify=n\0" \
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"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"bootimage=zImage\0" \
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"fdt_addr=100\0" \
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"fdtimage=socfpga.dtb\0" \
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"fsloadcmd=ext2load\0" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"mmcroot=/dev/mmcblk0p2\0" \
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"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
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" root=${mmcroot} rw rootwait;" \
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"bootz ${loadaddr} - ${fdt_addr}\0" \
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"mmcload=mmc rescan;" \
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"load mmc 0:1 ${loadaddr} ${bootimage};" \
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"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
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"qspiroot=/dev/mtdblock0\0" \
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"qspirootfstype=jffs2\0" \
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"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
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" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
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"bootm ${loadaddr} - ${fdt_addr}\0" |
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/* The rest of the configuration is shared */ |
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#include <configs/socfpga_common.h> |
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#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ |
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