Migo-R is a board based on SH7722 and has may devices. In this patch, supported SCIF, NOR flash and Ethernet. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
goda.yusuke
17 years ago
committed by
Nobuhiro Iwamatsu
parent
74d1e66d22
commit
c2042f5952
@ -0,0 +1,48 @@ |
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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# board/MigoR/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := migo_r.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,32 @@ |
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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# board/MigoR/config.mk
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# TEXT_BASE refers to image _after_ relocation.
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x8FFC0000
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@ -0,0 +1,269 @@ |
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/* |
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* Copyright (C) 2007 |
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* |
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* Copyright (C) 2007 |
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* Kenati Technologies, Inc. |
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* |
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* board/MigoR/lowlevel_init.S |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/processor.h> |
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/* |
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* Board specific low level init code, called _very_ early in the |
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* startup sequence. Relocation to SDRAM has not happened yet, no |
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* stack is available, bss section has not been initialised, etc. |
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* |
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* (Note: As no stack is available, no subroutines can be called...). |
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*/ |
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.global lowlevel_init
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.text |
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.align 2
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lowlevel_init: |
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mov.l CCR_A, r1 ! Address of Cache Control Register |
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mov.l CCR_D, r0 ! Instruction Cache Invalidate |
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mov.l r0, @r1
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mov.l MMUCR_A, r1 ! Address of MMU Control Register |
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mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit |
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mov.l r0, @r1
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mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 |
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mov.l MSTPCR0_D, r0 ! |
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mov.l r0, @r1
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mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 |
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mov.l MSTPCR2_D, r0 ! |
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mov.l r0, @r1
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mov.l PFC_PULCR_A, r1 |
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mov.w PFC_PULCR_D, r0 |
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mov.w r0,@r1
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mov.l PFC_DRVCR_A, r1 |
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mov.w PFC_DRVCR_D, r0 |
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mov.w r0, @r1
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mov.l SBSCR_A, r1 ! |
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mov.w SBSCR_D, r0 ! |
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mov.w r0, @r1
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mov.l PSCR_A, r1 ! |
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mov.w PSCR_D, r0 ! |
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mov.w r0, @r1
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mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) |
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mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max |
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mov.w r0, @r1
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mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) |
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mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear |
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mov.w r0, @r1
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mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) |
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mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms |
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mov.w r0, @r1
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mov.l DLLFRQ_A, r1 ! 20080115 |
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mov.l DLLFRQ_D, r0 ! 20080115 |
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mov.l r0, @r1
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mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register |
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mov.l FRQCR_D, r0 ! 20080115 |
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mov.l r0, @r1
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mov.l CCR_A, r1 ! Address of Cache Control Register |
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mov.l CCR_D_2, r0 ! ?? |
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mov.l r0, @r1
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bsc_init: |
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mov.l CMNCR_A, r1 ! CMNCR address -> R1 |
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mov.l CMNCR_D, r0 ! CMNCR data -> R0 |
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mov.l r0, @r1 ! CMNCR set
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mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 |
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mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 |
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mov.l r0, @r1 ! CS0BCR set
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mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 |
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mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 |
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mov.l r0, @r1 ! CS4BCR set
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mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 |
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mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 |
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mov.l r0, @r1 ! CS5ABCR set
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mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 |
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mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 |
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mov.l r0, @r1 ! CS5BBCR set
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mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 |
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mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 |
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mov.l r0, @r1 ! CS6ABCR set
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mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 |
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mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 |
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mov.l r0, @r1 ! CS0WCR set
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mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 |
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mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 |
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mov.l r0, @r1 ! CS4WCR set
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mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 |
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mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 |
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mov.l r0, @r1 ! CS5AWCR set
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mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 |
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mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 |
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mov.l r0, @r1 ! CS5BWCR set
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mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 |
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mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 |
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mov.l r0, @r1 ! CS6AWCR set
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! SDRAM initialization |
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mov.l SDCR_A, r1 ! SB_SDCR address -> R1 |
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mov.l SDCR_D, r0 ! SB_SDCR data -> R0 |
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mov.l r0, @r1 ! SB_SDCR set
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mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 |
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mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 |
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mov.l r0, @r1 ! SB_SDWCR set
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mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 |
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mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 |
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mov.l r0, @r1 ! SB_SDPCR set
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mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 |
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mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 |
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mov.l r0, @r1 ! SB_RTCOR set
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mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 |
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mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 |
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mov.l r0, @r1
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mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 |
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mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 |
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mov.l r0, @r1 ! SB_RTCSR set
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mov.l RFCR_A, r1 ! SB_RFCR address -> R1 |
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mov.l RFCR_D, r0 ! SB_RFCR data -> R0 |
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mov.l r0, @r1
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mov.l SDMR3_A, r1 ! SDMR3 address -> R1 |
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mov #0x00, r0 ! SDMR3 data -> R0 |
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mov.b r0, @r1 ! SDMR3 set
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! BL bit off (init = ON) (?!?) |
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stc sr, r0 ! BL bit off(init=ON) |
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mov.l SR_MASK_D, r1 |
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and r1, r0 |
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ldc r0, sr |
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rts |
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mov #0, r0 |
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.align 4
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CCR_A: .long CCR |
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MMUCR_A: .long MMUCR |
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MSTPCR0_A: .long MSTPCR0 |
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MSTPCR2_A: .long MSTPCR2 |
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PFC_PULCR_A: .long PULCR |
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PFC_DRVCR_A: .long DRVCR |
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SBSCR_A: .long SBSCR |
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PSCR_A: .long PSCR |
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RWTCSR_A: .long RWTCSR |
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RWTCNT_A: .long RWTCNT |
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FRQCR_A: .long FRQCR |
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PLLCR_A: .long PLLCR |
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DLLFRQ_A: .long DLLFRQ |
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CCR_D: .long 0x00000800 |
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CCR_D_2: .long 0x00000103 |
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MMUCR_D: .long 0x00000004 |
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MSTPCR0_D: .long 0x00001001 |
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MSTPCR2_D: .long 0xffffffff |
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PFC_PULCR_D: .long 0x6000 |
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PFC_DRVCR_D: .long 0x0464 |
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FRQCR_D: .long 0x07033639 |
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PLLCR_D: .long 0x00005000 |
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DLLFRQ_D: .long 0x000004F6 ! 20080115 |
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CMNCR_A: .long CMNCR |
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CMNCR_D: .long 0x0000001B ! 20080115 |
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CS0BCR_A: .long CS0BCR ! Flash bank 1 |
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CS0BCR_D: .long 0x24920400 |
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CS4BCR_A: .long CS4BCR ! |
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CS4BCR_D: .long 0x10003400 ! 20080115 |
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CS5ABCR_A: .long CS5ABCR ! |
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CS5ABCR_D: .long 0x24920400 |
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CS5BBCR_A: .long CS5BBCR ! |
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CS5BBCR_D: .long 0x24920400 |
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CS6ABCR_A: .long CS6ABCR ! |
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CS6ABCR_D: .long 0x24920400 |
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CS0WCR_A: .long CS0WCR |
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CS0WCR_D: .long 0x00000380 |
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CS4WCR_A: .long CS4WCR |
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CS4WCR_D: .long 0x00100A81 ! 20080115 |
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CS5AWCR_A: .long CS5AWCR |
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CS5AWCR_D: .long 0x00000300 |
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CS5BWCR_A: .long CS5BWCR |
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CS5BWCR_D: .long 0x00000300 |
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CS6AWCR_A: .long CS6AWCR |
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CS6AWCR_D: .long 0x00000300 |
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SDCR_A: .long SBSC_SDCR |
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SDCR_D: .long 0x80160809 ! 20080115 |
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SDWCR_A: .long SBSC_SDWCR |
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SDWCR_D: .long 0x0014450C ! 20080115 |
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SDPCR_A: .long SBSC_SDPCR |
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SDPCR_D: .long 0x00000087 |
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RTCOR_A: .long SBSC_RTCOR |
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RTCNT_A: .long SBSC_RTCNT |
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RTCNT_D: .long 0xA55A0012 |
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RTCOR_D: .long 0xA55A001C ! 20080115 |
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RTCSR_A: .long SBSC_RTCSR |
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RFCR_A: .long SBSC_RFCR |
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RFCR_D: .long 0xA55A0221 |
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RTCSR_D: .long 0xA55A009a ! 20080115 |
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SDMR3_A: .long 0xFE581180 ! 20080115 |
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SR_MASK_D: .long 0xEFFFFF0F |
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.align 2
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SBSCR_D: .word 0x0044 |
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PSCR_D: .word 0x0000 |
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RWTCSR_D_1: .word 0xA507 |
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RWTCSR_D_2: .word 0xA504 ! 20080115 |
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RWTCNT_D: .word 0x5A00 |
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@ -0,0 +1,54 @@ |
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/*
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* Copyright (C) 2007 |
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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* |
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* Copyright (C) 2007 |
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* Kenati Technologies, Inc. |
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* |
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* board/MigoR/migo_r.c |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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int checkboard(void) |
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{ |
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puts("BOARD: Renesas MigoR\n"); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int dram_init (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gd->bd->bi_memstart = CFG_SDRAM_BASE; |
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gd->bd->bi_memsize = CFG_SDRAM_SIZE; |
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printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); |
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return 0; |
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} |
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|
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void led_set_state (unsigned short value) |
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{ |
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} |
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@ -0,0 +1,106 @@ |
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/* |
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* Copyrigth (c) 2007 |
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") |
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OUTPUT_ARCH(sh) |
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ENTRY(_start) |
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|
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SECTIONS |
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{ |
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/* |
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Base address of internal SDRAM is 0x0C000000. |
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Although size of SDRAM can be either 16 or 32 MBytes, |
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we assume 16 MBytes (ie ignore upper half if the full |
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32 MBytes is present). |
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|
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NOTE: This address must match with the definition of |
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TEXT_BASE in config.mk (in this directory). |
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|
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*/ |
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. = 0x8C000000 + (64*1024*1024) - (256*1024); |
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|
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PROVIDE (reloc_dst = .); |
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|
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PROVIDE (_ftext = .); |
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PROVIDE (_fcode = .); |
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PROVIDE (_start = .); |
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|
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.text : |
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{ |
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cpu/sh4/start.o (.text) |
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. = ALIGN(8192); |
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common/environment.o (.ppcenv) |
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. = ALIGN(8192); |
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common/environment.o (.ppcenvr) |
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. = ALIGN(8192); |
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*(.text) |
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. = ALIGN(4); |
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} =0xFF |
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PROVIDE (_ecode = .); |
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.rodata : |
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{ |
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*(.rodata) |
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. = ALIGN(4); |
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} |
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PROVIDE (_etext = .); |
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|
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|
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PROVIDE (_fdata = .); |
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.data : |
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{ |
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*(.data) |
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. = ALIGN(4); |
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} |
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PROVIDE (_edata = .); |
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|
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PROVIDE (_fgot = .); |
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.got : |
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{ |
||||
*(.got) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_egot = .); |
||||
|
||||
PROVIDE (__u_boot_cmd_start = .); |
||||
.u_boot_cmd : |
||||
{ |
||||
*(.u_boot_cmd) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (__u_boot_cmd_end = .); |
||||
|
||||
PROVIDE (reloc_dst_end = .); |
||||
/* _reloc_dst_end = .; */ |
||||
|
||||
PROVIDE (bss_start = .); |
||||
PROVIDE (__bss_start = .); |
||||
.bss : |
||||
{ |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (bss_end = .); |
||||
|
||||
PROVIDE (_end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,151 @@ |
||||
/*
|
||||
* Configuation settings for the Renesas Solutions Migo-R board |
||||
* |
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __MIGO_R_H |
||||
#define __MIGO_R_H |
||||
|
||||
#undef DEBUG |
||||
#define CONFIG_SH 1 |
||||
#define CONFIG_SH4 1 |
||||
#define CONFIG_CPU_SH7722 1 |
||||
#define CONFIG_MIGO_R 1 |
||||
|
||||
#define CONFIG_CMD_LOADB |
||||
#define CONFIG_CMD_LOADS |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_DFL |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_ENV |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_IPADDR 192.168.10.100 |
||||
#define CONFIG_SERVERIP 192.168.10.77 |
||||
#define CONFIG_GATEWAYIP 192.168.10.77 |
||||
|
||||
#define CONFIG_VERSION_VARIABLE |
||||
#undef CONFIG_SHOW_BOOT_PROGRESS |
||||
|
||||
/* SMC9111 */ |
||||
#define CONFIG_DRIVER_SMC91111 |
||||
#define CONFIG_SMC91111_BASE (0xB0000000) |
||||
|
||||
/* MEMORY */ |
||||
#define MIGO_R_SDRAM_BASE (0x8C000000) |
||||
#define MIGO_R_FLASH_BASE_1 (0xA0000000) |
||||
#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ |
||||
#define CFG_PBSIZE 256 /* Buffer size for Console output */ |
||||
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ |
||||
#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ |
||||
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
||||
|
||||
/* SCIF */ |
||||
#define CFG_SCIF_CONSOLE 1 |
||||
#define CONFIG_CONS_SCIF0 1 |
||||
#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console |
||||
information at boot */ |
||||
#undef CFG_CONSOLE_OVERWRITE_ROUTINE |
||||
#undef CFG_CONSOLE_ENV_OVERWRITE |
||||
|
||||
#define CFG_MEMTEST_START (MIGO_R_SDRAM_BASE) |
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) |
||||
|
||||
/* Enable alternate, more extensive, memory test */ |
||||
#undef CFG_ALT_MEMTEST |
||||
/* Scratch address used by the alternate memory test */ |
||||
#undef CFG_MEMTEST_SCRATCH |
||||
|
||||
/* Enable temporary baudrate change while serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE |
||||
|
||||
#define CFG_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
||||
/* maybe more, but if so u-boot doesn't know about it... */ |
||||
#define CFG_SDRAM_SIZE (64 * 1024 * 1024) |
||||
/* default load address for scripts ?!? */ |
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024) |
||||
|
||||
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ |
||||
#define CFG_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
||||
/* Monitor size */ |
||||
#define CFG_MONITOR_LEN (128 * 1024) |
||||
/* Size of DRAM reserved for malloc() use */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) |
||||
/* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_SIZE (256) |
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024) |
||||
|
||||
/* FLASH */ |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#undef CFG_FLASH_QUIET_TEST |
||||
/* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
/* Physical start address of Flash memory */ |
||||
#define CFG_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
||||
/* Max number of sectors on each Flash chip */ |
||||
#define CFG_MAX_FLASH_SECT 512 |
||||
|
||||
/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } |
||||
|
||||
/* Timeout for Flash erase operations (in ms) */ |
||||
#define CFG_FLASH_ERASE_TOUT (3 * 1000) |
||||
/* Timeout for Flash write operations (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT (3 * 1000) |
||||
/* Timeout for Flash set sector lock bit operations (in ms) */ |
||||
#define CFG_FLASH_LOCK_TOUT (3 * 1000) |
||||
/* Timeout for Flash clear lock bit operations (in ms) */ |
||||
#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) |
||||
|
||||
/* Use hardware flash sectors protection instead of U-Boot software protection */ |
||||
#undef CFG_FLASH_PROTECTION |
||||
#undef CFG_DIRECT_FLASH_TFTP |
||||
|
||||
/* ENV setting */ |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#define CFG_ENV_SECT_SIZE (128 * 1024) |
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) |
||||
/* Offset of env Flash sector relative to CFG_FLASH_BASE */ |
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) |
||||
|
||||
/* Board Clock */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ |
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) |
||||
|
||||
#endif /* __MIGO_R_H */ |
||||
Loading…
Reference in new issue