Stefano Babic
11 years ago
commit
c23154aab5
@ -0,0 +1,27 @@ |
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# |
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# This list is used by git-shortlog to fix a few botched name translations |
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# in the git archive, either because the author's full name was messed up |
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# and/or not always written the same way, making contributions from the |
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# same person appearing not to be so or badly displayed. |
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# |
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# This file can be modified by hand or updated by the following command: |
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# scripts/mailmapper > tmp; mv tmp .mailmap |
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# |
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|
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Allen Martin <amartin@nvidia.com> |
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Andreas Bießmann <andreas.devel@googlemail.com> |
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Aneesh V <aneesh@ti.com> |
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Dirk Behme <dirk.behme@googlemail.com> |
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Fabio Estevam <fabio.estevam@freescale.com> |
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Jagannadha Sutradharudu Teki <402jagan@gmail.com> |
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Markus Klotzbuecher <mk@denx.de> |
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Prabhakar Kushwaha <prabhakar@freescale.com> |
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Rajeshwari Shinde <rajeshwari.s@samsung.com> |
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Sandeep Paulraj <s-paulraj@ti.com> |
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Shaohui Xie <Shaohui.Xie@freescale.com> |
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Stefan Roese <stroese> |
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Stefano Babic <sbabic@denx.de> |
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TsiChung Liew <Tsi-Chung.Liew@freescale.com> |
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Wolfgang Denk <wdenk> |
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York Sun <yorksun@freescale.com> |
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Łukasz Majewski <l.majewski@samsung.com> |
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@ -0,0 +1,101 @@ |
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/*
|
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* Keystone2: get clk rate for K2E |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/clock_defs.h> |
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|
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const struct keystone_pll_regs keystone_pll_regs[] = { |
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[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, |
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[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, |
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[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, |
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}; |
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|
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/**
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* pll_freq_get - get pll frequency |
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* Fout = Fref * NF(mult) / NR(prediv) / OD |
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* @pll: pll identifier |
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*/ |
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static unsigned long pll_freq_get(int pll) |
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{ |
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unsigned long mult = 1, prediv = 1, output_div = 2; |
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unsigned long ret; |
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u32 tmp, reg; |
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|
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if (pll == CORE_PLL) { |
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ret = external_clk[sys_clk]; |
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { |
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/* PLL mode */ |
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tmp = __raw_readl(KS2_MAINPLLCTL0); |
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prediv = (tmp & PLL_DIV_MASK) + 1; |
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mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | |
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(pllctl_reg_read(pll, mult) & |
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PLLM_MULT_LO_MASK)) + 1; |
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output_div = ((pllctl_reg_read(pll, secctl) >> |
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PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; |
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|
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ret = ret / prediv / output_div * mult; |
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} |
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} else { |
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switch (pll) { |
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case PASS_PLL: |
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ret = external_clk[pa_clk]; |
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reg = KS2_PASSPLLCTL0; |
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break; |
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case DDR3_PLL: |
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ret = external_clk[ddr3_clk]; |
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reg = KS2_DDR3APLLCTL0; |
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break; |
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default: |
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return 0; |
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} |
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|
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tmp = __raw_readl(reg); |
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|
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if (!(tmp & PLLCTL_BYPASS)) { |
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/* Bypass disabled */ |
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prediv = (tmp & PLL_DIV_MASK) + 1; |
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mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; |
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output_div = ((tmp >> PLL_CLKOD_SHIFT) & |
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PLL_CLKOD_MASK) + 1; |
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ret = ((ret / prediv) * mult) / output_div; |
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} |
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} |
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|
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return ret; |
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} |
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|
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unsigned long clk_get_rate(unsigned int clk) |
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{ |
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switch (clk) { |
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case core_pll_clk: return pll_freq_get(CORE_PLL); |
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case pass_pll_clk: return pll_freq_get(PASS_PLL); |
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case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); |
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case sys_clk0_1_clk: |
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case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); |
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case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); |
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case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); |
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case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); |
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case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; |
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case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; |
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case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; |
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case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; |
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case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; |
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case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; |
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case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; |
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case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; |
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case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; |
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case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; |
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case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; |
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default: |
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break; |
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} |
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return 0; |
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} |
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@ -0,0 +1,113 @@ |
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/*
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* Keystone2: get clk rate for K2HK |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/clock_defs.h> |
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|
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const struct keystone_pll_regs keystone_pll_regs[] = { |
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[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, |
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[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, |
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[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, |
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[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, |
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[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, |
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}; |
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|
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/**
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* pll_freq_get - get pll frequency |
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* Fout = Fref * NF(mult) / NR(prediv) / OD |
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* @pll: pll identifier |
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*/ |
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static unsigned long pll_freq_get(int pll) |
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{ |
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unsigned long mult = 1, prediv = 1, output_div = 2; |
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unsigned long ret; |
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u32 tmp, reg; |
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|
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if (pll == CORE_PLL) { |
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ret = external_clk[sys_clk]; |
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { |
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/* PLL mode */ |
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tmp = __raw_readl(KS2_MAINPLLCTL0); |
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prediv = (tmp & PLL_DIV_MASK) + 1; |
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mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | |
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(pllctl_reg_read(pll, mult) & |
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PLLM_MULT_LO_MASK)) + 1; |
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output_div = ((pllctl_reg_read(pll, secctl) >> |
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PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; |
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|
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ret = ret / prediv / output_div * mult; |
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} |
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} else { |
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switch (pll) { |
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case PASS_PLL: |
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ret = external_clk[pa_clk]; |
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reg = KS2_PASSPLLCTL0; |
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break; |
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case TETRIS_PLL: |
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ret = external_clk[tetris_clk]; |
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reg = KS2_ARMPLLCTL0; |
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break; |
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case DDR3A_PLL: |
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ret = external_clk[ddr3a_clk]; |
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reg = KS2_DDR3APLLCTL0; |
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break; |
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case DDR3B_PLL: |
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ret = external_clk[ddr3b_clk]; |
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reg = KS2_DDR3BPLLCTL0; |
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break; |
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default: |
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return 0; |
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} |
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tmp = __raw_readl(reg); |
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if (!(tmp & PLLCTL_BYPASS)) { |
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/* Bypass disabled */ |
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prediv = (tmp & PLL_DIV_MASK) + 1; |
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mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; |
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output_div = ((tmp >> PLL_CLKOD_SHIFT) & |
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PLL_CLKOD_MASK) + 1; |
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ret = ((ret / prediv) * mult) / output_div; |
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} |
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} |
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|
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return ret; |
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} |
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|
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unsigned long clk_get_rate(unsigned int clk) |
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{ |
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switch (clk) { |
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case core_pll_clk: return pll_freq_get(CORE_PLL); |
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case pass_pll_clk: return pll_freq_get(PASS_PLL); |
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case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); |
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case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); |
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case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); |
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case sys_clk0_1_clk: |
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case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); |
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case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); |
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case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); |
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case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); |
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case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; |
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case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; |
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case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; |
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case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; |
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case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; |
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case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; |
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case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; |
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case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; |
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case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; |
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case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; |
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case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; |
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default: |
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break; |
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} |
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return 0; |
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} |
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@ -0,0 +1,87 @@ |
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/*
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* Keystone EVM : Board initialization |
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* |
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* (C) Copyright 2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/mon.h> |
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#include <asm/arch/psc_defs.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/hardware.h> |
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|
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/**
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* cpu_to_bus - swap bytes of the 32-bit data if the device is BE |
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* @ptr - array of data |
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* @length - lenght of data array |
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*/ |
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int cpu_to_bus(u32 *ptr, u32 length) |
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{ |
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u32 i; |
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|
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if (!(readl(KS2_DEVSTAT) & 0x1)) |
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for (i = 0; i < length; i++, ptr++) |
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*ptr = cpu_to_be32(*ptr); |
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return 0; |
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} |
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static int turn_off_myself(void) |
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{ |
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printf("Turning off ourselves\r\n"); |
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mon_power_off(0); |
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psc_disable_module(KS2_LPSC_TETRIS); |
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psc_disable_domain(KS2_TETRIS_PWR_DOMAIN); |
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asm volatile ("isb\n" |
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"dsb\n" |
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"wfi\n"); |
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printf("What! Should not see that\n"); |
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return 0; |
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} |
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static void turn_off_all_dsps(int num_dsps) |
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{ |
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int i; |
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for (i = 0; i < num_dsps; i++) { |
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if (psc_disable_module(i + KS2_LPSC_GEM_0)) |
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printf("Cannot disable module for #%d DSP", i); |
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if (psc_disable_domain(i + 8)) |
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printf("Cannot disable domain for #%d DSP", i); |
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} |
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} |
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int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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return turn_off_myself(); |
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} |
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|
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U_BOOT_CMD( |
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killme, 1, 0, do_killme_cmd, |
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"turn off main ARM core", |
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"turn off main ARM core. Should not live after that :(\n" |
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); |
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|
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int misc_init_r(void) |
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{ |
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char *env; |
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long ks2_debug = 0; |
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env = getenv("ks2_debug"); |
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|
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if (env) |
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ks2_debug = simple_strtol(env, NULL, 0); |
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|
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if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0) |
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turn_off_all_dsps(KS2_NUM_DSPS); |
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return 0; |
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} |
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@ -1,139 +0,0 @@ |
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/*
|
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* (C) Copyright 2008 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Author : |
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* Manikandan Pillai <mani.pillai@ti.com> |
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* |
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* Initial Code from: |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* Syed Mohammed Khasim <khasim@ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/sys_proto.h> |
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#include <command.h> |
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|
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struct gpmc *gpmc_cfg; |
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|
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#if defined(CONFIG_CMD_NAND) |
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static const u32 gpmc_m_nand[GPMC_MAX_REG] = { |
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M_NAND_GPMC_CONFIG1, |
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M_NAND_GPMC_CONFIG2, |
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M_NAND_GPMC_CONFIG3, |
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M_NAND_GPMC_CONFIG4, |
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M_NAND_GPMC_CONFIG5, |
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M_NAND_GPMC_CONFIG6, 0 |
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}; |
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#endif /* CONFIG_CMD_NAND */ |
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|
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#if defined(CONFIG_CMD_ONENAND) |
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static const u32 gpmc_onenand[GPMC_MAX_REG] = { |
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ONENAND_GPMC_CONFIG1, |
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ONENAND_GPMC_CONFIG2, |
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ONENAND_GPMC_CONFIG3, |
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ONENAND_GPMC_CONFIG4, |
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ONENAND_GPMC_CONFIG5, |
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ONENAND_GPMC_CONFIG6, 0 |
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}; |
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#endif /* CONFIG_CMD_ONENAND */ |
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|
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/********************************************************
|
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* mem_ok() - test used to see if timings are correct |
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* for a part. Helps in guessing which part |
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* we are currently using. |
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*******************************************************/ |
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u32 mem_ok(u32 cs) |
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{ |
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u32 val1, val2, addr; |
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u32 pattern = 0x12345678; |
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|
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); |
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|
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writel(0x0, addr + 0x400); /* clear pos A */ |
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writel(pattern, addr); /* pattern to pos B */ |
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writel(0x0, addr + 4); /* remove pattern off the bus */ |
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val1 = readl(addr + 0x400); /* get pos A value */ |
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val2 = readl(addr); /* get val2 */ |
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writel(0x0, addr + 0x400); /* clear pos A */ |
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|
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ |
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return 0; |
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else |
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return 1; |
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} |
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|
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, |
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u32 size) |
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{ |
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writel(0, &cs->config7); |
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sdelay(1000); |
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/* Delay for settling */ |
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writel(gpmc_config[0], &cs->config1); |
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writel(gpmc_config[1], &cs->config2); |
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writel(gpmc_config[2], &cs->config3); |
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writel(gpmc_config[3], &cs->config4); |
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writel(gpmc_config[4], &cs->config5); |
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writel(gpmc_config[5], &cs->config6); |
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|
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/*
|
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* Enable the config. size is the CS size and goes in |
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* bits 11:8. We set bit 6 to enable this CS and the base |
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* address goes into bits 5:0. |
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*/ |
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writel((size << 8) | (GPMC_CS_ENABLE << 6) | |
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((base >> 24) & GPMC_BASEADDR_MASK), |
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&cs->config7); |
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sdelay(2000); |
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} |
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|
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/*****************************************************
|
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* gpmc_init(): init gpmc bus |
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* Init GPMC for x16, MuxMode (SDRAM in x32). |
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* This code can only be executed from SRAM or SDRAM. |
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*****************************************************/ |
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void gpmc_init(void) |
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{ |
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/* putting a blanket check on GPMC based on ZeBu for now */ |
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gpmc_cfg = (struct gpmc *)GPMC_BASE; |
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#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) |
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const u32 *gpmc_config = NULL; |
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u32 base = 0; |
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u32 size = 0; |
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#endif |
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u32 config = 0; |
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|
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/* global settings */ |
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ |
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ |
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|
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config = readl(&gpmc_cfg->config); |
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config &= (~0xf00); |
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writel(config, &gpmc_cfg->config); |
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|
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/*
|
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* Disable the GPMC0 config set by ROM code |
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* It conflicts with our MPDB (both at 0x08000000) |
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*/ |
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writel(0, &gpmc_cfg->cs[0].config7); |
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sdelay(1000); |
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|
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#if defined(CONFIG_CMD_NAND) /* CS 0 */ |
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gpmc_config = gpmc_m_nand; |
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|
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base = PISMO1_NAND_BASE; |
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size = PISMO1_NAND_SIZE; |
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); |
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#endif |
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|
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#if defined(CONFIG_CMD_ONENAND) |
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gpmc_config = gpmc_onenand; |
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base = PISMO1_ONEN_BASE; |
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size = PISMO1_ONEN_SIZE; |
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); |
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#endif |
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} |
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@ -0,0 +1,102 @@ |
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/* |
||||
* Copyright (C) 2013,2014 - ARM Ltd |
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>. |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <linux/linkage.h> |
||||
#include <asm/psci.h> |
||||
|
||||
.pushsection ._secure.text, "ax" |
||||
|
||||
.arch_extension sec
|
||||
|
||||
.align 5
|
||||
.globl _psci_vectors
|
||||
_psci_vectors: |
||||
b default_psci_vector @ reset
|
||||
b default_psci_vector @ undef
|
||||
b _smc_psci @ smc
|
||||
b default_psci_vector @ pabort
|
||||
b default_psci_vector @ dabort
|
||||
b default_psci_vector @ hyp
|
||||
b default_psci_vector @ irq
|
||||
b psci_fiq_enter @ fiq
|
||||
|
||||
ENTRY(psci_fiq_enter) |
||||
movs pc, lr |
||||
ENDPROC(psci_fiq_enter) |
||||
.weak psci_fiq_enter
|
||||
|
||||
ENTRY(default_psci_vector) |
||||
movs pc, lr |
||||
ENDPROC(default_psci_vector) |
||||
.weak default_psci_vector
|
||||
|
||||
ENTRY(psci_cpu_suspend) |
||||
ENTRY(psci_cpu_off) |
||||
ENTRY(psci_cpu_on) |
||||
ENTRY(psci_migrate) |
||||
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) |
||||
mov pc, lr |
||||
ENDPROC(psci_migrate) |
||||
ENDPROC(psci_cpu_on) |
||||
ENDPROC(psci_cpu_off) |
||||
ENDPROC(psci_cpu_suspend) |
||||
.weak psci_cpu_suspend
|
||||
.weak psci_cpu_off
|
||||
.weak psci_cpu_on
|
||||
.weak psci_migrate
|
||||
|
||||
_psci_table: |
||||
.word ARM_PSCI_FN_CPU_SUSPEND
|
||||
.word psci_cpu_suspend
|
||||
.word ARM_PSCI_FN_CPU_OFF
|
||||
.word psci_cpu_off
|
||||
.word ARM_PSCI_FN_CPU_ON
|
||||
.word psci_cpu_on
|
||||
.word ARM_PSCI_FN_MIGRATE
|
||||
.word psci_migrate
|
||||
.word 0
|
||||
.word 0
|
||||
|
||||
_smc_psci: |
||||
push {r4-r7,lr} |
||||
|
||||
@ Switch to secure
|
||||
mrc p15, 0, r7, c1, c1, 0 |
||||
bic r4, r7, #1 |
||||
mcr p15, 0, r4, c1, c1, 0 |
||||
isb |
||||
|
||||
adr r4, _psci_table |
||||
1: ldr r5, [r4] @ Load PSCI function ID
|
||||
ldr r6, [r4, #4] @ Load target PC
|
||||
cmp r5, #0 @ If reach the end, bail out
|
||||
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid) |
||||
beq 2f |
||||
cmp r0, r5 @ If not matching, try next entry
|
||||
addne r4, r4, #8 |
||||
bne 1b |
||||
|
||||
blx r6 @ Execute PSCI function
|
||||
|
||||
@ Switch back to non-secure
|
||||
2: mcr p15, 0, r7, c1, c1, 0 |
||||
|
||||
pop {r4-r7, lr} |
||||
movs pc, lr @ Return to the kernel
|
||||
|
||||
.popsection |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,100 @@ |
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd |
||||
* Author: Marc Zyngier <marc.zyngier@arm.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <stdio_dev.h> |
||||
#include <linux/ctype.h> |
||||
#include <linux/types.h> |
||||
#include <asm/global_data.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/armv7.h> |
||||
#include <asm/psci.h> |
||||
|
||||
static int fdt_psci(void *fdt) |
||||
{ |
||||
#ifdef CONFIG_ARMV7_PSCI |
||||
int nodeoff; |
||||
int tmp; |
||||
|
||||
nodeoff = fdt_path_offset(fdt, "/cpus"); |
||||
if (nodeoff < 0) { |
||||
printf("couldn't find /cpus\n"); |
||||
return nodeoff; |
||||
} |
||||
|
||||
/* add 'enable-method = "psci"' to each cpu node */ |
||||
for (tmp = fdt_first_subnode(fdt, nodeoff); |
||||
tmp >= 0; |
||||
tmp = fdt_next_subnode(fdt, tmp)) { |
||||
const struct fdt_property *prop; |
||||
int len; |
||||
|
||||
prop = fdt_get_property(fdt, tmp, "device_type", &len); |
||||
if (!prop) |
||||
continue; |
||||
if (len < 4) |
||||
continue; |
||||
if (strcmp(prop->data, "cpu")) |
||||
continue; |
||||
|
||||
fdt_setprop_string(fdt, tmp, "enable-method", "psci"); |
||||
} |
||||
|
||||
nodeoff = fdt_path_offset(fdt, "/psci"); |
||||
if (nodeoff < 0) { |
||||
nodeoff = fdt_path_offset(fdt, "/"); |
||||
if (nodeoff < 0) |
||||
return nodeoff; |
||||
|
||||
nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); |
||||
if (nodeoff < 0) |
||||
return nodeoff; |
||||
} |
||||
|
||||
tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci"); |
||||
if (tmp) |
||||
return tmp; |
||||
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); |
||||
if (tmp) |
||||
return tmp; |
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND); |
||||
if (tmp) |
||||
return tmp; |
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF); |
||||
if (tmp) |
||||
return tmp; |
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON); |
||||
if (tmp) |
||||
return tmp; |
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE); |
||||
if (tmp) |
||||
return tmp; |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int armv7_update_dt(void *fdt) |
||||
{ |
||||
#ifndef CONFIG_ARMV7_SECURE_BASE |
||||
/* secure code lives in RAM, keep it alive */ |
||||
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, |
||||
__secure_end - __secure_start); |
||||
#endif |
||||
|
||||
return fdt_psci(fdt); |
||||
} |
||||
@ -0,0 +1,68 @@ |
||||
/*
|
||||
* K2E: Clock management APIs |
||||
* |
||||
* (C) Copyright 2012-2014 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_K2E_H |
||||
#define __ASM_ARCH_CLOCK_K2E_H |
||||
|
||||
enum ext_clk_e { |
||||
sys_clk, |
||||
alt_core_clk, |
||||
pa_clk, |
||||
ddr3_clk, |
||||
mcm_clk, |
||||
pcie_clk, |
||||
sgmii_clk, |
||||
xgmii_clk, |
||||
usb_clk, |
||||
ext_clk_count /* number of external clocks */ |
||||
}; |
||||
|
||||
extern unsigned int external_clk[ext_clk_count]; |
||||
|
||||
enum clk_e { |
||||
core_pll_clk, |
||||
pass_pll_clk, |
||||
ddr3_pll_clk, |
||||
sys_clk0_clk, |
||||
sys_clk0_1_clk, |
||||
sys_clk0_2_clk, |
||||
sys_clk0_3_clk, |
||||
sys_clk0_4_clk, |
||||
sys_clk0_6_clk, |
||||
sys_clk0_8_clk, |
||||
sys_clk0_12_clk, |
||||
sys_clk0_24_clk, |
||||
sys_clk1_clk, |
||||
sys_clk1_3_clk, |
||||
sys_clk1_4_clk, |
||||
sys_clk1_6_clk, |
||||
sys_clk1_12_clk, |
||||
sys_clk2_clk, |
||||
sys_clk3_clk |
||||
}; |
||||
|
||||
#define KS2_CLK1_6 sys_clk0_6_clk |
||||
|
||||
/* PLL identifiers */ |
||||
enum pll_type_e { |
||||
CORE_PLL, |
||||
PASS_PLL, |
||||
DDR3_PLL, |
||||
}; |
||||
|
||||
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} |
||||
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} |
||||
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} |
||||
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} |
||||
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} |
||||
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} |
||||
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} |
||||
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} |
||||
|
||||
#endif |
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* DDR3 |
||||
* |
||||
* (C) Copyright 2014 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _DDR3_H_ |
||||
#define _DDR3_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
struct ddr3_phy_config { |
||||
unsigned int pllcr; |
||||
unsigned int pgcr1_mask; |
||||
unsigned int pgcr1_val; |
||||
unsigned int ptr0; |
||||
unsigned int ptr1; |
||||
unsigned int ptr2; |
||||
unsigned int ptr3; |
||||
unsigned int ptr4; |
||||
unsigned int dcr_mask; |
||||
unsigned int dcr_val; |
||||
unsigned int dtpr0; |
||||
unsigned int dtpr1; |
||||
unsigned int dtpr2; |
||||
unsigned int mr0; |
||||
unsigned int mr1; |
||||
unsigned int mr2; |
||||
unsigned int dtcr; |
||||
unsigned int pgcr2; |
||||
unsigned int zq0cr1; |
||||
unsigned int zq1cr1; |
||||
unsigned int zq2cr1; |
||||
unsigned int pir_v1; |
||||
unsigned int pir_v2; |
||||
}; |
||||
|
||||
struct ddr3_emif_config { |
||||
unsigned int sdcfg; |
||||
unsigned int sdtim1; |
||||
unsigned int sdtim2; |
||||
unsigned int sdtim3; |
||||
unsigned int sdtim4; |
||||
unsigned int zqcfg; |
||||
unsigned int sdrfc; |
||||
}; |
||||
|
||||
void ddr3_init(void); |
||||
void ddr3_reset_ddrphy(void); |
||||
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); |
||||
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); |
||||
|
||||
#endif |
||||
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* K2E: SoC definitions |
||||
* |
||||
* (C) Copyright 2012-2014 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_K2E_H |
||||
#define __ASM_ARCH_HARDWARE_K2E_H |
||||
|
||||
/* PA SS Registers */ |
||||
#define KS2_PASS_BASE 0x24000000 |
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */ |
||||
#define KS2_LPSC_MOD_RST 0 |
||||
#define KS2_LPSC_USB_1 1 |
||||
#define KS2_LPSC_USB 2 |
||||
#define KS2_LPSC_EMIF25_SPI 3 |
||||
#define KS2_LPSC_TSIP 4 |
||||
#define KS2_LPSC_DEBUGSS_TRC 5 |
||||
#define KS2_LPSC_TETB_TRC 6 |
||||
#define KS2_LPSC_PKTPROC 7 |
||||
#define KS2_LPSC_PA KS2_LPSC_PKTPROC |
||||
#define KS2_LPSC_SGMII 8 |
||||
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII |
||||
#define KS2_LPSC_CRYPTO 9 |
||||
#define KS2_LPSC_PCIE 10 |
||||
#define KS2_LPSC_VUSR0 12 |
||||
#define KS2_LPSC_CHIP_SRSS 13 |
||||
#define KS2_LPSC_MSMC 14 |
||||
#define KS2_LPSC_EMIF4F_DDR3 23 |
||||
#define KS2_LPSC_PCIE_1 27 |
||||
#define KS2_LPSC_XGE 50 |
||||
|
||||
/* Chip Interrupt Controller */ |
||||
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ |
||||
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ |
||||
|
||||
/* Number of DSP cores */ |
||||
#define KS2_NUM_DSPS 1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* K2HK: secure kernel command header file |
||||
* |
||||
* (C) Copyright 2014 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _MON_H_ |
||||
#define _MON_H_ |
||||
|
||||
int mon_power_off(int core_id); |
||||
|
||||
#endif |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* MSMC controller |
||||
* |
||||
* (C) Copyright 2014 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _MSMC_H_ |
||||
#define _MSMC_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
void msmc_share_all_segments(int priv_id); |
||||
|
||||
#endif |
||||
@ -0,0 +1,176 @@ |
||||
#ifndef __ASM_R8A7794_H__ |
||||
#define __ASM_R8A7794_H__ |
||||
|
||||
/* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function |
||||
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU |
||||
*/ |
||||
enum { |
||||
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, |
||||
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, |
||||
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, |
||||
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, |
||||
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, |
||||
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, |
||||
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, |
||||
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, |
||||
|
||||
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, |
||||
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, |
||||
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, |
||||
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, |
||||
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, |
||||
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, |
||||
GPIO_GP_1_24, GPIO_GP_1_25, |
||||
|
||||
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, |
||||
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, |
||||
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, |
||||
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, |
||||
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, |
||||
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, |
||||
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, |
||||
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, |
||||
|
||||
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, |
||||
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, |
||||
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, |
||||
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, |
||||
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, |
||||
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, |
||||
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, |
||||
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, |
||||
|
||||
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, |
||||
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, |
||||
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, |
||||
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, |
||||
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, |
||||
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, |
||||
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, |
||||
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, |
||||
|
||||
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, |
||||
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, |
||||
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, |
||||
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, |
||||
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, |
||||
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, |
||||
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, |
||||
|
||||
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, |
||||
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, |
||||
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, |
||||
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, |
||||
GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, |
||||
GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, |
||||
GPIO_GP_6_24, GPIO_GP_6_25, |
||||
|
||||
GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0, |
||||
GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, |
||||
GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, |
||||
GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2, |
||||
GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, |
||||
GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0, |
||||
GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3, |
||||
|
||||
/*
|
||||
* From IPSR0 to IPSR5 have been removed because they does not use. |
||||
*/ |
||||
|
||||
/* IPSR6 */ |
||||
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28, |
||||
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, |
||||
GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, |
||||
GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, |
||||
GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK, |
||||
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1, |
||||
GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1, |
||||
GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4, |
||||
GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4, |
||||
GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7, |
||||
GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL, |
||||
GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7, |
||||
GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C, |
||||
GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N, |
||||
GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C, |
||||
GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B, |
||||
GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN, |
||||
GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B, |
||||
GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI, |
||||
|
||||
/* IPSR7 */ |
||||
GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B, |
||||
GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO, |
||||
GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B, |
||||
GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK, |
||||
GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B, |
||||
GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N, |
||||
GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B, |
||||
GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1, |
||||
GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B, |
||||
GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2, |
||||
GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C, |
||||
GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7, |
||||
GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6, |
||||
GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0, |
||||
GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7, |
||||
GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1, |
||||
GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B, |
||||
GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B, |
||||
GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B, |
||||
GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD, |
||||
|
||||
/* IPSR8 */ |
||||
GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B, |
||||
GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B, |
||||
GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C, |
||||
GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B, |
||||
GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C, |
||||
GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B, |
||||
GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D, |
||||
GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B, |
||||
GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D, |
||||
GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B, |
||||
GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS, |
||||
GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C, |
||||
GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D, |
||||
GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0, |
||||
GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL, |
||||
GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B, |
||||
GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA, |
||||
GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B, |
||||
GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD, |
||||
GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2, |
||||
GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK, |
||||
|
||||
/*
|
||||
* From IPSR9 to IPSR10 have been removed because they does not use. |
||||
*/ |
||||
|
||||
/* IPSR11 */ |
||||
GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C, |
||||
GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, |
||||
GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1, |
||||
GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B, |
||||
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6, |
||||
GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, |
||||
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B, |
||||
GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, |
||||
GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B, |
||||
GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78, |
||||
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE, |
||||
GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8, |
||||
GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N, |
||||
GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D, |
||||
GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129, |
||||
GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B, |
||||
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B, |
||||
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B, |
||||
|
||||
/*
|
||||
* From IPSR12 to IPSR13 have been removed because they does not use. |
||||
*/ |
||||
}; |
||||
|
||||
#endif /* __ASM_R8A7794_H__ */ |
||||
@ -0,0 +1,14 @@ |
||||
/*
|
||||
* arch/arm/include/asm/arch-rmobile/r8a7794.h |
||||
* |
||||
* Copyright (C) 2014 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_R8A7794_H |
||||
#define __ASM_ARCH_R8A7794_H |
||||
|
||||
#include "rcar-base.h" |
||||
|
||||
#endif /* __ASM_ARCH_R8A7794_H */ |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* Copyright 2014 - Hans de Goede <hdegoede@redhat.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _SUNXI_I2C_H_ |
||||
#define _SUNXI_I2C_H_ |
||||
|
||||
#include <asm/arch/cpu.h> |
||||
|
||||
#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE |
||||
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ |
||||
#define CONFIG_SYS_TCLK 24000000 |
||||
|
||||
#endif |
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd |
||||
* Author: Marc Zyngier <marc.zyngier@arm.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef __ARM_PSCI_H__ |
||||
#define __ARM_PSCI_H__ |
||||
|
||||
/* PSCI interface */ |
||||
#define ARM_PSCI_FN_BASE 0x95c1ba5e |
||||
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) |
||||
|
||||
#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) |
||||
#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) |
||||
#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) |
||||
#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) |
||||
|
||||
#define ARM_PSCI_RET_SUCCESS 0 |
||||
#define ARM_PSCI_RET_NI (-1) |
||||
#define ARM_PSCI_RET_INVAL (-2) |
||||
#define ARM_PSCI_RET_DENIED (-3) |
||||
|
||||
#endif /* __ARM_PSCI_H__ */ |
||||
@ -0,0 +1,26 @@ |
||||
#ifndef __ASM_SECURE_H |
||||
#define __ASM_SECURE_H |
||||
|
||||
#include <config.h> |
||||
|
||||
#ifdef CONFIG_ARMV7_SECURE_BASE |
||||
/*
|
||||
* Warning, horror ahead. |
||||
* |
||||
* The target code lives in our "secure ram", but u-boot doesn't know |
||||
* that, and has blindly added reloc_off to every relocation |
||||
* entry. Gahh. Do the opposite conversion. This hack also prevents |
||||
* GCC from generating code veeners, which u-boot doesn't relocate at |
||||
* all... |
||||
*/ |
||||
#define secure_ram_addr(_fn) ({ \ |
||||
DECLARE_GLOBAL_DATA_PTR; \
|
||||
void *__fn = _fn; \
|
||||
typeof(_fn) *__tmp = (__fn - gd->reloc_off); \
|
||||
__tmp; \
|
||||
}) |
||||
#else |
||||
#define secure_ram_addr(_fn) (_fn) |
||||
#endif |
||||
|
||||
#endif |
||||
@ -1,76 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu |
||||
* Copyright (C) 2008 Renesas Solutions Corp. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") |
||||
OUTPUT_ARCH(sh) |
||||
ENTRY(_start) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* |
||||
* entry and reloct_dst will be provided via ldflags |
||||
*/ |
||||
. = .; |
||||
|
||||
PROVIDE (_ftext = .); |
||||
PROVIDE (_fcode = .); |
||||
PROVIDE (_start = .); |
||||
|
||||
.text : |
||||
{ |
||||
KEEP(arch/sh/cpu/sh2/start.o (.text)) |
||||
. = ALIGN(8192); |
||||
common/env_embedded.o (.ppcenv) |
||||
. = ALIGN(8192); |
||||
common/env_embedded.o (.ppcenvr) |
||||
. = ALIGN(8192); |
||||
*(.text) |
||||
. = ALIGN(4); |
||||
} =0xFF |
||||
PROVIDE (_ecode = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_etext = .); |
||||
|
||||
|
||||
PROVIDE (_fdata = .); |
||||
.data : |
||||
{ |
||||
*(.data) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_edata = .); |
||||
|
||||
PROVIDE (_fgot = .); |
||||
.got : |
||||
{ |
||||
*(.got) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_egot = .); |
||||
|
||||
|
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
PROVIDE (reloc_dst_end = .); |
||||
|
||||
PROVIDE (bss_start = .); |
||||
PROVIDE (__bss_start = .); |
||||
.bss : |
||||
{ |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (bss_end = .); |
||||
|
||||
PROVIDE (__bss_end = .); |
||||
} |
||||
@ -1,80 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2007 |
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
||||
* |
||||
* Copyright (C) 2008-2009 |
||||
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") |
||||
OUTPUT_ARCH(sh) |
||||
ENTRY(_start) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* |
||||
* entry and reloct_dst will be provided via ldflags |
||||
*/ |
||||
. = .; |
||||
|
||||
PROVIDE (_ftext = .); |
||||
PROVIDE (_fcode = .); |
||||
PROVIDE (_start = .); |
||||
|
||||
.text : |
||||
{ |
||||
KEEP(arch/sh/cpu/sh4/start.o (.text)) |
||||
. = ALIGN(8192); |
||||
common/env_embedded.o (.ppcenv) |
||||
. = ALIGN(8192); |
||||
common/env_embedded.o (.ppcenvr) |
||||
. = ALIGN(8192); |
||||
*(.text) |
||||
. = ALIGN(4); |
||||
} =0xFF |
||||
PROVIDE (_ecode = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_etext = .); |
||||
|
||||
|
||||
PROVIDE (_fdata = .); |
||||
.data : |
||||
{ |
||||
*(.data) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_edata = .); |
||||
|
||||
PROVIDE (_fgot = .); |
||||
.got : |
||||
{ |
||||
*(.got) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (_egot = .); |
||||
|
||||
|
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
PROVIDE (reloc_dst_end = .); |
||||
/* _reloc_dst_end = .; */ |
||||
|
||||
PROVIDE (bss_start = .); |
||||
PROVIDE (__bss_start = .); |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
PROVIDE (bss_end = .); |
||||
|
||||
PROVIDE (__bss_end = .); |
||||
} |
||||
@ -1,143 +0,0 @@ |
||||
/* |
||||
* Linker script for Gaisler Research AB's GR-CPCI-AX2000 board |
||||
* with template design. |
||||
* |
||||
* (C) Copyright 2008 |
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
||||
OUTPUT_ARCH(sparc) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
|
||||
.text : { |
||||
_load_addr = .; |
||||
_text = .; |
||||
|
||||
*(.start) |
||||
arch/sparc/cpu/leon3/start.o (.text) |
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ |
||||
. = ALIGN(8192); |
||||
/* PROM CODE, Will be relocated to the end of memory, |
||||
* no global data accesses please. |
||||
*/ |
||||
__prom_start = .; |
||||
*(.prom.pgt) |
||||
*(.prom.data) |
||||
*(.prom.text) |
||||
. = ALIGN(16); |
||||
__prom_end = .; |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.gnu.warning) |
||||
/* *(.got1)*/ |
||||
. = ALIGN(16); |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
. = ALIGN(4); |
||||
_etext = .; |
||||
|
||||
/* CMD Table */ |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.data.rel) |
||||
*(.data.rel.*) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = ALIGN(4); |
||||
__got_start = .; |
||||
.got : { |
||||
*(.got) |
||||
/* *(.data.rel) |
||||
*(.data.rel.local)*/ |
||||
. = ALIGN(16); |
||||
} |
||||
__got_end = .; |
||||
|
||||
/* .data.rel : { } */ |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(16); /* to speed clearing of bss up */ |
||||
} |
||||
__bss_end = . ; |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
/* Relocated into main memory */ |
||||
|
||||
/* Start of main memory */ |
||||
/*. = 0x40000000;*/ |
||||
|
||||
.stack (NOLOAD) : { *(.stack) } |
||||
|
||||
/* PROM CODE */ |
||||
|
||||
/* global data in RAM passed to kernel after booting */ |
||||
|
||||
.stab 0 : { *(.stab) } |
||||
.stabstr 0 : { *(.stabstr) } |
||||
.stab.excl 0 : { *(.stab.excl) } |
||||
.stab.exclstr 0 : { *(.stab.exclstr) } |
||||
.stab.index 0 : { *(.stab.index) } |
||||
.stab.indexstr 0 : { *(.stab.indexstr) } |
||||
.comment 0 : { *(.comment) } |
||||
|
||||
} |
||||
@ -1,143 +0,0 @@ |
||||
/* |
||||
* Linker script for Gaisler Research AB's Template design |
||||
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA. |
||||
* |
||||
* (C) Copyright 2008 |
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
||||
OUTPUT_ARCH(sparc) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
|
||||
.text : { |
||||
_load_addr = .; |
||||
_text = .; |
||||
|
||||
*(.start) |
||||
arch/sparc/cpu/leon3/start.o (.text) |
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ |
||||
. = ALIGN(8192); |
||||
/* PROM CODE, Will be relocated to the end of memory, |
||||
* no global data accesses please. |
||||
*/ |
||||
__prom_start = .; |
||||
*(.prom.pgt) |
||||
*(.prom.data) |
||||
*(.prom.text) |
||||
. = ALIGN(16); |
||||
__prom_end = .; |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.gnu.warning) |
||||
/* *(.got1)*/ |
||||
. = ALIGN(16); |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
. = ALIGN(4); |
||||
_etext = .; |
||||
|
||||
/* CMD Table */ |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.data.rel) |
||||
*(.data.rel.*) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = ALIGN(4); |
||||
__got_start = .; |
||||
.got : { |
||||
*(.got) |
||||
/* *(.data.rel) |
||||
*(.data.rel.local)*/ |
||||
. = ALIGN(16); |
||||
} |
||||
__got_end = .; |
||||
|
||||
/* .data.rel : { } */ |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(16); /* to speed clearing of bss up */ |
||||
} |
||||
__bss_end = . ; |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
/* Relocated into main memory */ |
||||
|
||||
/* Start of main memory */ |
||||
/*. = 0x40000000;*/ |
||||
|
||||
.stack (NOLOAD) : { *(.stack) } |
||||
|
||||
/* PROM CODE */ |
||||
|
||||
/* global data in RAM passed to kernel after booting */ |
||||
|
||||
.stab 0 : { *(.stab) } |
||||
.stabstr 0 : { *(.stabstr) } |
||||
.stab.excl 0 : { *(.stab.excl) } |
||||
.stab.exclstr 0 : { *(.stab.exclstr) } |
||||
.stab.index 0 : { *(.stab.index) } |
||||
.stab.indexstr 0 : { *(.stab.indexstr) } |
||||
.comment 0 : { *(.comment) } |
||||
|
||||
} |
||||
@ -1,145 +0,0 @@ |
||||
/* |
||||
* Linker script for Gaisler Research AB's GR-XC3S-1500 board |
||||
* with template design. |
||||
* |
||||
* (C) Copyright 2007 |
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
||||
OUTPUT_ARCH(sparc) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
|
||||
.text : { |
||||
_load_addr = .; |
||||
_text = .; |
||||
|
||||
*(.start) |
||||
arch/sparc/cpu/leon3/start.o (.text) |
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ |
||||
. = ALIGN(8192); |
||||
/* PROM CODE, Will be relocated to the end of memory, |
||||
* no global data accesses please. |
||||
*/ |
||||
__prom_start = .; |
||||
*(.prom.pgt) |
||||
*(.prom.data) |
||||
*(.prom.text) |
||||
. = ALIGN(16); |
||||
__prom_end = .; |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.gnu.warning) |
||||
/* *(.got1)*/ |
||||
. = ALIGN(16); |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
. = ALIGN(4); |
||||
_etext = .; |
||||
|
||||
/* CMD Table */ |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.data.rel) |
||||
*(.data.rel.*) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = ALIGN(4); |
||||
__got_start = .; |
||||
.got : { |
||||
*(.got) |
||||
/* *(.data.rel) |
||||
*(.data.rel.local)*/ |
||||
. = ALIGN(16); |
||||
} |
||||
__got_end = .; |
||||
|
||||
/* .data.rel : { } */ |
||||
|
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(16); /* to speed clearing of bss up */ |
||||
} |
||||
__bss_end = . ; |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
/* Relocated into main memory */ |
||||
|
||||
/* Start of main memory */ |
||||
/*. = 0x40000000;*/ |
||||
|
||||
.stack (NOLOAD) : { *(.stack) } |
||||
|
||||
/* PROM CODE */ |
||||
|
||||
/* global data in RAM passed to kernel after booting */ |
||||
|
||||
|
||||
.stab 0 : { *(.stab) } |
||||
.stabstr 0 : { *(.stabstr) } |
||||
.stab.excl 0 : { *(.stab.excl) } |
||||
.stab.exclstr 0 : { *(.stab.exclstr) } |
||||
.stab.index 0 : { *(.stab.index) } |
||||
.stab.indexstr 0 : { *(.stab.indexstr) } |
||||
.comment 0 : { *(.comment) } |
||||
|
||||
} |
||||
@ -1,142 +0,0 @@ |
||||
/* |
||||
* Linker script for Gaisler Research AB's GRSIM LEON2 simulator. |
||||
* |
||||
* (C) Copyright 2007 |
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
||||
OUTPUT_ARCH(sparc) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
|
||||
.text : { |
||||
_load_addr = .; |
||||
_text = .; |
||||
|
||||
*(.start) |
||||
arch/sparc/cpu/leon2/start.o (.text) |
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ |
||||
. = ALIGN(8192); |
||||
/* PROM CODE, Will be relocated to the end of memory, |
||||
* no global data accesses please. |
||||
*/ |
||||
__prom_start = .; |
||||
*(.prom.pgt) |
||||
*(.prom.data) |
||||
*(.prom.text) |
||||
. = ALIGN(16); |
||||
__prom_end = .; |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.gnu.warning) |
||||
/* *(.got1)*/ |
||||
. = ALIGN(16); |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
. = ALIGN(4); |
||||
_etext = .; |
||||
|
||||
/* CMD Table */ |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.data.rel) |
||||
*(.data.rel.*) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = ALIGN(4); |
||||
__got_start = .; |
||||
.got : { |
||||
*(.got) |
||||
/* *(.data.rel) |
||||
*(.data.rel.local)*/ |
||||
. = ALIGN(16); |
||||
} |
||||
__got_end = .; |
||||
|
||||
/* .data.rel : { } */ |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(16); /* to speed clearing of bss up */ |
||||
} |
||||
__bss_end = . ; |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
/* Relocated into main memory */ |
||||
|
||||
/* Start of main memory */ |
||||
/*. = 0x40000000;*/ |
||||
|
||||
.stack (NOLOAD) : { *(.stack) } |
||||
|
||||
/* PROM CODE */ |
||||
|
||||
/* global data in RAM passed to kernel after booting */ |
||||
|
||||
.stab 0 : { *(.stab) } |
||||
.stabstr 0 : { *(.stabstr) } |
||||
.stab.excl 0 : { *(.stab.excl) } |
||||
.stab.exclstr 0 : { *(.stab.exclstr) } |
||||
.stab.index 0 : { *(.stab.index) } |
||||
.stab.indexstr 0 : { *(.stab.indexstr) } |
||||
.comment 0 : { *(.comment) } |
||||
|
||||
} |
||||
@ -0,0 +1,9 @@ |
||||
#
|
||||
# board/renesas/alt/Makefile
|
||||
#
|
||||
# Copyright (C) 2014 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
obj-y := alt.o qos.o
|
||||
@ -0,0 +1,173 @@ |
||||
/*
|
||||
* board/renesas/alt/alt.c |
||||
* |
||||
* Copyright (C) 2014 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mach-types.h> |
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/arch/rmobile.h> |
||||
#include <netdev.h> |
||||
#include <miiphy.h> |
||||
#include <i2c.h> |
||||
#include <div64.h> |
||||
#include "qos.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define CLK2MHZ(clk) (clk / 1000 / 1000) |
||||
void s_init(void) |
||||
{ |
||||
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
||||
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
||||
|
||||
/* Watchdog init */ |
||||
writel(0xA5A5A500, &rwdt->rwtcsra); |
||||
writel(0xA5A5A500, &swdt->swtcsra); |
||||
|
||||
/* QoS */ |
||||
qos_init(); |
||||
} |
||||
|
||||
#define MSTPSR1 0xE6150038 |
||||
#define SMSTPCR1 0xE6150134 |
||||
#define TMU0_MSTP125 (1 << 25) |
||||
|
||||
#define MSTPSR7 0xE61501C4 |
||||
#define SMSTPCR7 0xE615014C |
||||
#define SCIF0_MSTP719 (1 << 19) |
||||
|
||||
#define MSTPSR8 0xE61509A0 |
||||
#define SMSTPCR8 0xE6150990 |
||||
#define ETHER_MSTP813 (1 << 13) |
||||
|
||||
#define mstp_setbits(type, addr, saddr, set) \ |
||||
out_##type((saddr), in_##type(addr) | (set)) |
||||
#define mstp_clrbits(type, addr, saddr, clear) \ |
||||
out_##type((saddr), in_##type(addr) & ~(clear)) |
||||
#define mstp_setbits_le32(addr, saddr, set) \ |
||||
mstp_setbits(le32, addr, saddr, set) |
||||
#define mstp_clrbits_le32(addr, saddr, clear) \ |
||||
mstp_clrbits(le32, addr, saddr, clear) |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/* TMU */ |
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
||||
|
||||
/* SCIF0 */ |
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719); |
||||
|
||||
/* ETHER */ |
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void arch_preboot_os(void) |
||||
{ |
||||
/* Disable TMU0 */ |
||||
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100; |
||||
|
||||
/* Init PFC controller */ |
||||
r8a7794_pinmux_init(); |
||||
|
||||
/* Ether Enable */ |
||||
gpio_request(GPIO_FN_ETH_CRS_DV, NULL); |
||||
gpio_request(GPIO_FN_ETH_RX_ER, NULL); |
||||
gpio_request(GPIO_FN_ETH_RXD0, NULL); |
||||
gpio_request(GPIO_FN_ETH_RXD1, NULL); |
||||
gpio_request(GPIO_FN_ETH_LINK, NULL); |
||||
gpio_request(GPIO_FN_ETH_REFCLK, NULL); |
||||
gpio_request(GPIO_FN_ETH_MDIO, NULL); |
||||
gpio_request(GPIO_FN_ETH_TXD1, NULL); |
||||
gpio_request(GPIO_FN_ETH_TX_EN, NULL); |
||||
gpio_request(GPIO_FN_ETH_MAGIC, NULL); |
||||
gpio_request(GPIO_FN_ETH_TXD0, NULL); |
||||
gpio_request(GPIO_FN_ETH_MDC, NULL); |
||||
gpio_request(GPIO_FN_IRQ8, NULL); |
||||
|
||||
/* PHY reset */ |
||||
gpio_request(GPIO_GP_1_24, NULL); |
||||
gpio_direction_output(GPIO_GP_1_24, 0); |
||||
mdelay(20); |
||||
gpio_set_value(GPIO_GP_1_24, 1); |
||||
udelay(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define CXR24 0xEE7003C0 /* MAC address high register */ |
||||
#define CXR25 0xEE7003C8 /* MAC address low register */ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#ifdef CONFIG_SH_ETHER |
||||
int ret = -ENODEV; |
||||
u32 val; |
||||
unsigned char enetaddr[6]; |
||||
|
||||
ret = sh_eth_initialize(bis); |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
return ret; |
||||
|
||||
/* Set Mac address */ |
||||
val = enetaddr[0] << 24 | enetaddr[1] << 16 | |
||||
enetaddr[2] << 8 | enetaddr[3]; |
||||
writel(val, CXR24); |
||||
|
||||
val = enetaddr[4] << 8 | enetaddr[5]; |
||||
writel(val, CXR25); |
||||
|
||||
return ret; |
||||
#else |
||||
return 0; |
||||
#endif |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
const struct rmobile_sysinfo sysinfo = { |
||||
CONFIG_RMOBILE_BOARD_STRING |
||||
}; |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = ALT_SDRAM_BASE; |
||||
gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
u8 val; |
||||
|
||||
i2c_set_bus_num(1); /* PowerIC connected to ch3 */ |
||||
i2c_init(400000, 0); |
||||
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
||||
val |= 0x02; |
||||
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); |
||||
} |
||||
@ -0,0 +1,944 @@ |
||||
/*
|
||||
* board/renesas/alt/qos.c |
||||
* |
||||
* Copyright (C) 2014 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mach-types.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/rmobile.h> |
||||
|
||||
/* QoS version 0.10 */ |
||||
|
||||
enum { |
||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, |
||||
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, |
||||
DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, |
||||
DBSC3_15, |
||||
DBSC3_NR, |
||||
}; |
||||
|
||||
static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { |
||||
[DBSC3_00] = DBSC3_0_QOS_R0_BASE, |
||||
[DBSC3_01] = DBSC3_0_QOS_R1_BASE, |
||||
[DBSC3_02] = DBSC3_0_QOS_R2_BASE, |
||||
[DBSC3_03] = DBSC3_0_QOS_R3_BASE, |
||||
[DBSC3_04] = DBSC3_0_QOS_R4_BASE, |
||||
[DBSC3_05] = DBSC3_0_QOS_R5_BASE, |
||||
[DBSC3_06] = DBSC3_0_QOS_R6_BASE, |
||||
[DBSC3_07] = DBSC3_0_QOS_R7_BASE, |
||||
[DBSC3_08] = DBSC3_0_QOS_R8_BASE, |
||||
[DBSC3_09] = DBSC3_0_QOS_R9_BASE, |
||||
[DBSC3_10] = DBSC3_0_QOS_R10_BASE, |
||||
[DBSC3_11] = DBSC3_0_QOS_R11_BASE, |
||||
[DBSC3_12] = DBSC3_0_QOS_R12_BASE, |
||||
[DBSC3_13] = DBSC3_0_QOS_R13_BASE, |
||||
[DBSC3_14] = DBSC3_0_QOS_R14_BASE, |
||||
[DBSC3_15] = DBSC3_0_QOS_R15_BASE, |
||||
}; |
||||
|
||||
static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { |
||||
[DBSC3_00] = DBSC3_0_QOS_W0_BASE, |
||||
[DBSC3_01] = DBSC3_0_QOS_W1_BASE, |
||||
[DBSC3_02] = DBSC3_0_QOS_W2_BASE, |
||||
[DBSC3_03] = DBSC3_0_QOS_W3_BASE, |
||||
[DBSC3_04] = DBSC3_0_QOS_W4_BASE, |
||||
[DBSC3_05] = DBSC3_0_QOS_W5_BASE, |
||||
[DBSC3_06] = DBSC3_0_QOS_W6_BASE, |
||||
[DBSC3_07] = DBSC3_0_QOS_W7_BASE, |
||||
[DBSC3_08] = DBSC3_0_QOS_W8_BASE, |
||||
[DBSC3_09] = DBSC3_0_QOS_W9_BASE, |
||||
[DBSC3_10] = DBSC3_0_QOS_W10_BASE, |
||||
[DBSC3_11] = DBSC3_0_QOS_W11_BASE, |
||||
[DBSC3_12] = DBSC3_0_QOS_W12_BASE, |
||||
[DBSC3_13] = DBSC3_0_QOS_W13_BASE, |
||||
[DBSC3_14] = DBSC3_0_QOS_W14_BASE, |
||||
[DBSC3_15] = DBSC3_0_QOS_W15_BASE, |
||||
}; |
||||
|
||||
void qos_init(void) |
||||
{ |
||||
int i; |
||||
struct rcar_s3c *s3c; |
||||
struct rcar_s3c_qos *s3c_qos; |
||||
struct rcar_dbsc3_qos *qos_addr; |
||||
struct rcar_mxi *mxi; |
||||
struct rcar_mxi_qos *mxi_qos; |
||||
struct rcar_axi_qos *axi_qos; |
||||
|
||||
/* DBSC DBADJ2 */ |
||||
writel(0x20042004, DBSC3_0_DBADJ2); |
||||
|
||||
/* S3C -QoS */ |
||||
s3c = (struct rcar_s3c *)S3C_BASE; |
||||
writel(0x1F0D0B0A, &s3c->s3crorr); |
||||
writel(0x1F0D0B09, &s3c->s3cworr); |
||||
|
||||
/* QoS Control Registers */ |
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; |
||||
writel(0x00890089, &s3c_qos->s3cqos0); |
||||
writel(0x20960010, &s3c_qos->s3cqos1); |
||||
writel(0x20302030, &s3c_qos->s3cqos2); |
||||
writel(0x20AA2200, &s3c_qos->s3cqos3); |
||||
writel(0x00002032, &s3c_qos->s3cqos4); |
||||
writel(0x20960010, &s3c_qos->s3cqos5); |
||||
writel(0x20302030, &s3c_qos->s3cqos6); |
||||
writel(0x20AA2200, &s3c_qos->s3cqos7); |
||||
writel(0x00002032, &s3c_qos->s3cqos8); |
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; |
||||
writel(0x00890089, &s3c_qos->s3cqos0); |
||||
writel(0x20960010, &s3c_qos->s3cqos1); |
||||
writel(0x20302030, &s3c_qos->s3cqos2); |
||||
writel(0x20AA2200, &s3c_qos->s3cqos3); |
||||
writel(0x00002032, &s3c_qos->s3cqos4); |
||||
writel(0x20960010, &s3c_qos->s3cqos5); |
||||
writel(0x20302030, &s3c_qos->s3cqos6); |
||||
writel(0x20AA2200, &s3c_qos->s3cqos7); |
||||
writel(0x00002032, &s3c_qos->s3cqos8); |
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; |
||||
writel(0x80928092, &s3c_qos->s3cqos0); |
||||
writel(0x20960020, &s3c_qos->s3cqos1); |
||||
writel(0x20302030, &s3c_qos->s3cqos2); |
||||
writel(0x20AA20DC, &s3c_qos->s3cqos3); |
||||
writel(0x00002032, &s3c_qos->s3cqos4); |
||||
writel(0x20960020, &s3c_qos->s3cqos5); |
||||
writel(0x20302030, &s3c_qos->s3cqos6); |
||||
writel(0x20AA20DC, &s3c_qos->s3cqos7); |
||||
writel(0x00002032, &s3c_qos->s3cqos8); |
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; |
||||
writel(0x00820082, &s3c_qos->s3cqos0); |
||||
writel(0x20960020, &s3c_qos->s3cqos1); |
||||
writel(0x20302030, &s3c_qos->s3cqos2); |
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3); |
||||
writel(0x00002032, &s3c_qos->s3cqos4); |
||||
writel(0x20960020, &s3c_qos->s3cqos5); |
||||
writel(0x20302030, &s3c_qos->s3cqos6); |
||||
writel(0x20AA20FA, &s3c_qos->s3cqos7); |
||||
writel(0x00002032, &s3c_qos->s3cqos8); |
||||
|
||||
/* DBSC -QoS */ |
||||
/* DBSC0 - Read */ |
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) { |
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; |
||||
writel(0x00000002, &qos_addr->dblgcnt); |
||||
writel(0x0000207D, &qos_addr->dbtmval0); |
||||
writel(0x00002053, &qos_addr->dbtmval1); |
||||
writel(0x0000202A, &qos_addr->dbtmval2); |
||||
writel(0x00001FBD, &qos_addr->dbtmval3); |
||||
writel(0x00000001, &qos_addr->dbrqctr); |
||||
writel(0x00002064, &qos_addr->dbthres0); |
||||
writel(0x0000203E, &qos_addr->dbthres1); |
||||
writel(0x00002019, &qos_addr->dbthres2); |
||||
writel(0x00000001, &qos_addr->dblgqon); |
||||
} |
||||
|
||||
/* DBSC0 - Write */ |
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) { |
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; |
||||
writel(0x00000002, &qos_addr->dblgcnt); |
||||
writel(0x0000207D, &qos_addr->dbtmval0); |
||||
writel(0x00002053, &qos_addr->dbtmval1); |
||||
writel(0x00002043, &qos_addr->dbtmval2); |
||||
writel(0x00002030, &qos_addr->dbtmval3); |
||||
writel(0x00000001, &qos_addr->dbrqctr); |
||||
writel(0x00002064, &qos_addr->dbthres0); |
||||
writel(0x0000203E, &qos_addr->dbthres1); |
||||
writel(0x00002031, &qos_addr->dbthres2); |
||||
writel(0x00000001, &qos_addr->dblgqon); |
||||
} |
||||
|
||||
/* CCI-400 -QoS */ |
||||
writel(0x20001000, CCI_400_MAXOT_1); |
||||
writel(0x20001000, CCI_400_MAXOT_2); |
||||
writel(0x0000000C, CCI_400_QOSCNTL_1); |
||||
writel(0x0000000C, CCI_400_QOSCNTL_2); |
||||
|
||||
/* MXI -QoS */ |
||||
/* Transaction Control (MXI) */ |
||||
mxi = (struct rcar_mxi *)MXI_BASE; |
||||
writel(0x00000013, &mxi->mxrtcr); |
||||
writel(0x00000013, &mxi->mxwtcr); |
||||
writel(0x00780080, &mxi->mxsaar0); |
||||
writel(0x02000800, &mxi->mxsaar1); |
||||
|
||||
/* QoS Control (MXI) */ |
||||
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; |
||||
writel(0x0000000C, &mxi_qos->vspdu0); |
||||
writel(0x0000000E, &mxi_qos->du0); |
||||
|
||||
/* AXI -QoS */ |
||||
/* Transaction Control (MXI) */ |
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x000020A6, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x0000214C, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x000020A6, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x000020A6, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002029, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x000020A6, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x0000214C, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x0000214C, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x000020A6, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
/* QoS Register (RT-AXI) */ |
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
/* QoS Register (MP-AXI) */ |
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002037, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002014, &axi_qos->qosctset0); |
||||
writel(0x00000040, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002014, &axi_qos->qosctset0); |
||||
writel(0x00000040, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00001FF0, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00002001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x00002053, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; |
||||
writel(0x00000000, &axi_qos->qosconf); |
||||
writel(0x0000206E, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
/* QoS Register (SYS-AXI256) */ |
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020EB, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020EB, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020EB, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020EB, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
/* QoS Register (CCI-AXI) */ |
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x00002245, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002004, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000000, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
/* QoS Register (Media-AXI) */ |
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020DC, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x000020AA, &axi_qos->qosthres0); |
||||
writel(0x00002032, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; |
||||
writel(0x00000002, &axi_qos->qosconf); |
||||
writel(0x000020DC, &axi_qos->qosctset0); |
||||
writel(0x00002096, &axi_qos->qosctset1); |
||||
writel(0x00002030, &axi_qos->qosctset2); |
||||
writel(0x00002030, &axi_qos->qosctset3); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x000020AA, &axi_qos->qosthres0); |
||||
writel(0x00002032, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002190, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00001FF0, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00002001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; |
||||
writel(0x00000003, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; |
||||
writel(0x00000003, &axi_qos->qosconf); |
||||
writel(0x000020C8, &axi_qos->qosctset0); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; |
||||
writel(0x00000003, &axi_qos->qosconf); |
||||
writel(0x00002063, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; |
||||
writel(0x00000003, &axi_qos->qosconf); |
||||
writel(0x00002063, &axi_qos->qosctset0); |
||||
writel(0x00000001, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002073, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002073, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002073, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002073, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00000001, &axi_qos->qosthres0); |
||||
writel(0x00000001, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; |
||||
writel(0x00000001, &axi_qos->qosconf); |
||||
writel(0x00002073, &axi_qos->qosctset0); |
||||
writel(0x00000020, &axi_qos->qosreqctr); |
||||
writel(0x00002064, &axi_qos->qosthres0); |
||||
writel(0x00002004, &axi_qos->qosthres1); |
||||
writel(0x00000001, &axi_qos->qosthres2); |
||||
writel(0x00000001, &axi_qos->qosqon); |
||||
} |
||||
@ -0,0 +1,12 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __QOS_H__ |
||||
#define __QOS_H__ |
||||
|
||||
void qos_init(void); |
||||
|
||||
#endif |
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue