- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>master
Dave Liu
15 years ago
committed by
Kumar Gala
parent
6a81978367
commit
c360ceac02
@ -0,0 +1,314 @@ |
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/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* calculate the organization and timing parameter |
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* from ddr3 spd, please refer to the spec |
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* JEDEC standard No.21-C 4_01_02_11R18.pdf |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include "ddr.h" |
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/*
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* Calculate the Density of each Physical Rank. |
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* Returned size is in bytes. |
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* |
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* each rank size = |
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* sdram capacity(bit) / 8 * primary bus width / sdram width |
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* |
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* where: sdram capacity = spd byte4[3:0] |
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* primary bus width = spd byte8[2:0] |
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* sdram width = spd byte7[2:0] |
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* |
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* SPD byte4 - sdram density and banks |
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* bit[3:0] size(bit) size(byte) |
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* 0000 256Mb 32MB |
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* 0001 512Mb 64MB |
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* 0010 1Gb 128MB |
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* 0011 2Gb 256MB |
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* 0100 4Gb 512MB |
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* 0101 8Gb 1GB |
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* 0110 16Gb 2GB |
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* |
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* SPD byte8 - module memory bus width |
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* bit[2:0] primary bus width |
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* 000 8bits |
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* 001 16bits |
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* 010 32bits |
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* 011 64bits |
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* |
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* SPD byte7 - module organiztion |
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* bit[2:0] sdram device width |
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* 000 4bits |
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* 001 8bits |
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* 010 16bits |
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* 011 32bits |
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* |
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*/ |
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static phys_size_t |
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compute_ranksize(const ddr3_spd_eeprom_t *spd) |
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{ |
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phys_size_t bsize; |
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int nbit_sdram_cap_bsize = 0; |
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int nbit_primary_bus_width = 0; |
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int nbit_sdram_width = 0; |
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if ((spd->density_banks & 0xf) < 7) |
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nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; |
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if ((spd->bus_width & 0x7) < 4) |
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nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; |
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if ((spd->organization & 0x7) < 4) |
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nbit_sdram_width = (spd->organization & 0x7) + 2; |
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bsize = 1 << (nbit_sdram_cap_bsize - 3 |
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+ nbit_primary_bus_width - nbit_sdram_width); |
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debug("DDR: DDR III rank density = 0x%08x\n", bsize); |
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return bsize; |
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} |
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|
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/*
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* ddr_compute_dimm_parameters for DDR3 SPD |
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* |
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* Compute DIMM parameters based upon the SPD information in spd. |
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* Writes the results to the dimm_params_t structure pointed by pdimm. |
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* |
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*/ |
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unsigned int |
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ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, |
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dimm_params_t *pdimm, |
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unsigned int dimm_number) |
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{ |
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unsigned int retval; |
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unsigned int mtb_ps; |
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if (spd->mem_type) { |
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if (spd->mem_type != SPD_MEMTYPE_DDR3) { |
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printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); |
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return 1; |
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} |
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} else { |
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memset(pdimm, 0, sizeof(dimm_params_t)); |
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return 1; |
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} |
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retval = ddr3_spd_check(spd); |
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if (retval) { |
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printf("DIMM %u: failed checksum\n", dimm_number); |
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return 2; |
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} |
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/*
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* The part name in ASCII in the SPD EEPROM is not null terminated. |
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* Guarantee null termination here by presetting all bytes to 0 |
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* and copying the part name in ASCII from the SPD onto it |
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*/ |
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
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memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); |
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|
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/* DIMM organization parameters */ |
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pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; |
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pdimm->rank_density = compute_ranksize(spd); |
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pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; |
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pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); |
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if ((spd->bus_width >> 3) & 0x3) |
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pdimm->ec_sdram_width = 8; |
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else |
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pdimm->ec_sdram_width = 0; |
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pdimm->data_width = pdimm->primary_sdram_width |
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+ pdimm->ec_sdram_width; |
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switch (spd->module_type & 0xf) { |
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case 0x01: /* RDIMM */ |
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case 0x05: /* Mini-RDIMM */ |
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pdimm->registered_dimm = 1; /* register buffered */ |
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break; |
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case 0x02: /* UDIMM */ |
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case 0x03: /* SO-DIMM */ |
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case 0x04: /* Micro-DIMM */ |
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case 0x06: /* Mini-UDIMM */ |
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pdimm->registered_dimm = 0; /* unbuffered */ |
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break; |
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default: |
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printf("unknown dimm_type 0x%02X\n", spd->module_type); |
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return 1; |
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} |
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/* SDRAM device parameters */ |
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pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; |
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pdimm->n_col_addr = (spd->addressing & 0x7) + 9; |
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pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); |
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/*
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* The SPD spec has not the ECC bit, |
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* We consider the DIMM as ECC capability |
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* when the extension bus exist |
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*/ |
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if (pdimm->ec_sdram_width) |
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pdimm->edc_config = 0x02; |
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else |
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pdimm->edc_config = 0x00; |
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/*
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* The SPD spec has not the burst length byte |
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* but DDR3 spec has nature BL8 and BC4, |
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* BL8 -bit3, BC4 -bit2 |
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*/ |
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pdimm->burst_lengths_bitmask = 0x0c; |
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pdimm->row_density = __ilog2(pdimm->rank_density); |
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/* MTB - medium timebase
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* The unit in the SPD spec is ns, |
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* We convert it to ps. |
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* eg: MTB = 0.125ns (125ps) |
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*/ |
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mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; |
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pdimm->mtb_ps = mtb_ps; |
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/*
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* sdram minimum cycle time |
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* we assume the MTB is 0.125ns |
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* eg: |
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* tCK_min=15 MTB (1.875ns) ->DDR3-1066 |
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* =12 MTB (1.5ns) ->DDR3-1333 |
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* =10 MTB (1.25ns) ->DDR3-1600 |
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*/ |
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pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps; |
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/*
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* CAS latency supported |
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* bit4 - CL4 |
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* bit5 - CL5 |
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* bit18 - CL18 |
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*/ |
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pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; |
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/*
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* min CAS latency time |
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* eg: tAA_min = |
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* DDR3-800D 100 MTB (12.5ns) |
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* DDR3-1066F 105 MTB (13.125ns) |
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* DDR3-1333H 108 MTB (13.5ns) |
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* DDR3-1600H 90 MTB (11.25ns) |
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*/ |
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pdimm->tAA_ps = spd->tAA_min * mtb_ps; |
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/*
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* min write recovery time |
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* eg: |
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* tWR_min = 120 MTB (15ns) -> all speed grades. |
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*/ |
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pdimm->tWR_ps = spd->tWR_min * mtb_ps; |
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/*
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* min RAS to CAS delay time |
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* eg: tRCD_min = |
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* DDR3-800 100 MTB (12.5ns) |
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* DDR3-1066F 105 MTB (13.125ns) |
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* DDR3-1333H 108 MTB (13.5ns) |
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* DDR3-1600H 90 MTB (11.25) |
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*/ |
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pdimm->tRCD_ps = spd->tRCD_min * mtb_ps; |
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/*
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* min row active to row active delay time |
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* eg: tRRD_min = |
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* DDR3-800(1KB page) 80 MTB (10ns) |
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* DDR3-1333(1KB page) 48 MTB (6ns) |
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*/ |
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pdimm->tRRD_ps = spd->tRRD_min * mtb_ps; |
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/*
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* min row precharge delay time |
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* eg: tRP_min = |
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* DDR3-800D 100 MTB (12.5ns) |
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* DDR3-1066F 105 MTB (13.125ns) |
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* DDR3-1333H 108 MTB (13.5ns) |
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* DDR3-1600H 90 MTB (11.25ns) |
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*/ |
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pdimm->tRP_ps = spd->tRP_min * mtb_ps; |
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/* min active to precharge delay time
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* eg: tRAS_min = |
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* DDR3-800D 300 MTB (37.5ns) |
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* DDR3-1066F 300 MTB (37.5ns) |
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* DDR3-1333H 288 MTB (36ns) |
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* DDR3-1600H 280 MTB (35ns) |
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*/ |
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pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb) |
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* mtb_ps; |
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/*
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* min active to actice/refresh delay time |
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* eg: tRC_min = |
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* DDR3-800D 400 MTB (50ns) |
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* DDR3-1066F 405 MTB (50.625ns) |
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* DDR3-1333H 396 MTB (49.5ns) |
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* DDR3-1600H 370 MTB (46.25ns) |
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*/ |
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pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb) |
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* mtb_ps; |
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/*
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* min refresh recovery delay time |
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* eg: tRFC_min = |
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* 512Mb 720 MTB (90ns) |
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* 1Gb 880 MTB (110ns) |
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* 2Gb 1280 MTB (160ns) |
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*/ |
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pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb) |
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* mtb_ps; |
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/*
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* min internal write to read command delay time |
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* eg: tWTR_min = 40 MTB (7.5ns) - all speed bins. |
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* tWRT is at least 4 mclk independent of operating freq. |
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*/ |
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pdimm->tWTR_ps = spd->tWTR_min * mtb_ps; |
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/*
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* min internal read to precharge command delay time |
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* eg: tRTP_min = 40 MTB (7.5ns) - all speed bins. |
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* tRTP is at least 4 mclk independent of operating freq. |
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*/ |
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pdimm->tRTP_ps = spd->tRTP_min * mtb_ps; |
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/*
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* Average periodic refresh interval |
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* tREFI = 7.8 us at normal temperature range |
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* = 3.9 us at ext temperature range |
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*/ |
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pdimm->refresh_rate_ps = 7800000; |
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/*
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* min four active window delay time |
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* eg: tFAW_min = |
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* DDR3-800(1KB page) 320 MTB (40ns) |
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* DDR3-1066(1KB page) 300 MTB (37.5ns) |
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* DDR3-1333(1KB page) 240 MTB (30ns) |
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* DDR3-1600(1KB page) 240 MTB (30ns) |
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*/ |
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pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) |
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* mtb_ps; |
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/*
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* We need check the address mirror for unbuffered DIMM |
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* If SPD indicate the address map mirror, The DDR controller |
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* need care it. |
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*/ |
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if ((spd->module_type == SPD_MODULETYPE_UDIMM) || |
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(spd->module_type == SPD_MODULETYPE_SODIMM) || |
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(spd->module_type == SPD_MODULETYPE_MICRODIMM) || |
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(spd->module_type == SPD_MODULETYPE_MINIUDIMM)) |
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pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1; |
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return 0; |
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} |
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