Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Patch by Yuli Barcohen, 20 May 2004:

Browse Source 
Add support for Interphase iSPAN boards.
master
wdenk 21 years ago
parent f39748ae8e
commit c3c7f861ae
12 changed files with 1097 additions and 6 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 7
      CHANGELOG
  2. 1
      CREDITS
  3. 1
      MAINTAINERS
  4. 10
      MAKEALL
  5. 7
      Makefile
  6. 46
      board/ispan/Makefile
  7. 29
      board/ispan/config.mk
  8. 462
      board/ispan/ispan.c
  9. 122
      board/ispan/u-boot.lds
  10. 71
      drivers/smc91111.c
  11. 3
      drivers/smc91111.h
  12. 344
      include/configs/ISPAN.h

7
CHANGELOG
Unescape View File

@ -2,7 +2,12 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Paul Ruhland, 17 May 2004:
* Patch by Yuli Barcohen, 20 May 2004:
Add support for Interphase iSPAN boards.
* Patches by Paul Ruhland, 17 May 2004:
- Add I/O functions to the smc91111 ethernet driver to support the
Logic LPD7A40x boards.
- Add support for the Logic Zoom LH7A40x based SDK board(s),
specifically the LPD7A400.

1
CREDITS
Unescape View File

@ -38,6 +38,7 @@ N: Yuli Barcohen
E: yuli@arabellasw.com
D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
D: Support for Zephyr Engineering ZPC.1900 board.
D: Support for Interphase iSPAN boards.
W: http://www.arabellasw.com
N: Jerry van Baren

1
MAINTAINERS
Unescape View File

@ -27,6 +27,7 @@ Pantelis Antoniou <panto@intracom.gr>
Yuli Barcohen <yuli@arabellasw.com>
ISPAN MPC8260
MPC8260ADS MPC826x/MPC827x/MPC8280
ZPC1900 MPC8265

10
MAKEALL
Unescape View File

@ -86,11 +86,11 @@ LIST_824x=" \
LIST_8260=" \
atc cogent_mpc8260 CPU86 ep8260 \
gw8260 hymod IPHASE4539 MPC8260ADS \
MPC8266ADS MPC8272ADS PM826 PM828 \
ppmc8260 PQ2FADS RPXsuper rsdproto \
sacsng sbc8260 SCM TQM8260_AC \
TQM8260_AD TQM8260_AE ZPC1900 \
gw8260 hymod IPHASE4539 ISPAN \
MPC8260ADS MPC8266ADS MPC8272ADS PM826 \
PM828 ppmc8260 PQ2FADS RPXsuper \
rsdproto sacsng sbc8260 SCM \
TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
"
#########################################################################

7
Makefile
Unescape View File

@ -789,6 +789,13 @@ hymod_config: unconfig
IPHASE4539_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
ISPAN_config \
ISPAN_REVB_config: unconfig
@if [ "$(findstring _REVB_,$@)" ] ; then \
echo "#define CFG_REV_B" > include/config.h ; \
fi
@./mkconfig -a ISPAN ppc mpc8260 ispan
MPC8260ADS_config \
MPC8260ADS_33MHz_config \
MPC8260ADS_40MHz_config \

46
board/ispan/Makefile
Unescape View File

@ -0,0 +1,46 @@
#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

29
board/ispan/config.mk
Unescape View File

@ -0,0 +1,29 @@
#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Interphase iSPAN Communications Controllers
#
#TEXT_BASE = 0xFF800000
#TEXT_BASE = 0xFFBA0000
TEXT_BASE = 0xFE7A0000

462
board/ispan/ispan.c
Unescape View File

@ -0,0 +1,462 @@
/*
* Copyright (C) 2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Interphase iSPAN Communications Controllers
* (453x and others). Tested on 4532.
*
* Derived from iSPAN 4539 port (iphase4539) by
* Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <asm/io.h>
/*
* I/O Ports configuration table
*
* If conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
/* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
/* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
},
/* Port B */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
/* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
/* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
/* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
/* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
/* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
/* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
/* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
/* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
/* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
/* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
/* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
/* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
/* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
/* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
/* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
/* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
/* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
/* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
/* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
#define PSPAN_ADDR 0xF0020000
#define EEPROM_REG 0x408
#define EEPROM_READ_CMD 0xA000
#define PSPAN_WRITE(a,v) \
*((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
#define PSPAN_READ(a) \
*((volatile unsigned long *)(PSPAN_ADDR+(a)))
static int seeprom_read (int addr, uchar * data, int size)
{
ulong val, cmd;
int i;
for (i = 0; i < size; i++) {
cmd = EEPROM_READ_CMD;
cmd |= ((addr + i) << 24) & 0xff000000;
/* Wait for ACT to authorize write */
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
eieio ();
/* Write command */
PSPAN_WRITE (EEPROM_REG, cmd);
/* Wait for data to be valid */
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
eieio ();
/* Do it twice, first read might be erratic */
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
eieio ();
/* Read error */
if (val & 0x00000040) {
return -1;
} else {
data[i] = (val >> 16) & 0xff;
}
}
return 0;
}
/***************************************************************
* We take some basic Hardware Configuration Parameter from the
* Serial EEPROM conected to the PSpan bridge. We keep it as
* simple as possible.
*/
static int hwc_flash_size (void)
{
uchar byte;
if (!seeprom_read (0x40, &byte, sizeof (byte))) {
switch ((byte >> 2) & 0x3) {
case 0x1:
return 0x0400000;
break;
case 0x2:
return 0x0800000;
break;
case 0x3:
return 0x1000000;
default:
return 0x0100000;
}
}
return -1;
}
static int hwc_local_sdram_size (void)
{
uchar byte;
if (!seeprom_read (0x40, &byte, sizeof (byte))) {
switch ((byte & 0x03)) {
case 0x1:
return 0x0800000;
case 0x2:
return 0x1000000;
default:
return 0; /* not present */
}
}
return -1;
}
static int hwc_main_sdram_size (void)
{
uchar byte;
if (!seeprom_read (0x41, &byte, sizeof (byte))) {
return 0x1000000 << ((byte >> 5) & 0x7);
}
return -1;
}
static int hwc_serial_number (void)
{
int sn = -1;
if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
sn = cpu_to_le32 (sn);
}
return sn;
}
static int hwc_mac_address (char *str)
{
char mac[6];
if (!seeprom_read (0xb0, mac, sizeof (mac))) {
sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
} else {
strcpy (str, "ERROR");
return -1;
}
return 0;
}
static int hwc_manufact_date (char *str)
{
uchar byte;
int value;
if (seeprom_read (0x92, &byte, sizeof (byte)))
goto out;
value = byte;
if (seeprom_read (0x93, &byte, sizeof (byte)))
goto out;
value += byte << 8;
sprintf (str, "%02d/%02d/%04d",
value & 0x1F, (value >> 5) & 0xF,
1980 + ((value >> 9) & 0x1FF));
return 0;
out:
strcpy (str, "ERROR");
return -1;
}
static int hwc_board_type (char **str)
{
ushort id = 0;
if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
switch (id) {
case 0x9080:
*str = "4532-002";
break;
case 0x9081:
*str = "4532-001";
break;
case 0x9082:
*str = "4532-000";
break;
default:
*str = "Unknown";
}
} else {
*str = "Unknown";
}
return id;
}
long int initdram (int board_type)
{
long maxsize = hwc_main_sdram_size();
#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *base;
int i;
immap->im_siu_conf.sc_ppc_acr = 0x00000026;
immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
immap->im_siu_conf.sc_lcl_acr = 0x00000000;
immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
immap->im_siu_conf.sc_tescr1 = 0x00004000;
immap->im_siu_conf.sc_ltescr1 = 0x00004000;
memctl->memc_mptpr = CFG_MPTPR;
/* Initialise 60x bus SDRAM */
base = (uchar *)(CFG_SDRAM_BASE | 0x110);
memctl->memc_psrt = CFG_PSRT;
memctl->memc_or1 = CFG_60x_OR;
memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR;
memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
*base = 0xFF;
memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
for (i = 0; i < 8; i++)
*base = 0xFF;
memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
*base = 0xFF;
memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
/* Initialise local bus SDRAM */
base = (uchar *)CFG_LSDRAM_BASE;
memctl->memc_lsrt = CFG_LSRT;
memctl->memc_or2 = CFG_LOC_OR;
memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR;
memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
*base = 0xFF;
memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
for (i = 0; i < 8; i++)
*base = 0xFF;
memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
*base = 0xFF;
memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
memctl->memc_or1 |= ~(maxsize - 1);
if (maxsize != hwc_main_sdram_size())
puts("Oops: memory test has not found all memory!\n");
#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
/* Return total RAM size (size of 60x SDRAM) */
return maxsize;
}
int checkboard(void)
{
char string[32], *id;
hwc_manufact_date(string);
hwc_board_type(&id);
printf("Board: Interphase iSPAN %s (#%d %s)\n",
id, hwc_serial_number(), string);
#ifdef DEBUG
printf("Manufacturing date: %s\n", string);
printf("Serial number : %d\n", hwc_serial_number());
printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
hwc_mac_address(string);
printf("MAC address : %s\n", string);
#endif
return 0;
}
int misc_init_r(void)
{
char *s, str[32];
int num;
if ((s = getenv("serial#")) == NULL &&
(num = hwc_serial_number()) != -1) {
sprintf(str, "%06d", num);
setenv("serial#", str);
}
if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
setenv("ethaddr", str);
}
return 0;
}

122
board/ispan/u-boot.lds
Unescape View File

@ -0,0 +1,122 @@
/*
* (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified by Yuli Barcohen <yuli@arabellasw.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8260/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

71
drivers/smc91111.c
Unescape View File

@ -220,6 +220,77 @@ int get_rom_mac(char *v_rom_mac);
------------------------------------------------------------
*/
#ifdef CONFIG_SMC_USE_IOFUNCS
/*
* input and output functions
*
* Implemented due to inx,outx macros accessing the device improperly
* and putting the device into an unkown state.
*
* For instance, on Sharp LPD7A400 SDK, affects were chip memory
* could not be free'd (hence the alloc failures), duplicate packets,
* packets being corrupt (shifted) on the wire, etc. Switching to the
* inx,outx functions fixed this problem.
*/
static inline word SMC_inw(dword offset);
static inline void SMC_outw(word value, dword offset);
static inline byte SMC_inb(dword offset);
static inline void SMC_outb(byte value, dword offset);
static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
static inline void SMC_outsw(dword offset, uchar* buf, dword len);
#define barrier() __asm__ __volatile__("": : :"memory")
static inline word SMC_inw(dword offset)
{
word v;
v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
barrier(); *(volatile u32*)(0xc0000000);
return v;
}
static inline void SMC_outw(word value, dword offset)
{
*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
barrier(); *(volatile u32*)(0xc0000000);
}
static inline byte SMC_inb(dword offset)
{
word _w;
_w = SMC_inw(offset & ~((dword)1));
return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
}
static inline void SMC_outb(byte value, dword offset)
{
word _w;
_w = SMC_inw(offset & ~((dword)1));
if (offset & 1)
*((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
else
*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
}
static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
{
while (len-- > 0) {
*((word*)buf)++ = SMC_inw(offset);
barrier(); *((volatile u32*)(0xc0000000));
}
}
static inline void SMC_outsw(dword offset, uchar* buf, dword len)
{
while (len-- > 0) {
SMC_outw(*((word*)buf)++, offset);
barrier(); *(volatile u32*)(0xc0000000);
}
}
#endif /* CONFIG_SMC_USE_IOFUNCS */
static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
/*

3
drivers/smc91111.h
Unescape View File

@ -139,6 +139,7 @@ typedef unsigned long int dword;
#else /* if not CONFIG_PXA250 */
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
/*
* We have only 16 Bit PCMCIA access on Socket 0
*/
@ -186,6 +187,8 @@ typedef unsigned long int dword;
})
#endif
#endif /* CONFIG_SMC_USE_IOFUNCS */
#if defined(CONFIG_SMC_USE_32_BIT)
#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))

344
include/configs/ISPAN.h
Unescape View File

@ -0,0 +1,344 @@
/*
* Copyright (C) 2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Interphase iSPAN Communications Controllers
* (453x and others). Tested on 4532.
*
* Derived from iSPAN 4539 port (iphase4539) by
* Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
/*-----------------------------------------------------------------------
* Select serial console configuration
*
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*
* If CONFIG_CONS_NONE is defined, then the serial console routines must be
* defined elsewhere (for example, on the cogent platform, there are serial
* ports on the motherboard which are used for the serial console - see
* cogent/cma101/serial.[ch]).
*/
#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
#undef CONFIG_CONS_NONE /* Define if console on something else */
#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
/*-----------------------------------------------------------------------
* Select Ethernet configuration
*
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
* for FCC).
*
* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
* be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
#ifdef CONFIG_ETHER_ON_FCC
#if CONFIG_ETHER_INDEX == 3
#define CFG_PHY_ADDR 0
#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#endif /* CONFIG_ETHER_INDEX == 3 */
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#define CONFIG_MII /* MII PHY management */
#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
/*
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 3 /* Port D */
#define CFG_MDIO_PIN 0x00040000 /* PD13 */
#define CFG_MDC_PIN 0x00080000 /* PD12 */
#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
else iop->pdat &= ~CFG_MDIO_PIN
#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
else iop->pdat &= ~CFG_MDC_PIN
#define MIIDELAY udelay(1)
#endif /* CONFIG_ETHER_ON_FCC */
#define CONFIG_8260_CLKIN 65536000 /* in Hz */
#define CONFIG_BAUDRATE 38400
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DHCP \
| CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
| CFG_CMD_REGINFO \
)
/* This must be included AFTER the definition of CONFIG_COMMANDS */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* #undef to save memory */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
#define CFG_LOAD_ADDR 0x100000 /* Default load address */
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_RESET_ADDRESS 0x09900000
#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
/*-----------------------------------------------------------------------
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#else
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
#endif /* CONFIG_BZIP2 */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */
#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
/* Environment is in flash, there is little space left in Serial EEPROM */
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*
* If you change bits in the HRCW, you must also change the CFG_*
* defines for the various registers affected by the HRCW e.g. changing
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
/* 0x1686B245 */
#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
HRCW_L2CPC10 | HRCW_ISB110 |\
HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
HRCW_CS10PC01 | HRCW_MODCK_H0101 \
)
/* No slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xF0F00000
#ifdef CFG_REV_B
#define CFG_DEFAULT_IMMR 0xFF000000
#endif /* CFG_REV_B */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control.
*
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
*-----------------------------------------------------------------------
* turn on Checkstop Reset Enable
*/
#define CFG_RMR RMR_CSRE
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
#define CFG_BCR 0xA01C0000
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR 0x42250000/* 0x4205C000 */
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 4-35
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#if defined (CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*-----------------------------------------------------------------------
*/
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
* Ensure DFBRG is Divide by 16
*/
#define CFG_SCCR SCCR_DFBRG01
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CFG_RCCR 0
/*-----------------------------------------------------------------------
* Init Memory Controller:
*
* Bank Bus Machine PortSize Device
* ---- --- ------- ----------------------------- ------
* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
* 1 60x SDRAM 64 bit SDRAM
* 2 Local SDRAM 32 bit SDRAM
*/
#define CFG_USE_FIRMWARE /* If defined - do not initialise memory
controller, rely on initialisation
performed by the Interphase boot firmware.
*/
#define CFG_OR0_PRELIM 0xFE000882
#ifdef CFG_REV_B
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V)
#else /* Rev. D */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
#endif /* CFG_REV_B */
#define CFG_MPTPR 0x7F00
/* Please note that 60x SDRAM MUST start at 0 */
#define CFG_SDRAM_BASE 0x00000000
#define CFG_60x_BR 0x00000041
#define CFG_60x_OR 0xF0002CD0
#define CFG_PSDMR 0x0049929A
#define CFG_PSRT 0x07
#define CFG_LSDRAM_BASE 0xF7000000
#define CFG_LOC_BR 0x00001861
#define CFG_LOC_OR 0xFF803280
#define CFG_LSDMR 0x8285A552
#define CFG_LSRT 0x07
#endif /* __CONFIG_H */
Write Preview
Loading…
Cancel
Save