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@ -93,6 +93,21 @@ static int mxs_dma_read_semaphore(int channel) |
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return tmp; |
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} |
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#ifndef CONFIG_SYS_DCACHE_OFF |
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void mxs_dma_flush_desc(struct mxs_dma_desc *desc) |
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{ |
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uint32_t addr; |
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uint32_t size; |
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addr = (uint32_t)desc; |
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size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); |
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flush_dcache_range(addr, addr + size); |
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} |
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#else |
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inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {} |
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#endif |
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/*
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* Enable a DMA channel. |
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* |
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@ -329,8 +344,10 @@ static int mxs_dma_release(int channel) |
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struct mxs_dma_desc *mxs_dma_desc_alloc(void) |
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{ |
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struct mxs_dma_desc *pdesc; |
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uint32_t size; |
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pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc)); |
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size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); |
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pdesc = memalign(MXS_DMA_ALIGNMENT, size); |
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if (pdesc == NULL) |
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return NULL; |
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@ -415,12 +432,16 @@ int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) |
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last->cmd.next = mxs_dma_cmd_address(pdesc); |
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last->cmd.data |= MXS_DMA_DESC_CHAIN; |
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mxs_dma_flush_desc(last); |
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} |
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pdesc->flags |= MXS_DMA_DESC_READY; |
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if (pdesc->flags & MXS_DMA_DESC_FIRST) |
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pchan->pending_num++; |
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list_add_tail(&pdesc->node, &pchan->active); |
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mxs_dma_flush_desc(pdesc); |
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return ret; |
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} |
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