These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
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c750b9c012
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = netphone.o flash.o phone_console.o
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/*
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size(vu_long * addr, flash_info_t * info); |
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static int write_byte(flash_info_t * info, ulong dest, uchar data); |
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static void flash_get_offsets(ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long size; |
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#if CONFIG_NETPHONE_VERSION == 2 |
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unsigned long size1; |
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#endif |
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int i; |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size, size << 20); |
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} |
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/* Remap FLASH according to real size */ |
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); |
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); |
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/* Re-do sizing to get full correct info */ |
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size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, |
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&flash_info[0]); |
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flash_protect ( FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[0]); |
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#ifdef CONFIG_ENV_ADDR_REDUND |
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flash_protect ( FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR_REDUND, |
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[0]); |
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#endif |
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flash_info[0].size = size; |
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#if CONFIG_NETPHONE_VERSION == 2 |
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size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]); |
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if (size1 > 0) { |
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if (flash_info[1].flash_id == FLASH_UNKNOWN) |
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printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); |
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/* Remap FLASH according to real size */ |
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memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); |
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memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); |
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/* Re-do sizing to get full correct info */ |
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size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]); |
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flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]); |
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size += size1; |
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} else |
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memctl->memc_br4 &= ~BR_V; |
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#endif |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets(ulong base, flash_info_t * info) |
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{ |
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int i; |
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/* set up sector start address table */ |
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000); |
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} |
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} else if (info->flash_id & FLASH_BTYPE) { |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00004000; |
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info->start[2] = base + 0x00006000; |
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info->start[3] = base + 0x00008000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000) - 0x00030000; |
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} |
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} else { |
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/* set sector offsets for top boot block type */ |
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i = info->sector_count - 1; |
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info->start[i--] = base + info->size - 0x00004000; |
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info->start[i--] = base + info->size - 0x00006000; |
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info->start[i--] = base + info->size - 0x00008000; |
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for (; i >= 0; i--) { |
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info->start[i] = base + i * 0x00010000; |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info(flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: |
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printf("AMD "); |
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break; |
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case FLASH_MAN_FUJ: |
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printf("FUJITSU "); |
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break; |
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case FLASH_MAN_MX: |
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printf("MXIC "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM040: |
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printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400B: |
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printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: |
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printf("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: |
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printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: |
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printf("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: |
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printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: |
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printf("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: |
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printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: |
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printf("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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break; |
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} |
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printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); |
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printf(" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf("\n "); |
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printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf("\n"); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size(vu_long * addr, flash_info_t * info) |
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{ |
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short i; |
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uchar mid; |
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uchar pid; |
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vu_char *caddr = (vu_char *) addr; |
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ulong base = (ulong) addr; |
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/* Write auto select command: read Manufacturer ID */ |
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caddr[0x0555] = 0xAA; |
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caddr[0x02AA] = 0x55; |
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caddr[0x0555] = 0x90; |
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mid = caddr[0]; |
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switch (mid) { |
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case (AMD_MANUFACT & 0xFF): |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case (FUJ_MANUFACT & 0xFF): |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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case (MX_MANUFACT & 0xFF): |
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info->flash_id = FLASH_MAN_MX; |
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break; |
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case (STM_MANUFACT & 0xFF): |
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info->flash_id = FLASH_MAN_STM; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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pid = caddr[1]; /* device ID */ |
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switch (pid) { |
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case (AMD_ID_LV400T & 0xFF): |
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info->flash_id += FLASH_AM400T; |
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info->sector_count = 11; |
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info->size = 0x00080000; |
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break; /* => 512 kB */ |
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case (AMD_ID_LV400B & 0xFF): |
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info->flash_id += FLASH_AM400B; |
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info->sector_count = 11; |
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info->size = 0x00080000; |
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break; /* => 512 kB */ |
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case (AMD_ID_LV800T & 0xFF): |
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info->flash_id += FLASH_AM800T; |
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info->sector_count = 19; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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case (AMD_ID_LV800B & 0xFF): |
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info->flash_id += FLASH_AM800B; |
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info->sector_count = 19; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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case (AMD_ID_LV160T & 0xFF): |
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info->flash_id += FLASH_AM160T; |
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info->sector_count = 35; |
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info->size = 0x00200000; |
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break; /* => 2 MB */ |
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case (AMD_ID_LV160B & 0xFF): |
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info->flash_id += FLASH_AM160B; |
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info->sector_count = 35; |
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info->size = 0x00200000; |
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break; /* => 2 MB */ |
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case (AMD_ID_LV040B & 0xFF): |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x00080000; |
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break; |
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case (STM_ID_M29W040B & 0xFF): |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x00080000; |
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break; |
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#if 0 /* enable when device IDs are available */
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case (AMD_ID_LV320T & 0xFF): |
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info->flash_id += FLASH_AM320T; |
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info->sector_count = 67; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case (AMD_ID_LV320B & 0xFF): |
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info->flash_id += FLASH_AM320B; |
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info->sector_count = 67; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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#endif |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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printf(" "); |
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/* set up sector start address table */ |
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000); |
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} |
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} else if (info->flash_id & FLASH_BTYPE) { |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00004000; |
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info->start[2] = base + 0x00006000; |
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info->start[3] = base + 0x00008000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000) - 0x00030000; |
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} |
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} else { |
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/* set sector offsets for top boot block type */ |
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i = info->sector_count - 1; |
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info->start[i--] = base + info->size - 0x00004000; |
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info->start[i--] = base + info->size - 0x00006000; |
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info->start[i--] = base + info->size - 0x00008000; |
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for (; i >= 0; i--) { |
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info->start[i] = base + i * 0x00010000; |
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} |
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} |
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection: D0 = 1 if protected */ |
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caddr = (volatile unsigned char *)(info->start[i]); |
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info->protect[i] = caddr[2] & 1; |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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caddr = (vu_char *) info->start[0]; |
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caddr[0x0555] = 0xAA; |
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caddr[0x02AA] = 0x55; |
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caddr[0x0555] = 0xF0; |
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udelay(20000); |
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} |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase(flash_info_t * info, int s_first, int s_last) |
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{ |
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vu_char *addr = (vu_char *) (info->start[0]); |
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int flag, prot, sect, l_sect; |
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ulong start, now, last; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf("- missing\n"); |
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} else { |
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printf("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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if ((info->flash_id == FLASH_UNKNOWN) || |
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(info->flash_id > FLASH_AMD_COMP)) { |
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printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf("- Warning: %d protected sectors will not be erased!\n", prot); |
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} else { |
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printf("\n"); |
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} |
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l_sect = -1; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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addr[0x0555] = 0xAA; |
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addr[0x02AA] = 0x55; |
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addr[0x0555] = 0x80; |
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addr[0x0555] = 0xAA; |
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addr[0x02AA] = 0x55; |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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addr = (vu_char *) (info->start[sect]); |
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addr[0] = 0x30; |
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l_sect = sect; |
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} |
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} |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay(1000); |
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/*
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* We wait for the last triggered sector |
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*/ |
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if (l_sect < 0) |
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goto DONE; |
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start = get_timer(0); |
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last = start; |
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addr = (vu_char *) (info->start[l_sect]); |
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while ((addr[0] & 0x80) != 0x80) { |
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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printf("Timeout\n"); |
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return 1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc('.'); |
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last = now; |
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} |
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} |
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DONE: |
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/* reset to read mode */ |
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addr = (vu_char *) info->start[0]; |
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addr[0] = 0xF0; /* reset bank */ |
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printf(" done\n"); |
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return 0; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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int rc; |
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while (cnt > 0) { |
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if ((rc = write_byte(info, addr++, *src++)) != 0) { |
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return (rc); |
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} |
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--cnt; |
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} |
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return (0); |
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} |
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_byte(flash_info_t * info, ulong dest, uchar data) |
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{ |
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vu_char *addr = (vu_char *) (info->start[0]); |
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ulong start; |
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int flag; |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*((vu_char *) dest) & data) != data) { |
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return (2); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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addr[0x0555] = 0xAA; |
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addr[0x02AA] = 0x55; |
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addr[0x0555] = 0xA0; |
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*((vu_char *) dest) = data; |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* data polling for D7 */ |
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start = get_timer(0); |
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while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { |
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
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return (1); |
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} |
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} |
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return (0); |
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} |
@ -1,690 +0,0 @@ |
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/*
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* (C) Copyright 2000-2004 |
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* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
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* U-Boot port on NetTA4 board |
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*/ |
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#include <common.h> |
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#include <miiphy.h> |
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#include <sed156x.h> |
||||
#include <status_led.h> |
||||
|
||||
#include "mpc8xx.h" |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
#include <watchdog.h> |
||||
#endif |
||||
|
||||
int fec8xx_miiphy_read(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short *value); |
||||
int fec8xx_miiphy_write(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short value); |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/* some sane bit macros */ |
||||
#define _BD(_b) (1U << (31-(_b))) |
||||
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) |
||||
|
||||
#define _BW(_b) (1U << (15-(_b))) |
||||
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) |
||||
|
||||
#define _BB(_b) (1U << (7-(_b))) |
||||
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) |
||||
|
||||
#define _B(_b) _BD(_b) |
||||
#define _BR(_l, _h) _BDR(_l, _h) |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Return 1 always. |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION); |
||||
return (0); |
||||
} |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define CS_0000 0x00000000 |
||||
#define CS_0001 0x10000000 |
||||
#define CS_0010 0x20000000 |
||||
#define CS_0011 0x30000000 |
||||
#define CS_0100 0x40000000 |
||||
#define CS_0101 0x50000000 |
||||
#define CS_0110 0x60000000 |
||||
#define CS_0111 0x70000000 |
||||
#define CS_1000 0x80000000 |
||||
#define CS_1001 0x90000000 |
||||
#define CS_1010 0xA0000000 |
||||
#define CS_1011 0xB0000000 |
||||
#define CS_1100 0xC0000000 |
||||
#define CS_1101 0xD0000000 |
||||
#define CS_1110 0xE0000000 |
||||
#define CS_1111 0xF0000000 |
||||
|
||||
#define BS_0000 0x00000000 |
||||
#define BS_0001 0x01000000 |
||||
#define BS_0010 0x02000000 |
||||
#define BS_0011 0x03000000 |
||||
#define BS_0100 0x04000000 |
||||
#define BS_0101 0x05000000 |
||||
#define BS_0110 0x06000000 |
||||
#define BS_0111 0x07000000 |
||||
#define BS_1000 0x08000000 |
||||
#define BS_1001 0x09000000 |
||||
#define BS_1010 0x0A000000 |
||||
#define BS_1011 0x0B000000 |
||||
#define BS_1100 0x0C000000 |
||||
#define BS_1101 0x0D000000 |
||||
#define BS_1110 0x0E000000 |
||||
#define BS_1111 0x0F000000 |
||||
|
||||
#define GPL0_AAAA 0x00000000 |
||||
#define GPL0_AAA0 0x00200000 |
||||
#define GPL0_AAA1 0x00300000 |
||||
#define GPL0_000A 0x00800000 |
||||
#define GPL0_0000 0x00A00000 |
||||
#define GPL0_0001 0x00B00000 |
||||
#define GPL0_111A 0x00C00000 |
||||
#define GPL0_1110 0x00E00000 |
||||
#define GPL0_1111 0x00F00000 |
||||
|
||||
#define GPL1_0000 0x00000000 |
||||
#define GPL1_0001 0x00040000 |
||||
#define GPL1_1110 0x00080000 |
||||
#define GPL1_1111 0x000C0000 |
||||
|
||||
#define GPL2_0000 0x00000000 |
||||
#define GPL2_0001 0x00010000 |
||||
#define GPL2_1110 0x00020000 |
||||
#define GPL2_1111 0x00030000 |
||||
|
||||
#define GPL3_0000 0x00000000 |
||||
#define GPL3_0001 0x00004000 |
||||
#define GPL3_1110 0x00008000 |
||||
#define GPL3_1111 0x0000C000 |
||||
|
||||
#define GPL4_0000 0x00000000 |
||||
#define GPL4_0001 0x00001000 |
||||
#define GPL4_1110 0x00002000 |
||||
#define GPL4_1111 0x00003000 |
||||
|
||||
#define GPL5_0000 0x00000000 |
||||
#define GPL5_0001 0x00000400 |
||||
#define GPL5_1110 0x00000800 |
||||
#define GPL5_1111 0x00000C00 |
||||
#define LOOP 0x00000080 |
||||
|
||||
#define EXEN 0x00000040 |
||||
|
||||
#define AMX_COL 0x00000000 |
||||
#define AMX_ROW 0x00000020 |
||||
#define AMX_MAR 0x00000030 |
||||
|
||||
#define NA 0x00000008 |
||||
|
||||
#define UTA 0x00000004 |
||||
|
||||
#define TODT 0x00000002 |
||||
|
||||
#define LAST 0x00000001 |
||||
|
||||
#define A10_AAAA GPL0_AAAA |
||||
#define A10_AAA0 GPL0_AAA0 |
||||
#define A10_AAA1 GPL0_AAA1 |
||||
#define A10_000A GPL0_000A |
||||
#define A10_0000 GPL0_0000 |
||||
#define A10_0001 GPL0_0001 |
||||
#define A10_111A GPL0_111A |
||||
#define A10_1110 GPL0_1110 |
||||
#define A10_1111 GPL0_1111 |
||||
|
||||
#define RAS_0000 GPL1_0000 |
||||
#define RAS_0001 GPL1_0001 |
||||
#define RAS_1110 GPL1_1110 |
||||
#define RAS_1111 GPL1_1111 |
||||
|
||||
#define CAS_0000 GPL2_0000 |
||||
#define CAS_0001 GPL2_0001 |
||||
#define CAS_1110 GPL2_1110 |
||||
#define CAS_1111 GPL2_1111 |
||||
|
||||
#define WE_0000 GPL3_0000 |
||||
#define WE_0001 GPL3_0001 |
||||
#define WE_1110 GPL3_1110 |
||||
#define WE_1111 GPL3_1111 |
||||
|
||||
/* #define CAS_LATENCY 3 */ |
||||
#define CAS_LATENCY 2 |
||||
|
||||
const uint sdram_table[0x40] = { |
||||
|
||||
#if CAS_LATENCY == 3 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
#endif |
||||
|
||||
#if CAS_LATENCY == 2 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
#endif |
||||
|
||||
/* UPT */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* EXC */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, |
||||
_NOT_USED_, |
||||
|
||||
/* REG */ |
||||
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, |
||||
}; |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 2 |
||||
static const uint nandcs_table[0x40] = { |
||||
/* RSS */ |
||||
CS_1000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1110 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111, |
||||
CS_0000 | GPL4_0001 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ |
||||
|
||||
/* RBS */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_1000 | GPL4_1111 | GPL5_1110 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0001 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111, |
||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, |
||||
|
||||
/* WBS */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* UPT */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* EXC */ |
||||
CS_0001 | LAST, |
||||
_NOT_USED_, |
||||
|
||||
/* REG */ |
||||
CS_1110 , |
||||
CS_0001 | LAST, |
||||
}; |
||||
#endif |
||||
|
||||
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ |
||||
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ |
||||
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) |
||||
|
||||
/* 8 */ |
||||
#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
void check_ram(unsigned int addr, unsigned int size) |
||||
{ |
||||
unsigned int i, j, v, vv; |
||||
volatile unsigned int *p; |
||||
unsigned int pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
pv = (unsigned int)p; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) |
||||
*p++ = pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
v = (unsigned int)p; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
p++; |
||||
} |
||||
|
||||
for (j = 0; j < 5; j++) { |
||||
switch (j) { |
||||
case 0: v = 0x00000000; break; |
||||
case 1: v = 0xffffffff; break; |
||||
case 2: v = 0x55555555; break; |
||||
case 3: v = 0xaaaaaaaa; break; |
||||
default:v = 0xdeadbeef; break; |
||||
} |
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
*p = v; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
*p = ~v; |
||||
p++; |
||||
} |
||||
} |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size; |
||||
|
||||
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh |
||||
*/ |
||||
memctl->memc_mptpr = MPTPR_PTP_DIV8; |
||||
|
||||
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ |
||||
|
||||
/*
|
||||
* Map controller bank 3 to the SDRAM bank at preliminary address. |
||||
*/ |
||||
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; |
||||
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; |
||||
|
||||
memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform SDRAM initialisation sequence */ |
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ |
||||
|
||||
udelay(10000); |
||||
|
||||
{ |
||||
u32 d1, d2; |
||||
|
||||
d1 = 0xAA55AA55; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
|
||||
d1 = 0x55AA55AA; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
} |
||||
|
||||
size = get_ram_size((long *)0, SDRAM_MAX_SIZE); |
||||
|
||||
if (size == 0) { |
||||
printf("SIZE is zero: LOOP on 0\n"); |
||||
for (;;) { |
||||
*(volatile u32 *)0 = 0; |
||||
(void)*(volatile u32 *)0; |
||||
} |
||||
} |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
void reset_phys(void) |
||||
{ |
||||
int phyno; |
||||
unsigned short v; |
||||
|
||||
udelay(10000); |
||||
/* reset the damn phys */ |
||||
mii_init(); |
||||
|
||||
for (phyno = 0; phyno < 32; ++phyno) { |
||||
fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); |
||||
if (v == 0xFFFF) |
||||
continue; |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); |
||||
udelay(10000); |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, |
||||
BMCR_RESET | BMCR_ANENABLE); |
||||
udelay(10000); |
||||
} |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* GP = general purpose, SP = special purpose (on chip peripheral) */ |
||||
|
||||
/* bits that can have a special purpose or can be configured as inputs/outputs */ |
||||
#define PA_GP_INMASK 0 |
||||
#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) |
||||
#define PA_SP_MASK 0 |
||||
#define PA_ODR_VAL 0 |
||||
#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) |
||||
#define PA_SP_DIRVAL 0 |
||||
|
||||
#define PB_GP_INMASK _B(28) |
||||
#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) |
||||
#define PB_SP_MASK (_BR(22, 25)) |
||||
#define PB_ODR_VAL 0 |
||||
#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) |
||||
#define PB_SP_DIRVAL 0 |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
#define PC_GP_INMASK _BW(12) |
||||
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) |
||||
#elif CONFIG_NETPHONE_VERSION == 2 |
||||
#define PC_GP_INMASK (_BW(13) | _BW(15)) |
||||
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) |
||||
#endif |
||||
#define PC_SP_MASK 0 |
||||
#define PC_SOVAL 0 |
||||
#define PC_INTVAL 0 |
||||
#define PC_GP_OUTVAL (_BW(10) | _BW(11)) |
||||
#define PC_SP_DIRVAL 0 |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
#define PE_GP_INMASK _B(31) |
||||
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) |
||||
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) |
||||
#elif CONFIG_NETPHONE_VERSION == 2 |
||||
#define PE_GP_INMASK _BR(28, 31) |
||||
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) |
||||
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) |
||||
#endif |
||||
#define PE_SP_MASK 0 |
||||
#define PE_ODR_VAL 0 |
||||
#define PE_SP_DIRVAL 0 |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile iop8xx_t *ioport = &immap->im_ioport; |
||||
volatile cpm8xx_t *cpm = &immap->im_cpm; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
/* NAND chip select */ |
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); |
||||
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); |
||||
#elif CONFIG_NETPHONE_VERSION == 2 |
||||
upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); |
||||
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); |
||||
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); |
||||
memctl->memc_mamr = 0; /* all clear */ |
||||
#endif |
||||
|
||||
/* DSP chip select */ |
||||
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); |
||||
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
memctl->memc_br4 &= ~BR_V; |
||||
#endif |
||||
memctl->memc_br5 &= ~BR_V; |
||||
memctl->memc_br6 &= ~BR_V; |
||||
memctl->memc_br7 &= ~BR_V; |
||||
|
||||
ioport->iop_padat = PA_GP_OUTVAL; |
||||
ioport->iop_paodr = PA_ODR_VAL; |
||||
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; |
||||
ioport->iop_papar = PA_SP_MASK; |
||||
|
||||
cpm->cp_pbdat = PB_GP_OUTVAL; |
||||
cpm->cp_pbodr = PB_ODR_VAL; |
||||
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; |
||||
cpm->cp_pbpar = PB_SP_MASK; |
||||
|
||||
ioport->iop_pcdat = PC_GP_OUTVAL; |
||||
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; |
||||
ioport->iop_pcso = PC_SOVAL; |
||||
ioport->iop_pcint = PC_INTVAL; |
||||
ioport->iop_pcpar = PC_SP_MASK; |
||||
|
||||
cpm->cp_pedat = PE_GP_OUTVAL; |
||||
cpm->cp_peodr = PE_ODR_VAL; |
||||
cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; |
||||
cpm->cp_pepar = PE_SP_MASK; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
|
||||
void hw_watchdog_reset(void) |
||||
{ |
||||
/* XXX add here the really funky stuff */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_SHOW_ACTIVITY |
||||
|
||||
static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ |
||||
|
||||
/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */ |
||||
void board_show_activity(ulong timestamp) |
||||
{ |
||||
if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) |
||||
--left_to_poll; |
||||
} |
||||
|
||||
extern void phone_console_do_poll(void); |
||||
|
||||
static void do_poll(void) |
||||
{ |
||||
unsigned int base; |
||||
|
||||
while (left_to_poll <= 0) { |
||||
phone_console_do_poll(); |
||||
base = left_to_poll + PHONE_CONSOLE_POLL_HZ; |
||||
do { |
||||
left_to_poll = base; |
||||
} while (base != left_to_poll); |
||||
} |
||||
} |
||||
|
||||
/* called when looping */ |
||||
void show_activity(int arg) |
||||
{ |
||||
do_poll(); |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
||||
int overwrite_console(void) |
||||
{ |
||||
/* printf("overwrite_console called\n"); */ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
extern int drv_phone_init(void); |
||||
extern int drv_phone_use_me(void); |
||||
extern int drv_phone_is_idle(void); |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return drv_phone_init(); |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
int i; |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 2 |
||||
/* assert peripheral reset */ |
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); |
||||
for (i = 0; i < 10; i++) |
||||
udelay(1000); |
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); |
||||
#endif |
||||
reset_phys(); |
||||
|
||||
/* check in order to enable the local console */ |
||||
left_to_poll = PHONE_CONSOLE_POLL_HZ; |
||||
i = CONFIG_SYS_HZ * 2; |
||||
while (i > 0) { |
||||
|
||||
if (tstc()) { |
||||
getc(); |
||||
break; |
||||
} |
||||
|
||||
do_poll(); |
||||
|
||||
if (drv_phone_use_me()) { |
||||
status_led_set(0, STATUS_LED_ON); |
||||
while (!drv_phone_is_idle()) { |
||||
do_poll(); |
||||
udelay(1000000 / CONFIG_SYS_HZ); |
||||
} |
||||
|
||||
console_assign(stdin, "phone"); |
||||
console_assign(stdout, "phone"); |
||||
console_assign(stderr, "phone"); |
||||
setenv("bootdelay", "-1"); |
||||
break; |
||||
} |
||||
|
||||
udelay(1000000 / CONFIG_SYS_HZ); |
||||
i--; |
||||
left_to_poll--; |
||||
} |
||||
left_to_poll = PHONE_CONSOLE_POLL_HZ; |
||||
|
||||
return 0; |
||||
} |
File diff suppressed because it is too large
Load Diff
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,8 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = netta.o flash.o dsp.o codec.o pcmcia.o
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,492 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info); |
||||
static int write_byte(flash_info_t * info, ulong dest, uchar data); |
||||
static void flash_get_offsets(ulong base, flash_info_t * info); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
unsigned long size; |
||||
int i; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
|
||||
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); |
||||
} |
||||
|
||||
/* Remap FLASH according to real size */ |
||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); |
||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
||||
|
||||
flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
||||
|
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, |
||||
&flash_info[0]); |
||||
|
||||
flash_protect ( FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR, |
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
|
||||
#ifdef CONFIG_ENV_ADDR_REDUND |
||||
flash_protect ( FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR_REDUND, |
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
|
||||
flash_info[0].size = size; |
||||
|
||||
return (size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets(ulong base, flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
/* set up sector start address table */ |
||||
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} |
||||
} else if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
|
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info(flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: |
||||
printf("AMD "); |
||||
break; |
||||
case FLASH_MAN_FUJ: |
||||
printf("FUJITSU "); |
||||
break; |
||||
case FLASH_MAN_MX: |
||||
printf("MXIC "); |
||||
break; |
||||
default: |
||||
printf("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM040: |
||||
printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400B: |
||||
printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400T: |
||||
printf("AM29LV400T (4 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM800B: |
||||
printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM800T: |
||||
printf("AM29LV800T (8 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM160B: |
||||
printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM160T: |
||||
printf("AM29LV160T (16 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM320B: |
||||
printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM320T: |
||||
printf("AM29LV320T (32 Mbit, top boot sector)\n"); |
||||
break; |
||||
default: |
||||
printf("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); |
||||
|
||||
printf(" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf("\n "); |
||||
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf("\n"); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info) |
||||
{ |
||||
short i; |
||||
uchar mid; |
||||
uchar pid; |
||||
vu_char *caddr = (vu_char *) addr; |
||||
ulong base = (ulong) addr; |
||||
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
caddr[0x0555] = 0xAA; |
||||
caddr[0x02AA] = 0x55; |
||||
caddr[0x0555] = 0x90; |
||||
|
||||
mid = caddr[0]; |
||||
switch (mid) { |
||||
case (AMD_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case (FUJ_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
case (MX_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_MX; |
||||
break; |
||||
case (STM_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
pid = caddr[1]; /* device ID */ |
||||
switch (pid) { |
||||
case (AMD_ID_LV400T & 0xFF): |
||||
info->flash_id += FLASH_AM400T; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 512 kB */ |
||||
|
||||
case (AMD_ID_LV400B & 0xFF): |
||||
info->flash_id += FLASH_AM400B; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 512 kB */ |
||||
|
||||
case (AMD_ID_LV800T & 0xFF): |
||||
info->flash_id += FLASH_AM800T; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (AMD_ID_LV800B & 0xFF): |
||||
info->flash_id += FLASH_AM800B; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (AMD_ID_LV160T & 0xFF): |
||||
info->flash_id += FLASH_AM160T; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (AMD_ID_LV160B & 0xFF): |
||||
info->flash_id += FLASH_AM160B; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (AMD_ID_LV040B & 0xFF): |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; |
||||
break; |
||||
|
||||
case (STM_ID_M29W040B & 0xFF): |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; |
||||
break; |
||||
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case (AMD_ID_LV320T & 0xFF): |
||||
info->flash_id += FLASH_AM320T; |
||||
info->sector_count = 67; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
|
||||
case (AMD_ID_LV320B & 0xFF): |
||||
info->flash_id += FLASH_AM320B; |
||||
info->sector_count = 67; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
#endif |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
printf(" "); |
||||
/* set up sector start address table */ |
||||
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} |
||||
} else if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection: D0 = 1 if protected */ |
||||
caddr = (volatile unsigned char *)(info->start[i]); |
||||
info->protect[i] = caddr[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
caddr = (vu_char *) info->start[0]; |
||||
|
||||
caddr[0x0555] = 0xAA; |
||||
caddr[0x02AA] = 0x55; |
||||
caddr[0x0555] = 0xF0; |
||||
|
||||
udelay(20000); |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
vu_char *addr = (vu_char *) (info->start[0]); |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf("- missing\n"); |
||||
} else { |
||||
printf("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP)) { |
||||
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf("- Warning: %d protected sectors will not be erased!\n", prot); |
||||
} else { |
||||
printf("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0x80; |
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_char *) (info->start[sect]); |
||||
addr[0] = 0x30; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay(1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer(0); |
||||
last = start; |
||||
addr = (vu_char *) (info->start[l_sect]); |
||||
while ((addr[0] & 0x80) != 0x80) { |
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
||||
printf("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (vu_char *) info->start[0]; |
||||
addr[0] = 0xF0; /* reset bank */ |
||||
|
||||
printf(" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
int rc; |
||||
|
||||
while (cnt > 0) { |
||||
if ((rc = write_byte(info, addr++, *src++)) != 0) { |
||||
return (rc); |
||||
} |
||||
--cnt; |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_byte(flash_info_t * info, ulong dest, uchar data) |
||||
{ |
||||
vu_char *addr = (vu_char *) (info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((vu_char *) dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0xA0; |
||||
|
||||
*((vu_char *) dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer(0); |
||||
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { |
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
return (0); |
||||
} |
@ -1,558 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* U-Boot port on NetTA4 board |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "mpc8xx.h" |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
#include <watchdog.h> |
||||
#endif |
||||
|
||||
int fec8xx_miiphy_read(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short *value); |
||||
int fec8xx_miiphy_write(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short value); |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/* some sane bit macros */ |
||||
#define _BD(_b) (1U << (31-(_b))) |
||||
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) |
||||
|
||||
#define _BW(_b) (1U << (15-(_b))) |
||||
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) |
||||
|
||||
#define _BB(_b) (1U << (7-(_b))) |
||||
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) |
||||
|
||||
#define _B(_b) _BD(_b) |
||||
#define _BR(_l, _h) _BDR(_l, _h) |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Return 1 always. |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf ("Intracom NETTA" |
||||
#if defined(CONFIG_NETTA_ISDN) |
||||
" with ISDN support" |
||||
#endif |
||||
#if defined(CONFIG_NETTA_6412) |
||||
" (DSP:TI6412)" |
||||
#else |
||||
" (DSP:TI6711)" |
||||
#endif |
||||
"\n" |
||||
); |
||||
return (0); |
||||
} |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define CS_0000 0x00000000 |
||||
#define CS_0001 0x10000000 |
||||
#define CS_0010 0x20000000 |
||||
#define CS_0011 0x30000000 |
||||
#define CS_0100 0x40000000 |
||||
#define CS_0101 0x50000000 |
||||
#define CS_0110 0x60000000 |
||||
#define CS_0111 0x70000000 |
||||
#define CS_1000 0x80000000 |
||||
#define CS_1001 0x90000000 |
||||
#define CS_1010 0xA0000000 |
||||
#define CS_1011 0xB0000000 |
||||
#define CS_1100 0xC0000000 |
||||
#define CS_1101 0xD0000000 |
||||
#define CS_1110 0xE0000000 |
||||
#define CS_1111 0xF0000000 |
||||
|
||||
#define BS_0000 0x00000000 |
||||
#define BS_0001 0x01000000 |
||||
#define BS_0010 0x02000000 |
||||
#define BS_0011 0x03000000 |
||||
#define BS_0100 0x04000000 |
||||
#define BS_0101 0x05000000 |
||||
#define BS_0110 0x06000000 |
||||
#define BS_0111 0x07000000 |
||||
#define BS_1000 0x08000000 |
||||
#define BS_1001 0x09000000 |
||||
#define BS_1010 0x0A000000 |
||||
#define BS_1011 0x0B000000 |
||||
#define BS_1100 0x0C000000 |
||||
#define BS_1101 0x0D000000 |
||||
#define BS_1110 0x0E000000 |
||||
#define BS_1111 0x0F000000 |
||||
|
||||
#define A10_AAAA 0x00000000 |
||||
#define A10_AAA0 0x00200000 |
||||
#define A10_AAA1 0x00300000 |
||||
#define A10_000A 0x00800000 |
||||
#define A10_0000 0x00A00000 |
||||
#define A10_0001 0x00B00000 |
||||
#define A10_111A 0x00C00000 |
||||
#define A10_1110 0x00E00000 |
||||
#define A10_1111 0x00F00000 |
||||
|
||||
#define RAS_0000 0x00000000 |
||||
#define RAS_0001 0x00040000 |
||||
#define RAS_1110 0x00080000 |
||||
#define RAS_1111 0x000C0000 |
||||
|
||||
#define CAS_0000 0x00000000 |
||||
#define CAS_0001 0x00010000 |
||||
#define CAS_1110 0x00020000 |
||||
#define CAS_1111 0x00030000 |
||||
|
||||
#define WE_0000 0x00000000 |
||||
#define WE_0001 0x00004000 |
||||
#define WE_1110 0x00008000 |
||||
#define WE_1111 0x0000C000 |
||||
|
||||
#define GPL4_0000 0x00000000 |
||||
#define GPL4_0001 0x00001000 |
||||
#define GPL4_1110 0x00002000 |
||||
#define GPL4_1111 0x00003000 |
||||
|
||||
#define GPL5_0000 0x00000000 |
||||
#define GPL5_0001 0x00000400 |
||||
#define GPL5_1110 0x00000800 |
||||
#define GPL5_1111 0x00000C00 |
||||
#define LOOP 0x00000080 |
||||
|
||||
#define EXEN 0x00000040 |
||||
|
||||
#define AMX_COL 0x00000000 |
||||
#define AMX_ROW 0x00000020 |
||||
#define AMX_MAR 0x00000030 |
||||
|
||||
#define NA 0x00000008 |
||||
|
||||
#define UTA 0x00000004 |
||||
|
||||
#define TODT 0x00000002 |
||||
|
||||
#define LAST 0x00000001 |
||||
|
||||
/* #define CAS_LATENCY 3 */ |
||||
#define CAS_LATENCY 2 |
||||
|
||||
const uint sdram_table[0x40] = { |
||||
|
||||
#if CAS_LATENCY == 3 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
#endif |
||||
|
||||
#if CAS_LATENCY == 2 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
#endif |
||||
|
||||
/* UPT */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* EXC */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, |
||||
_NOT_USED_, |
||||
|
||||
/* REG */ |
||||
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, |
||||
}; |
||||
|
||||
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ |
||||
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ |
||||
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) |
||||
|
||||
/* 8 */ |
||||
#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
void check_ram(unsigned int addr, unsigned int size) |
||||
{ |
||||
unsigned int i, j, v, vv; |
||||
volatile unsigned int *p; |
||||
unsigned int pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
pv = (unsigned int)p; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) |
||||
*p++ = pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
v = (unsigned int)p; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
p++; |
||||
} |
||||
|
||||
for (j = 0; j < 5; j++) { |
||||
switch (j) { |
||||
case 0: v = 0x00000000; break; |
||||
case 1: v = 0xffffffff; break; |
||||
case 2: v = 0x55555555; break; |
||||
case 3: v = 0xaaaaaaaa; break; |
||||
default:v = 0xdeadbeef; break; |
||||
} |
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
*p = v; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
*p = ~v; |
||||
p++; |
||||
} |
||||
} |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size; |
||||
|
||||
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh |
||||
*/ |
||||
memctl->memc_mptpr = MPTPR_PTP_DIV8; |
||||
|
||||
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ |
||||
|
||||
/*
|
||||
* Map controller bank 3 to the SDRAM bank at preliminary address. |
||||
*/ |
||||
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; |
||||
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; |
||||
|
||||
memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform SDRAM initialisation sequence */ |
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ |
||||
|
||||
udelay(10000); |
||||
|
||||
{ |
||||
u32 d1, d2; |
||||
|
||||
d1 = 0xAA55AA55; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
|
||||
d1 = 0x55AA55AA; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
} |
||||
|
||||
size = get_ram_size((long *)0, SDRAM_MAX_SIZE); |
||||
|
||||
#if 0 |
||||
printf("check 0\n"); |
||||
check_ram(( 0 << 20), (2 << 20)); |
||||
printf("check 16\n"); |
||||
check_ram((16 << 20), (2 << 20)); |
||||
printf("check 32\n"); |
||||
check_ram((32 << 20), (2 << 20)); |
||||
printf("check 48\n"); |
||||
check_ram((48 << 20), (2 << 20)); |
||||
#endif |
||||
|
||||
if (size == 0) { |
||||
printf("SIZE is zero: LOOP on 0\n"); |
||||
for (;;) { |
||||
*(volatile u32 *)0 = 0; |
||||
(void)*(volatile u32 *)0; |
||||
} |
||||
} |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return(0); |
||||
} |
||||
|
||||
void reset_phys(void) |
||||
{ |
||||
int phyno; |
||||
unsigned short v; |
||||
|
||||
/* reset the damn phys */ |
||||
mii_init(); |
||||
|
||||
for (phyno = 0; phyno < 32; ++phyno) { |
||||
fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); |
||||
if (v == 0xFFFF) |
||||
continue; |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); |
||||
udelay(10000); |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, |
||||
BMCR_RESET | BMCR_ANENABLE); |
||||
udelay(10000); |
||||
} |
||||
} |
||||
|
||||
extern int board_dsp_reset(void); |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
int r; |
||||
|
||||
reset_phys(); |
||||
r = board_dsp_reset(); |
||||
if (r < 0) |
||||
printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* GP = general purpose, SP = special purpose (on chip peripheral) */ |
||||
|
||||
/* bits that can have a special purpose or can be configured as inputs/outputs */ |
||||
#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) |
||||
#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) |
||||
#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) |
||||
#define PA_ODR_VAL 0 |
||||
#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) |
||||
#define PA_SP_DIRVAL 0 |
||||
|
||||
#define PB_GP_INMASK (_B(28) | _B(31)) |
||||
#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) |
||||
#define PB_SP_MASK (_BR(22, 25)) |
||||
#define PB_ODR_VAL 0 |
||||
#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) |
||||
#define PB_SP_DIRVAL 0 |
||||
|
||||
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) |
||||
#define PC_GP_OUTMASK (_BW(6) | _BW(12)) |
||||
#define PC_SP_MASK (_BW(4) | _BW(8)) |
||||
#define PC_SOVAL 0 |
||||
#define PC_INTVAL _BW(7) |
||||
#define PC_GP_OUTVAL (_BW(6) | _BW(12)) |
||||
#define PC_SP_DIRVAL 0 |
||||
|
||||
#define PD_GP_INMASK 0 |
||||
#define PD_GP_OUTMASK _BWR(3, 15) |
||||
#define PD_SP_MASK 0 |
||||
|
||||
#if defined(CONFIG_NETTA_6412) |
||||
|
||||
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) |
||||
|
||||
#else |
||||
|
||||
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) |
||||
|
||||
#endif |
||||
|
||||
#define PD_SP_DIRVAL 0 |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile iop8xx_t *ioport = &immap->im_ioport; |
||||
volatile cpm8xx_t *cpm = &immap->im_cpm; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
/* CS1: NAND chip select */ |
||||
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; |
||||
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); |
||||
#if !defined(CONFIG_NETTA_6412) |
||||
/* CS2: DSP */ |
||||
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); |
||||
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); |
||||
#else |
||||
/* CS6: DSP */ |
||||
memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); |
||||
memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); |
||||
#endif |
||||
/* CS4: External register chip select */ |
||||
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); |
||||
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); |
||||
|
||||
/* CS5: dummy for accurate delay */ |
||||
memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); |
||||
memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); |
||||
|
||||
ioport->iop_padat = PA_GP_OUTVAL; |
||||
ioport->iop_paodr = PA_ODR_VAL; |
||||
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; |
||||
ioport->iop_papar = PA_SP_MASK; |
||||
|
||||
cpm->cp_pbdat = PB_GP_OUTVAL; |
||||
cpm->cp_pbodr = PB_ODR_VAL; |
||||
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; |
||||
cpm->cp_pbpar = PB_SP_MASK; |
||||
|
||||
ioport->iop_pcdat = PC_GP_OUTVAL; |
||||
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; |
||||
ioport->iop_pcso = PC_SOVAL; |
||||
ioport->iop_pcint = PC_INTVAL; |
||||
ioport->iop_pcpar = PC_SP_MASK; |
||||
|
||||
ioport->iop_pddat = PD_GP_OUTVAL; |
||||
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; |
||||
ioport->iop_pdpar = PD_SP_MASK; |
||||
|
||||
/* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
|
||||
int pcmcia_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
|
||||
void hw_watchdog_reset(void) |
||||
{ |
||||
/* XXX add here the really funky stuff */ |
||||
} |
||||
|
||||
#endif |
@ -1,346 +0,0 @@ |
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
#include <pcmcia.h> |
||||
|
||||
#undef CONFIG_PCMCIA |
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCMCIA |
||||
|
||||
/* some sane bit macros */ |
||||
#define _BD(_b) (1U << (31-(_b))) |
||||
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) |
||||
|
||||
#define _BW(_b) (1U << (15-(_b))) |
||||
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) |
||||
|
||||
#define _BB(_b) (1U << (7-(_b))) |
||||
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) |
||||
|
||||
#define _B(_b) _BD(_b) |
||||
#define _BR(_l, _h) _BDR(_l, _h) |
||||
|
||||
#define PCMCIA_BOARD_MSG "NETTA" |
||||
|
||||
static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; |
||||
|
||||
static void cfg_vppd(int no) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) |
||||
return; |
||||
|
||||
mask = vppd_masks[no]; |
||||
|
||||
immap->im_ioport.iop_papar &= ~mask; |
||||
immap->im_ioport.iop_paodr &= ~mask; |
||||
immap->im_ioport.iop_padir |= mask; |
||||
} |
||||
|
||||
static void set_vppd(int no, int what) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) |
||||
return; |
||||
|
||||
mask = vppd_masks[no]; |
||||
|
||||
if (what) |
||||
immap->im_ioport.iop_padat |= mask; |
||||
else |
||||
immap->im_ioport.iop_padat &= ~mask; |
||||
} |
||||
|
||||
static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; |
||||
|
||||
static void cfg_vccd(int no) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) |
||||
return; |
||||
|
||||
mask = vccd_masks[no]; |
||||
|
||||
immap->im_ioport.iop_papar &= ~mask; |
||||
immap->im_ioport.iop_paodr &= ~mask; |
||||
immap->im_ioport.iop_padir |= mask; |
||||
} |
||||
|
||||
static void set_vccd(int no, int what) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) |
||||
return; |
||||
|
||||
mask = vccd_masks[no]; |
||||
|
||||
if (what) |
||||
immap->im_ioport.iop_padat |= mask; |
||||
else |
||||
immap->im_ioport.iop_padat &= ~mask; |
||||
} |
||||
|
||||
static const unsigned short oc_mask = _BW(8); |
||||
|
||||
static void cfg_oc(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask = oc_mask; |
||||
|
||||
immap->im_ioport.iop_pcdir &= ~mask; |
||||
immap->im_ioport.iop_pcso &= ~mask; |
||||
immap->im_ioport.iop_pcint &= ~mask; |
||||
immap->im_ioport.iop_pcpar &= ~mask; |
||||
} |
||||
|
||||
static int get_oc(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask = oc_mask; |
||||
int what; |
||||
|
||||
what = !!(immap->im_ioport.iop_pcdat & mask);; |
||||
return what; |
||||
} |
||||
|
||||
static const unsigned short shdn_mask = _BW(12); |
||||
|
||||
static void cfg_shdn(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
mask = shdn_mask; |
||||
|
||||
immap->im_ioport.iop_papar &= ~mask; |
||||
immap->im_ioport.iop_paodr &= ~mask; |
||||
immap->im_ioport.iop_padir |= mask; |
||||
} |
||||
|
||||
static void set_shdn(int what) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
unsigned short mask; |
||||
|
||||
mask = shdn_mask; |
||||
|
||||
if (what) |
||||
immap->im_ioport.iop_padat |= mask; |
||||
else |
||||
immap->im_ioport.iop_padat &= ~mask; |
||||
} |
||||
|
||||
static void cfg_ports (void) |
||||
{ |
||||
cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ |
||||
cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ |
||||
cfg_shdn(); |
||||
cfg_oc(); |
||||
|
||||
/*
|
||||
* Configure Port A for TPS2211 PC-Card Power-Interface Switch |
||||
* |
||||
* Switch off all voltages, assert shutdown |
||||
*/ |
||||
set_vppd(0, 1); set_vppd(1, 1); |
||||
set_vccd(0, 0); set_vccd(1, 0); |
||||
set_shdn(1); |
||||
|
||||
udelay(100000); |
||||
} |
||||
|
||||
int pcmcia_hardware_enable(int slot) |
||||
{ |
||||
volatile pcmconf8xx_t *pcmp; |
||||
uint reg, pipr, mask; |
||||
int i; |
||||
|
||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
||||
|
||||
udelay(10000); |
||||
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
|
||||
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ |
||||
cfg_ports (); |
||||
|
||||
/* clear interrupt state, and disable interrupts */ |
||||
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); |
||||
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); |
||||
|
||||
/*
|
||||
* Disable interrupts, DMA, and PCMCIA buffers |
||||
* (isolate the interface) and assert RESET signal |
||||
*/ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = 0; |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(_slot_) = reg; |
||||
|
||||
udelay(500); |
||||
|
||||
/*
|
||||
* Make sure there is a card in the slot, then configure the interface. |
||||
*/ |
||||
udelay(10000); |
||||
debug ("[%d] %s: PIPR(%p)=0x%x\n", |
||||
__LINE__,__FUNCTION__, |
||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr); |
||||
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { |
||||
printf (" No Card found\n"); |
||||
return (1); |
||||
} |
||||
|
||||
/*
|
||||
* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z |
||||
*/ |
||||
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); |
||||
pipr = pcmp->pcmc_pipr; |
||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", |
||||
pipr, |
||||
(reg&PCMCIA_VS1(slot))?"n":"ff", |
||||
(reg&PCMCIA_VS2(slot))?"n":"ff"); |
||||
|
||||
if ((pipr & mask) == mask) { |
||||
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ |
||||
set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ |
||||
puts (" 5.0V card found: "); |
||||
} else { |
||||
set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ |
||||
set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ |
||||
puts (" 3.3V card found: "); |
||||
} |
||||
|
||||
/* Wait 500 ms; use this to check for over-current */ |
||||
for (i=0; i<5000; ++i) { |
||||
if (!get_oc()) { |
||||
printf (" *** Overcurrent - Safety shutdown ***\n"); |
||||
set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ |
||||
return (1); |
||||
} |
||||
udelay (100); |
||||
} |
||||
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
||||
reg = PCMCIA_PGCRX(_slot_); |
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(_slot_) = reg; |
||||
|
||||
udelay(250000); /* some cards need >150 ms to come up :-( */ |
||||
|
||||
debug ("# hardware_enable done\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
int pcmcia_hardware_disable(int slot) |
||||
{ |
||||
u_long reg; |
||||
|
||||
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
||||
|
||||
/* Configure PCMCIA General Control Register */ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = 0; |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(_slot_) = reg; |
||||
|
||||
/* All voltages off / Hi-Z */ |
||||
set_vppd(0, 1); set_vppd(1, 1); |
||||
set_vccd(0, 1); set_vccd(1, 1); |
||||
|
||||
udelay(10000); |
||||
|
||||
return (0); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
int pcmcia_voltage_set(int slot, int vcc, int vpp) |
||||
{ |
||||
volatile pcmconf8xx_t *pcmp; |
||||
u_long reg; |
||||
|
||||
debug ("voltage_set: " |
||||
PCMCIA_BOARD_MSG |
||||
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", |
||||
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); |
||||
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
/*
|
||||
* Disable PCMCIA buffers (isolate the interface) |
||||
* and assert RESET signal |
||||
*/ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = PCMCIA_PGCRX(_slot_); |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(_slot_) = reg; |
||||
udelay(500); |
||||
|
||||
/*
|
||||
* Configure Port C pins for |
||||
* 5 Volts Enable and 3 Volts enable, |
||||
* Turn all power pins to Hi-Z |
||||
*/ |
||||
debug ("PCMCIA power OFF\n"); |
||||
cfg_ports (); /* Enables switch, but all in Hi-Z */ |
||||
|
||||
set_vppd(0, 1); set_vppd(1, 1); |
||||
|
||||
switch(vcc) { |
||||
case 0: |
||||
break; /* Switch off */ |
||||
|
||||
case 33: |
||||
set_vccd(0, 1); set_vccd(1, 0); |
||||
break; |
||||
|
||||
case 50: |
||||
set_vccd(0, 0); set_vccd(1, 1); |
||||
break; |
||||
|
||||
default: |
||||
goto done; |
||||
} |
||||
|
||||
/* Checking supported voltages */ |
||||
|
||||
debug ("PIPR: 0x%x --> %s\n", |
||||
pcmp->pcmc_pipr, |
||||
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); |
||||
|
||||
done: |
||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
||||
reg = PCMCIA_PGCRX(_slot_); |
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(_slot_) = reg; |
||||
udelay(500); |
||||
|
||||
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", |
||||
slot+'A'); |
||||
return (0); |
||||
} |
||||
|
||||
#endif /* CONFIG_PCMCIA */ |
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,8 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = netta2.o flash.o
|
@ -1,490 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info); |
||||
static int write_byte(flash_info_t * info, ulong dest, uchar data); |
||||
static void flash_get_offsets(ulong base, flash_info_t * info); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
unsigned long size; |
||||
int i; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
|
||||
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size, size << 20); |
||||
} |
||||
|
||||
/* Remap FLASH according to real size */ |
||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); |
||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
||||
|
||||
flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
||||
|
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, |
||||
&flash_info[0]); |
||||
|
||||
flash_protect ( FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR, |
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
|
||||
#ifdef CONFIG_ENV_ADDR_REDUND |
||||
flash_protect ( FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR_REDUND, |
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
flash_info[0].size = size; |
||||
|
||||
return (size); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets(ulong base, flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
/* set up sector start address table */ |
||||
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} |
||||
} else if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info(flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: |
||||
printf("AMD "); |
||||
break; |
||||
case FLASH_MAN_FUJ: |
||||
printf("FUJITSU "); |
||||
break; |
||||
case FLASH_MAN_MX: |
||||
printf("MXIC "); |
||||
break; |
||||
default: |
||||
printf("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM040: |
||||
printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400B: |
||||
printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400T: |
||||
printf("AM29LV400T (4 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM800B: |
||||
printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM800T: |
||||
printf("AM29LV800T (8 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM160B: |
||||
printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM160T: |
||||
printf("AM29LV160T (16 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM320B: |
||||
printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM320T: |
||||
printf("AM29LV320T (32 Mbit, top boot sector)\n"); |
||||
break; |
||||
default: |
||||
printf("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); |
||||
|
||||
printf(" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf("\n "); |
||||
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf("\n"); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info) |
||||
{ |
||||
short i; |
||||
uchar mid; |
||||
uchar pid; |
||||
vu_char *caddr = (vu_char *) addr; |
||||
ulong base = (ulong) addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
caddr[0x0555] = 0xAA; |
||||
caddr[0x02AA] = 0x55; |
||||
caddr[0x0555] = 0x90; |
||||
|
||||
mid = caddr[0]; |
||||
switch (mid) { |
||||
case (AMD_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case (FUJ_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
case (MX_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_MX; |
||||
break; |
||||
case (STM_MANUFACT & 0xFF): |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
pid = caddr[1]; /* device ID */ |
||||
switch (pid) { |
||||
case (AMD_ID_LV400T & 0xFF): |
||||
info->flash_id += FLASH_AM400T; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 512 kB */ |
||||
|
||||
case (AMD_ID_LV400B & 0xFF): |
||||
info->flash_id += FLASH_AM400B; |
||||
info->sector_count = 11; |
||||
info->size = 0x00080000; |
||||
break; /* => 512 kB */ |
||||
|
||||
case (AMD_ID_LV800T & 0xFF): |
||||
info->flash_id += FLASH_AM800T; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (AMD_ID_LV800B & 0xFF): |
||||
info->flash_id += FLASH_AM800B; |
||||
info->sector_count = 19; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case (AMD_ID_LV160T & 0xFF): |
||||
info->flash_id += FLASH_AM160T; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (AMD_ID_LV160B & 0xFF): |
||||
info->flash_id += FLASH_AM160B; |
||||
info->sector_count = 35; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case (AMD_ID_LV040B & 0xFF): |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; |
||||
break; |
||||
|
||||
case (STM_ID_M29W040B & 0xFF): |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; |
||||
break; |
||||
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case (AMD_ID_LV320T & 0xFF): |
||||
info->flash_id += FLASH_AM320T; |
||||
info->sector_count = 67; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
|
||||
case (AMD_ID_LV320B & 0xFF): |
||||
info->flash_id += FLASH_AM320B; |
||||
info->sector_count = 67; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
#endif |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
printf(" "); |
||||
/* set up sector start address table */ |
||||
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} |
||||
} else if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection: D0 = 1 if protected */ |
||||
caddr = (volatile unsigned char *)(info->start[i]); |
||||
info->protect[i] = caddr[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
caddr = (vu_char *) info->start[0]; |
||||
|
||||
caddr[0x0555] = 0xAA; |
||||
caddr[0x02AA] = 0x55; |
||||
caddr[0x0555] = 0xF0; |
||||
|
||||
udelay(20000); |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
vu_char *addr = (vu_char *) (info->start[0]); |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf("- missing\n"); |
||||
} else { |
||||
printf("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP)) { |
||||
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf("- Warning: %d protected sectors will not be erased!\n", prot); |
||||
} else { |
||||
printf("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0x80; |
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_char *) (info->start[sect]); |
||||
addr[0] = 0x30; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay(1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer(0); |
||||
last = start; |
||||
addr = (vu_char *) (info->start[l_sect]); |
||||
while ((addr[0] & 0x80) != 0x80) { |
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
||||
printf("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (vu_char *) info->start[0]; |
||||
addr[0] = 0xF0; /* reset bank */ |
||||
|
||||
printf(" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
int rc; |
||||
|
||||
while (cnt > 0) { |
||||
if ((rc = write_byte(info, addr++, *src++)) != 0) { |
||||
return (rc); |
||||
} |
||||
--cnt; |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_byte(flash_info_t * info, ulong dest, uchar data) |
||||
{ |
||||
vu_char *addr = (vu_char *) (info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((vu_char *) dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0xA0; |
||||
|
||||
*((vu_char *) dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer(0); |
||||
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { |
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
return (0); |
||||
} |
@ -1,624 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* U-Boot port on NetTA4 board |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "mpc8xx.h" |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
#include <watchdog.h> |
||||
#endif |
||||
|
||||
int fec8xx_miiphy_read(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short *value); |
||||
int fec8xx_miiphy_write(char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short value); |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/* some sane bit macros */ |
||||
#define _BD(_b) (1U << (31-(_b))) |
||||
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) |
||||
|
||||
#define _BW(_b) (1U << (15-(_b))) |
||||
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) |
||||
|
||||
#define _BB(_b) (1U << (7-(_b))) |
||||
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) |
||||
|
||||
#define _B(_b) _BD(_b) |
||||
#define _BR(_l, _h) _BDR(_l, _h) |
||||
|
||||
/****************************************************************/ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Return 1 always. |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION); |
||||
return (0); |
||||
} |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define CS_0000 0x00000000 |
||||
#define CS_0001 0x10000000 |
||||
#define CS_0010 0x20000000 |
||||
#define CS_0011 0x30000000 |
||||
#define CS_0100 0x40000000 |
||||
#define CS_0101 0x50000000 |
||||
#define CS_0110 0x60000000 |
||||
#define CS_0111 0x70000000 |
||||
#define CS_1000 0x80000000 |
||||
#define CS_1001 0x90000000 |
||||
#define CS_1010 0xA0000000 |
||||
#define CS_1011 0xB0000000 |
||||
#define CS_1100 0xC0000000 |
||||
#define CS_1101 0xD0000000 |
||||
#define CS_1110 0xE0000000 |
||||
#define CS_1111 0xF0000000 |
||||
|
||||
#define BS_0000 0x00000000 |
||||
#define BS_0001 0x01000000 |
||||
#define BS_0010 0x02000000 |
||||
#define BS_0011 0x03000000 |
||||
#define BS_0100 0x04000000 |
||||
#define BS_0101 0x05000000 |
||||
#define BS_0110 0x06000000 |
||||
#define BS_0111 0x07000000 |
||||
#define BS_1000 0x08000000 |
||||
#define BS_1001 0x09000000 |
||||
#define BS_1010 0x0A000000 |
||||
#define BS_1011 0x0B000000 |
||||
#define BS_1100 0x0C000000 |
||||
#define BS_1101 0x0D000000 |
||||
#define BS_1110 0x0E000000 |
||||
#define BS_1111 0x0F000000 |
||||
|
||||
#define GPL0_AAAA 0x00000000 |
||||
#define GPL0_AAA0 0x00200000 |
||||
#define GPL0_AAA1 0x00300000 |
||||
#define GPL0_000A 0x00800000 |
||||
#define GPL0_0000 0x00A00000 |
||||
#define GPL0_0001 0x00B00000 |
||||
#define GPL0_111A 0x00C00000 |
||||
#define GPL0_1110 0x00E00000 |
||||
#define GPL0_1111 0x00F00000 |
||||
|
||||
#define GPL1_0000 0x00000000 |
||||
#define GPL1_0001 0x00040000 |
||||
#define GPL1_1110 0x00080000 |
||||
#define GPL1_1111 0x000C0000 |
||||
|
||||
#define GPL2_0000 0x00000000 |
||||
#define GPL2_0001 0x00010000 |
||||
#define GPL2_1110 0x00020000 |
||||
#define GPL2_1111 0x00030000 |
||||
|
||||
#define GPL3_0000 0x00000000 |
||||
#define GPL3_0001 0x00004000 |
||||
#define GPL3_1110 0x00008000 |
||||
#define GPL3_1111 0x0000C000 |
||||
|
||||
#define GPL4_0000 0x00000000 |
||||
#define GPL4_0001 0x00001000 |
||||
#define GPL4_1110 0x00002000 |
||||
#define GPL4_1111 0x00003000 |
||||
|
||||
#define GPL5_0000 0x00000000 |
||||
#define GPL5_0001 0x00000400 |
||||
#define GPL5_1110 0x00000800 |
||||
#define GPL5_1111 0x00000C00 |
||||
#define LOOP 0x00000080 |
||||
|
||||
#define EXEN 0x00000040 |
||||
|
||||
#define AMX_COL 0x00000000 |
||||
#define AMX_ROW 0x00000020 |
||||
#define AMX_MAR 0x00000030 |
||||
|
||||
#define NA 0x00000008 |
||||
|
||||
#define UTA 0x00000004 |
||||
|
||||
#define TODT 0x00000002 |
||||
|
||||
#define LAST 0x00000001 |
||||
|
||||
#define A10_AAAA GPL0_AAAA |
||||
#define A10_AAA0 GPL0_AAA0 |
||||
#define A10_AAA1 GPL0_AAA1 |
||||
#define A10_000A GPL0_000A |
||||
#define A10_0000 GPL0_0000 |
||||
#define A10_0001 GPL0_0001 |
||||
#define A10_111A GPL0_111A |
||||
#define A10_1110 GPL0_1110 |
||||
#define A10_1111 GPL0_1111 |
||||
|
||||
#define RAS_0000 GPL1_0000 |
||||
#define RAS_0001 GPL1_0001 |
||||
#define RAS_1110 GPL1_1110 |
||||
#define RAS_1111 GPL1_1111 |
||||
|
||||
#define CAS_0000 GPL2_0000 |
||||
#define CAS_0001 GPL2_0001 |
||||
#define CAS_1110 GPL2_1110 |
||||
#define CAS_1111 GPL2_1111 |
||||
|
||||
#define WE_0000 GPL3_0000 |
||||
#define WE_0001 GPL3_0001 |
||||
#define WE_1110 GPL3_1110 |
||||
#define WE_1111 GPL3_1111 |
||||
|
||||
/* #define CAS_LATENCY 3 */ |
||||
#define CAS_LATENCY 2 |
||||
|
||||
const uint sdram_table[0x40] = { |
||||
|
||||
#if CAS_LATENCY == 3 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
#endif |
||||
|
||||
#if CAS_LATENCY == 2 |
||||
/* RSS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* RBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, |
||||
|
||||
/* WBS */ |
||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ |
||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ |
||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ |
||||
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
#endif |
||||
|
||||
/* UPT */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ |
||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, |
||||
|
||||
/* EXC */ |
||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, |
||||
_NOT_USED_, |
||||
|
||||
/* REG */ |
||||
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, |
||||
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, |
||||
}; |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 2 |
||||
static const uint nandcs_table[0x40] = { |
||||
/* RSS */ |
||||
CS_1000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1110 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_0000 | GPL5_1111, |
||||
CS_0000 | GPL4_0001 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ |
||||
|
||||
/* RBS */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* WSS */ |
||||
CS_1000 | GPL4_1111 | GPL5_1110 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_0001 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA, |
||||
CS_0000 | GPL4_1111 | GPL5_1111, |
||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, |
||||
|
||||
/* WBS */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* UPT */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/* EXC */ |
||||
CS_0001 | LAST, |
||||
_NOT_USED_, |
||||
|
||||
/* REG */ |
||||
CS_1110 , |
||||
CS_0001 | LAST, |
||||
}; |
||||
#endif |
||||
|
||||
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ |
||||
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ |
||||
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) |
||||
|
||||
/* 8 */ |
||||
#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
void check_ram(unsigned int addr, unsigned int size) |
||||
{ |
||||
unsigned int i, j, v, vv; |
||||
volatile unsigned int *p; |
||||
unsigned int pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
pv = (unsigned int)p; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) |
||||
*p++ = pv; |
||||
|
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
v = (unsigned int)p; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
p++; |
||||
} |
||||
|
||||
for (j = 0; j < 5; j++) { |
||||
switch (j) { |
||||
case 0: v = 0x00000000; break; |
||||
case 1: v = 0xffffffff; break; |
||||
case 2: v = 0x55555555; break; |
||||
case 3: v = 0xaaaaaaaa; break; |
||||
default:v = 0xdeadbeef; break; |
||||
} |
||||
p = (unsigned int *)addr; |
||||
for (i = 0; i < size / sizeof(unsigned int); i++) { |
||||
*p = v; |
||||
vv = *p; |
||||
if (vv != v) { |
||||
printf("%p: read %08x instead of %08x\n", p, vv, v); |
||||
hang(); |
||||
} |
||||
*p = ~v; |
||||
p++; |
||||
} |
||||
} |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size; |
||||
|
||||
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh |
||||
*/ |
||||
memctl->memc_mptpr = MPTPR_PTP_DIV8; |
||||
|
||||
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ |
||||
|
||||
/*
|
||||
* Map controller bank 3 to the SDRAM bank at preliminary address. |
||||
*/ |
||||
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; |
||||
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; |
||||
|
||||
memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform SDRAM initialisation sequence */ |
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ |
||||
udelay(1); |
||||
|
||||
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ |
||||
|
||||
udelay(10000); |
||||
|
||||
{ |
||||
u32 d1, d2; |
||||
|
||||
d1 = 0xAA55AA55; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
|
||||
d1 = 0x55AA55AA; |
||||
*(volatile u32 *)0 = d1; |
||||
d2 = *(volatile u32 *)0; |
||||
if (d1 != d2) { |
||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); |
||||
hang(); |
||||
} |
||||
} |
||||
|
||||
size = get_ram_size((long *)0, SDRAM_MAX_SIZE); |
||||
|
||||
if (size == 0) { |
||||
printf("SIZE is zero: LOOP on 0\n"); |
||||
for (;;) { |
||||
*(volatile u32 *)0 = 0; |
||||
(void)*(volatile u32 *)0; |
||||
} |
||||
} |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
void reset_phys(void) |
||||
{ |
||||
int phyno; |
||||
unsigned short v; |
||||
|
||||
udelay(10000); |
||||
/* reset the damn phys */ |
||||
mii_init(); |
||||
|
||||
for (phyno = 0; phyno < 32; ++phyno) { |
||||
fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); |
||||
if (v == 0xFFFF) |
||||
continue; |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); |
||||
udelay(10000); |
||||
fec8xx_miiphy_write(NULL, phyno, MII_BMCR, |
||||
BMCR_RESET | BMCR_ANENABLE); |
||||
udelay(10000); |
||||
} |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/* GP = general purpose, SP = special purpose (on chip peripheral) */ |
||||
|
||||
/* bits that can have a special purpose or can be configured as inputs/outputs */ |
||||
#define PA_GP_INMASK 0 |
||||
#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) |
||||
#define PA_SP_MASK 0 |
||||
#define PA_ODR_VAL 0 |
||||
#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) |
||||
#define PA_SP_DIRVAL 0 |
||||
|
||||
#define PB_GP_INMASK _B(28) |
||||
#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) |
||||
#define PB_SP_MASK (_BR(22, 25)) |
||||
#define PB_ODR_VAL 0 |
||||
#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) |
||||
#define PB_SP_DIRVAL 0 |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
#define PC_GP_INMASK _BW(12) |
||||
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) |
||||
#elif CONFIG_NETTA2_VERSION == 2 |
||||
#define PC_GP_INMASK (_BW(13) | _BW(15)) |
||||
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) |
||||
#endif |
||||
#define PC_SP_MASK 0 |
||||
#define PC_SOVAL 0 |
||||
#define PC_INTVAL 0 |
||||
#define PC_GP_OUTVAL (_BW(10) | _BW(11)) |
||||
#define PC_SP_DIRVAL 0 |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
#define PE_GP_INMASK _B(31) |
||||
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) |
||||
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) |
||||
#elif CONFIG_NETTA2_VERSION == 2 |
||||
#define PE_GP_INMASK _BR(28, 31) |
||||
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) |
||||
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) |
||||
#endif |
||||
#define PE_SP_MASK 0 |
||||
#define PE_ODR_VAL 0 |
||||
#define PE_SP_DIRVAL 0 |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile iop8xx_t *ioport = &immap->im_ioport; |
||||
volatile cpm8xx_t *cpm = &immap->im_cpm; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
/* NAND chip select */ |
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); |
||||
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); |
||||
#elif CONFIG_NETTA2_VERSION == 2 |
||||
upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); |
||||
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); |
||||
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); |
||||
memctl->memc_mamr = 0; /* all clear */ |
||||
#endif |
||||
|
||||
/* DSP chip select */ |
||||
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); |
||||
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
memctl->memc_br4 &= ~BR_V; |
||||
#endif |
||||
memctl->memc_br5 &= ~BR_V; |
||||
memctl->memc_br6 &= ~BR_V; |
||||
memctl->memc_br7 &= ~BR_V; |
||||
|
||||
ioport->iop_padat = PA_GP_OUTVAL; |
||||
ioport->iop_paodr = PA_ODR_VAL; |
||||
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; |
||||
ioport->iop_papar = PA_SP_MASK; |
||||
|
||||
cpm->cp_pbdat = PB_GP_OUTVAL; |
||||
cpm->cp_pbodr = PB_ODR_VAL; |
||||
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; |
||||
cpm->cp_pbpar = PB_SP_MASK; |
||||
|
||||
ioport->iop_pcdat = PC_GP_OUTVAL; |
||||
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; |
||||
ioport->iop_pcso = PC_SOVAL; |
||||
ioport->iop_pcint = PC_INTVAL; |
||||
ioport->iop_pcpar = PC_SP_MASK; |
||||
|
||||
cpm->cp_pedat = PE_GP_OUTVAL; |
||||
cpm->cp_peodr = PE_ODR_VAL; |
||||
cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; |
||||
cpm->cp_pepar = PE_SP_MASK; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
|
||||
void hw_watchdog_reset(void) |
||||
{ |
||||
/* XXX add here the really funky stuff */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
||||
int overwrite_console(void) |
||||
{ |
||||
/* printf("overwrite_console called\n"); */ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
extern int drv_phone_init(void); |
||||
extern int drv_phone_use_me(void); |
||||
extern int drv_phone_is_idle(void); |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
#if CONFIG_NETTA2_VERSION == 2 |
||||
int i; |
||||
#endif |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 2 |
||||
/* assert peripheral reset */ |
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); |
||||
for (i = 0; i < 10; i++) |
||||
udelay(1000); |
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); |
||||
#endif |
||||
reset_phys(); |
||||
|
||||
return 0; |
||||
} |
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,701 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* U-Boot port on NetTA4 board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 |
||||
#error Unsupported CONFIG_NETPHONE version |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ |
||||
#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
/* #define CONFIG_XIN 10000000 */ |
||||
#define CONFIG_XIN 50000000 |
||||
/* #define MPC8XX_HZ 120000000 */ |
||||
#define MPC8XX_HZ 66666666 |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"tftpboot; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_SOURCE |
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_NISDOMAIN |
||||
|
||||
#undef CONFIG_MAC_PARTITION |
||||
#undef CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define FEC_ENET 1 /* eth.c needs it that way... */ |
||||
#undef CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_MII_INIT 1 |
||||
#define CONFIG_RMII 1 /* use RMII interface */ |
||||
|
||||
#define CONFIG_ETHER_ON_FEC1 1 |
||||
#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ |
||||
#define CONFIG_FEC1_PHY_NORXERR 1 |
||||
|
||||
#define CONFIG_ETHER_ON_FEC2 1 |
||||
#define CONFIG_FEC2_PHY 4 |
||||
#define CONFIG_FEC2_PHY_NORXERR 1 |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_CDP |
||||
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#if CONFIG_NETPHONE_VERSION == 2 |
||||
#define CONFIG_SYS_FLASH_BASE4 0x40080000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#elif CONFIG_NETPHONE_VERSION == 2 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#endif |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
*/ |
||||
|
||||
#if CONFIG_XIN == 10000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 50000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 25000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 40000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 75000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 10MHz |
||||
#endif |
||||
|
||||
#elif CONFIG_XIN == 50000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 66666666 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 50MHz |
||||
#endif |
||||
|
||||
#else |
||||
|
||||
#error unsupported XIN freq |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------- |
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
* |
||||
* Note: When TBS == 0 the timebase is independent of current cpu clock. |
||||
*/ |
||||
|
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#if MPC8XX_HZ > 66666666 |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00 | SCCR_EBDF01) |
||||
#else |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 2 |
||||
|
||||
#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ |
||||
|
||||
#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* BR3 and OR3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MAMR_PTA 234 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define DSP_SIZE 0x00010000 /* 64K */ |
||||
#define NAND_SIZE 0x00010000 /* 64K */ |
||||
|
||||
#define DSP_BASE 0xF1000000 |
||||
#define NAND_BASE 0xF1010000 |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#if CONFIG_NETPHONE_VERSION == 1 |
||||
#define STATUS_LED_BIT 0x00000008 /* bit 28 */ |
||||
#elif CONFIG_NETPHONE_VERSION == 2 |
||||
#define STATUS_LED_BIT 0x00000080 /* bit 24 */ |
||||
#endif |
||||
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_STATE STATUS_LED_BLINKING |
||||
|
||||
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ |
||||
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/* LEDs */ |
||||
|
||||
/* led_id_t is unsigned int mask */ |
||||
typedef unsigned int led_id_t; |
||||
|
||||
#define __led_toggle(_msk) \ |
||||
do { \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_set(_msk, _st) \ |
||||
do { \
|
||||
if ((_st)) \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
|
||||
else \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_init(msk, st) __led_set(msk, st) |
||||
|
||||
#endif |
||||
|
||||
/***********************************************************************************************************
|
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
(V1) version 1 of the board |
||||
(V2) version 2 of the board |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Pin definitions: |
||||
|
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| # | Name | Type | Comment |
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| PA3 | SPIEN_MAX | Output | MAX serial to uart chip select |
||||
| PA7 | DSP_INT | Output | DSP interrupt |
||||
| PA10 | DSP_RESET | Output | DSP reset |
||||
| PA14 | USBOE | Output | USB (1) |
||||
| PA15 | USBRXD | Output | USB (1) |
||||
| PB19 | BT_RTS | Output | Bluetooth (0) |
||||
| PB23 | BT_CTS | Output | Bluetooth (0) |
||||
| PB26 | SPIEN_SEP | Output | Serial EEPROM chip select |
||||
| PB27 | SPICS_DISP | Output | Display chip select |
||||
| PB28 | SPI_RXD_3V | Input | SPI Data Rx |
||||
| PB29 | SPI_TXD | Output | SPI Data Tx |
||||
| PB30 | SPI_CLK | Output | SPI Clock |
||||
| PC10 | DISPA0 | Output | Display A0 |
||||
| PC11 | BACKLIGHT | Output | Display backlit |
||||
| PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD |
||||
| | IO_RESET | Output | (V2) General I/O reset |
||||
| PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) |
||||
| | HOOK | Input | (V2) Hook input interrupt |
||||
| PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK |
||||
| | F_RY_BY | Input | (V2) NAND F_RY_BY |
||||
| PE17 | F_ALE | Output | NAND F_ALE |
||||
| PE18 | F_CLE | Output | NAND F_CLE |
||||
| PE20 | F_CE | Output | NAND F_CE |
||||
| PE24 | SPICS_SCOUT | Output | (V1) Codec chip select |
||||
| | LED | Output | (V2) LED |
||||
| PE27 | SPICS_ER | Output | External serial register CS |
||||
| PE28 | LEDIO1 | Output | (V1) LED |
||||
| | BKBR1 | Input | (V2) Keyboard input scan |
||||
| PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) |
||||
| | BKBR2 | Input | (V2) Keyboard input scan |
||||
| PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) |
||||
| | BKBR3 | Input | (V2) Keyboard input scan |
||||
| PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY |
||||
| | BKBR4 | Input | (V2) Keyboard input scan |
||||
+------+----------------+--------+--------------------------------------------------- |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Serial register input: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| 0 | BKBR1 | (V1) Keyboard input scan |
||||
| 1 | BKBR3 | (V1) Keyboard input scan |
||||
| 2 | BKBR4 | (V1) Keyboard input scan |
||||
| 3 | BKBR2 | (V1) Keyboard input scan |
||||
| 4 | HOOK | (V1) Hook switch |
||||
| 5 | BT_LINK | (V1) Bluetooth link status |
||||
| 6 | HOST_WAKE | (V1) Bluetooth host wake up |
||||
| 7 | OK_ETH | (V1) Cisco inline power OK status |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Serial register output: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| 0 | KEY1 | Keyboard output scan |
||||
| 1 | KEY2 | Keyboard output scan |
||||
| 2 | KEY3 | Keyboard output scan |
||||
| 3 | KEY4 | Keyboard output scan |
||||
| 4 | KEY5 | Keyboard output scan |
||||
| 5 | KEY6 | Keyboard output scan |
||||
| 6 | KEY7 | Keyboard output scan |
||||
| 7 | BT_WAKE | Bluetooth wake up |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Chip selects: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| CS0 | CS0 | Boot flash |
||||
| CS1 | CS_FLASH | NAND flash |
||||
| CS2 | CS_DSP | DSP |
||||
| CS3 | DCS_DRAM | DRAM |
||||
| CS4 | CS_FLASH2 | (V2) 2nd flash |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Interrupts: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| IRQ1 | IRQ_DSP | DSP interrupt |
||||
| IRQ3 | S_INTER | DUSLIC ??? |
||||
| IRQ4 | F_RY_BY | NAND |
||||
| IRQ7 | IRQ_MAX | MAX 3100 interrupt |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Interrupts on PCMCIA pins: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface |
||||
| IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface |
||||
| IP_A2| RMII1_MDINT | PHY interrupt for #1 |
||||
| IP_A3| RMII2_MDINT | PHY interrupt for #2 |
||||
| IP_A5| HOST_WAKE | (V2) Bluetooth host wake |
||||
| IP_A6| OK_ETH | (V2) Cisco inline power OK |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
*************************************************************************************************/ |
||||
|
||||
#define CONFIG_SED156X 1 /* use SED156X */ |
||||
#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ |
||||
|
||||
/* serial interfacing macros */ |
||||
|
||||
#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
||||
#define SED156X_SPI_RXD_MASK 0x00000008 |
||||
|
||||
#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
||||
#define SED156X_SPI_TXD_MASK 0x00000004 |
||||
|
||||
#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
||||
#define SED156X_SPI_CLK_MASK 0x00000002 |
||||
|
||||
#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
||||
#define SED156X_CS_MASK 0x00000010 |
||||
|
||||
#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |
||||
#define SED156X_A0_MASK 0x0020 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 |
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
/* use board specific hardware */ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_HW_WATCHDOG |
||||
#define CONFIG_SHOW_ACTIVITY |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
/* phone console configuration */ |
||||
|
||||
#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CDP_DEVICE_ID 20 |
||||
#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ |
||||
#define CONFIG_CDP_PORT_ID "eth%d" |
||||
#define CONFIG_CDP_CAPABILITIES 0x00000010 |
||||
#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME |
||||
#define CONFIG_CDP_PLATFORM "Intracom NetPhone" |
||||
#define CONFIG_CDP_TRIGGER 0x20020001 |
||||
#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ |
||||
#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CRC32_VERIFY 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
#endif /* __CONFIG_H */ |
@ -1,666 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* U-Boot port on NetTA4 board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ |
||||
#define CONFIG_NETTA 1 /* ...on a NetTA board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
/* #define CONFIG_XIN 10000000 */ |
||||
#define CONFIG_XIN 50000000 |
||||
#define MPC8XX_HZ 120000000 |
||||
/* #define MPC8XX_HZ 100000000 */ |
||||
/* #define MPC8XX_HZ 50000000 */ |
||||
/* #define MPC8XX_HZ 80000000 */ |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"tftpboot; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_HW_WATCHDOG |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_NISDOMAIN |
||||
|
||||
|
||||
#undef CONFIG_MAC_PARTITION |
||||
#undef CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define FEC_ENET 1 /* eth.c needs it that way... */ |
||||
#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */ |
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_MII_INIT 1 |
||||
#define CONFIG_RMII 1 /* use RMII interface */ |
||||
|
||||
#if defined(CONFIG_NETTA_ISDN) |
||||
#define CONFIG_ETHER_ON_FEC1 1 |
||||
#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ |
||||
#define CONFIG_FEC1_PHY_NORXERR 1 |
||||
#undef CONFIG_ETHER_ON_FEC2 |
||||
#else |
||||
#define CONFIG_ETHER_ON_FEC1 1 |
||||
#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ |
||||
#define CONFIG_FEC1_PHY_NORXERR 1 |
||||
#define CONFIG_ETHER_ON_FEC2 1 |
||||
#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ |
||||
#define CONFIG_FEC2_PHY_NORXERR 1 |
||||
#endif |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
||||
CONFIG_SYS_POST_CODEC | \
|
||||
CONFIG_SYS_POST_DSP ) |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CDP |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PCMCIA |
||||
#define CONFIG_CMD_PING |
||||
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
*/ |
||||
|
||||
#if CONFIG_XIN == 10000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 50000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 25000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 40000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 75000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 10MHz |
||||
#endif |
||||
|
||||
#elif CONFIG_XIN == 50000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 80000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 50000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 50MHz |
||||
#endif |
||||
|
||||
#else |
||||
|
||||
#error unsupported XIN freq |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------- |
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
* |
||||
* Note: When TBS == 0 the timebase is independent of current cpu clock. |
||||
*/ |
||||
|
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#if MPC8XX_HZ > 66666666 |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00 | SCCR_EBDF01) |
||||
#else |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR3 and OR3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_MAMR_PTA 234 |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_MAMR_PTA 195 |
||||
#elif MPC8XX_HZ == 80000000 |
||||
#define CONFIG_SYS_MAMR_PTA 156 |
||||
#elif MPC8XX_HZ == 50000000 |
||||
#define CONFIG_SYS_MAMR_PTA 98 |
||||
#else |
||||
#error Unknown frequency |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
||||
|
||||
/***********************************************************************************************************
|
||||
|
||||
Pin definitions: |
||||
|
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| # | Name | Type | Comment |
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK |
||||
| | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) |
||||
| PA6 | P_VCCD1 | Output | TPS2211A PCMCIA |
||||
| PA7 | DCL1_3V | Periph | IDL1 PCM clock |
||||
| PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx |
||||
| PA9 | L1TXDA | Periph | IDL1 PCM Data Tx |
||||
| PA10 | P_VCCD0 | Output | TPS2211A PCMCIA |
||||
| PA12 | P_SHDN | Output | TPS2211A PCMCIA |
||||
| PA13 | ETH_LOOP | Output | CISCO Loopback remote power |
||||
| | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) |
||||
| PA14 | P_VPPD0 | Output | TPS2211A PCMCIA |
||||
| PA15 | P_VPPD1 | Output | TPS2211A PCMCIA |
||||
| PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board |
||||
| PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) |
||||
| PB16 | DREQ1 | Output | D channel request for S-interface chip 1. |
||||
| PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC |
||||
| PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC |
||||
| PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) |
||||
| PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom |
||||
| PB21 | LEDIO | Output | Led mode indication for PHY |
||||
| PB22 | UART_CTS | Input | UART CTS |
||||
| PB23 | UART_RTS | Output | UART RTS |
||||
| PB24 | UART_RX | Periph | UART Data Rx |
||||
| PB25 | UART_TX | Periph | UART Data Tx |
||||
| PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) |
||||
| PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) |
||||
| PB28 | SPI_RXD_3V | Input | SPI Data Rx |
||||
| PB29 | SPI_TXD | Output | SPI Data Tx |
||||
| PB30 | SPI_CLK | Output | SPI Clock |
||||
| PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 |
||||
| PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) |
||||
| PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) |
||||
| PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) |
||||
| PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) |
||||
| PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) |
||||
| PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) |
||||
| PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) |
||||
| PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) |
||||
| PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) |
||||
| PC13 | F_RY_BY | Input | NAND ready signal (interrupt) |
||||
| PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) |
||||
| PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. |
||||
| PD3 | F_ALE | Output | NAND |
||||
| PD4 | F_CLE | Output | NAND |
||||
| PD5 | F_CE | Output | NAND |
||||
| PD6 | DSP_INT | Output | DSP debug interrupt |
||||
| PD7 | DSP_RESET | Output | DSP reset |
||||
| PD8 | RMII_MDC | Periph | MII mgt clock |
||||
| PD9 | SPIEN_C1 | Output | SPI CS for codec #1 |
||||
| PD10 | SPIEN_C2 | Output | SPI CS for codec #2 |
||||
| PD11 | SPIEN_C3 | Output | SPI CS for codec #3 |
||||
| PD12 | FSC2 | Periph | IDL2 frame sync |
||||
| PD13 | DGRANT2 | Input | D channel grant from S #2 |
||||
| PD14 | SPIEN_C4 | Output | SPI CS for codec #4 |
||||
| PD15 | TP700 | Output | Testpoint for software debugging |
||||
| PE14 | RMII2-TXD0 | Periph | FEC2 transmit data |
||||
| PE15 | RMII2-TXD1 | Periph | FEC2 transmit data |
||||
| PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for |
||||
| | DCL2 | Periph | NetRoute: PCM clock #2 |
||||
| PE17 | TP703 | Output | Testpoint for software debugging |
||||
| PE18 | DGRANT1 | Input | D channel grant from S #1 |
||||
| PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable |
||||
| | PCM2OUT | Periph | NetRoute: Tx data for IDL2 |
||||
| PE20 | FSC1 | Periph | IDL1 frame sync |
||||
| PE21 | RMII2-RXD0 | Periph | FEC2 receive data |
||||
| PE22 | RMII2-RXD1 | Periph | FEC2 receive data |
||||
| PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC |
||||
| PE24 | U-N1 | Output | Select user/network for S #1 (0=user) |
||||
| PE25 | U-N2 | Output | Select user/network for S #2 (0=user) |
||||
| PE26 | RMII2-RXDV | Periph | FEC2 valid |
||||
| PE27 | DREQ2 | Output | D channel request for S #2. |
||||
| PE28 | FPGA_DONE | Input | FPGA done signal |
||||
| PE29 | FPGA_INIT | Output | FPGA init signal |
||||
| PE30 | UDOUT2_3V | Input | IDL2 PCM input |
||||
| PE31 | | | Free |
||||
+------+----------------+--------+--------------------------------------------------- |
||||
|
||||
Chip selects: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| CS0 | CS0 | Boot flash |
||||
| CS1 | CS_FLASH | NAND flash |
||||
| CS2 | CS_DSP | DSP |
||||
| CS3 | DCS_DRAM | DRAM |
||||
| CS4 | CS_ER1 | External output register |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
Interrupts: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| IRQ1 | UINTER_3V | S interrupt chips interrupt (common) |
||||
| IRQ3 | IRQ_DSP | DSP interrupt |
||||
| IRQ4 | IRQ_DSP1 | Extra DSP interrupt |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
*************************************************************************************************/ |
||||
|
||||
#define DSP_SIZE 0x00010000 /* 64K */ |
||||
#define NAND_SIZE 0x00010000 /* 64K */ |
||||
#define ER_SIZE 0x00010000 /* 64K */ |
||||
#define DUMMY_SIZE 0x00010000 /* 64K */ |
||||
|
||||
#define DSP_BASE 0xF1000000 |
||||
#define NAND_BASE 0xF1010000 |
||||
#define ER_BASE 0xF1020000 |
||||
#define DUMMY_BASE 0xF1FF0000 |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP |
||||
#define CONFIG_SYS_DIRECT_NAND_TFTP |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#if 1 |
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CDP_DEVICE_ID 20 |
||||
#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ |
||||
#define CONFIG_CDP_PORT_ID "eth%d" |
||||
#define CONFIG_CDP_CAPABILITIES 0x00000010 |
||||
#define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME |
||||
#define CONFIG_CDP_PLATFORM "Intracom NetTA" |
||||
#define CONFIG_CDP_TRIGGER 0x20020001 |
||||
#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ |
||||
#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CRC32_VERIFY 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -1,654 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr |
||||
* U-Boot port on NetTA4 board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2 |
||||
#error Unsupported CONFIG_NETTA2 version |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ |
||||
#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
|
||||
/* #define CONFIG_XIN 10000000 */ |
||||
#define CONFIG_XIN 50000000 |
||||
/* #define MPC8XX_HZ 120000000 */ |
||||
#define MPC8XX_HZ 66666666 |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"tftpboot; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_SOURCE |
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_NISDOMAIN |
||||
|
||||
|
||||
#undef CONFIG_MAC_PARTITION |
||||
#undef CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define FEC_ENET 1 /* eth.c needs it that way... */ |
||||
#undef CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_MII 1 |
||||
#define CONFIG_MII_INIT 1 |
||||
#define CONFIG_RMII 1 /* use RMII interface */ |
||||
|
||||
#define CONFIG_ETHER_ON_FEC1 1 |
||||
#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ |
||||
#define CONFIG_FEC1_PHY_NORXERR 1 |
||||
|
||||
#define CONFIG_ETHER_ON_FEC2 1 |
||||
#define CONFIG_FEC2_PHY 4 |
||||
#define CONFIG_FEC2_PHY_NORXERR 1 |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_CDP |
||||
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#if CONFIG_NETTA2_VERSION == 2 |
||||
#define CONFIG_SYS_FLASH_BASE4 0x40080000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#elif CONFIG_NETTA2_VERSION == 2 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#endif |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
||||
#define CONFIG_ENV_OFFSET 0 |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
||||
#define CONFIG_ENV_OFFSET_REDUND 0 |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
*/ |
||||
|
||||
#if CONFIG_XIN == 10000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 50000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 25000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 40000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 75000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 10MHz |
||||
#endif |
||||
|
||||
#elif CONFIG_XIN == 50000000 |
||||
|
||||
#if MPC8XX_HZ == 120000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 100000000 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#elif MPC8XX_HZ == 66666666 |
||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
||||
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
|
||||
PLPRCR_TEXPS) |
||||
#else |
||||
#error unsupported CPU freq for XIN = 50MHz |
||||
#endif |
||||
|
||||
#else |
||||
|
||||
#error unsupported XIN freq |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------- |
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
* |
||||
* Note: When TBS == 0 the timebase is independent of current cpu clock. |
||||
*/ |
||||
|
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#if MPC8XX_HZ > 66666666 |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00 | SCCR_EBDF01) |
||||
#else |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 2 |
||||
|
||||
#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ |
||||
|
||||
#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* BR3 and OR3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MAMR_PTA 234 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
||||
|
||||
/****************************************************************/ |
||||
|
||||
#define DSP_SIZE 0x00010000 /* 64K */ |
||||
#define NAND_SIZE 0x00010000 /* 64K */ |
||||
|
||||
#define DSP_BASE 0xF1000000 |
||||
#define NAND_BASE 0xF1010000 |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#if CONFIG_NETTA2_VERSION == 1 |
||||
#define STATUS_LED_BIT 0x00000008 /* bit 28 */ |
||||
#elif CONFIG_NETTA2_VERSION == 2 |
||||
#define STATUS_LED_BIT 0x00000080 /* bit 24 */ |
||||
#endif |
||||
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_STATE STATUS_LED_BLINKING |
||||
|
||||
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ |
||||
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/* LEDs */ |
||||
|
||||
/* led_id_t is unsigned int mask */ |
||||
typedef unsigned int led_id_t; |
||||
|
||||
#define __led_toggle(_msk) \ |
||||
do { \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_set(_msk, _st) \ |
||||
do { \
|
||||
if ((_st)) \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
|
||||
else \
|
||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_init(msk, st) __led_set(msk, st) |
||||
|
||||
#endif |
||||
|
||||
/***********************************************************************************************************
|
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
(V1) version 1 of the board |
||||
(V2) version 2 of the board |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Pin definitions: |
||||
|
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| # | Name | Type | Comment |
||||
+------+----------------+--------+------------------------------------------------------------ |
||||
| PA3 | SPIEN_MAX | Output | MAX serial to uart chip select |
||||
| PA7 | DSP_INT | Output | DSP interrupt |
||||
| PA10 | DSP_RESET | Output | DSP reset |
||||
| PA14 | USBOE | Output | USB (1) |
||||
| PA15 | USBRXD | Output | USB (1) |
||||
| PB19 | BT_RTS | Output | Bluetooth (0) |
||||
| PB23 | BT_CTS | Output | Bluetooth (0) |
||||
| PB26 | SPIEN_SEP | Output | Serial EEPROM chip select |
||||
| PB27 | SPICS_DISP | Output | Display chip select |
||||
| PB28 | SPI_RXD_3V | Input | SPI Data Rx |
||||
| PB29 | SPI_TXD | Output | SPI Data Tx |
||||
| PB30 | SPI_CLK | Output | SPI Clock |
||||
| PC10 | DISPA0 | Output | Display A0 |
||||
| PC11 | BACKLIGHT | Output | Display backlit |
||||
| PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD |
||||
| | IO_RESET | Output | (V2) General I/O reset |
||||
| PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) |
||||
| | HOOK | Input | (V2) Hook input interrupt |
||||
| PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK |
||||
| | F_RY_BY | Input | (V2) NAND F_RY_BY |
||||
| PE17 | F_ALE | Output | NAND F_ALE |
||||
| PE18 | F_CLE | Output | NAND F_CLE |
||||
| PE20 | F_CE | Output | NAND F_CE |
||||
| PE24 | SPICS_SCOUT | Output | (V1) Codec chip select |
||||
| | LED | Output | (V2) LED |
||||
| PE27 | SPICS_ER | Output | External serial register CS |
||||
| PE28 | LEDIO1 | Output | (V1) LED |
||||
| | BKBR1 | Input | (V2) Keyboard input scan |
||||
| PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) |
||||
| | BKBR2 | Input | (V2) Keyboard input scan |
||||
| PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) |
||||
| | BKBR3 | Input | (V2) Keyboard input scan |
||||
| PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY |
||||
| | BKBR4 | Input | (V2) Keyboard input scan |
||||
+------+----------------+--------+--------------------------------------------------- |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Serial register input: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| 4 | HOOK | Hook switch |
||||
| 5 | BT_LINK | Bluetooth link status |
||||
| 6 | HOST_WAKE | Bluetooth host wake up |
||||
| 7 | OK_ETH | Cisco inline power OK status |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Chip selects: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| CS0 | CS0 | Boot flash |
||||
| CS1 | CS_FLASH | NAND flash |
||||
| CS2 | CS_DSP | DSP |
||||
| CS3 | DCS_DRAM | DRAM |
||||
| CS4 | CS_FLASH2 | (V2) 2nd flash |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Interrupts: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| IRQ1 | IRQ_DSP | DSP interrupt |
||||
| IRQ3 | S_INTER | DUSLIC ??? |
||||
| IRQ4 | F_RY_BY | NAND |
||||
| IRQ7 | IRQ_MAX | MAX 3100 interrupt |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
---------------------------------------------------------------------------------------------- |
||||
|
||||
Interrupts on PCMCIA pins: |
||||
|
||||
+------+----------------+------------------------------------------------------------ |
||||
| # | Name | Comment |
||||
+------+----------------+------------------------------------------------------------ |
||||
| IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface |
||||
| IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface |
||||
| IP_A2| RMII1_MDINT | PHY interrupt for #1 |
||||
| IP_A3| RMII2_MDINT | PHY interrupt for #2 |
||||
| IP_A5| HOST_WAKE | (V2) Bluetooth host wake |
||||
| IP_A6| OK_ETH | (V2) Cisco inline power OK |
||||
+------+----------------+------------------------------------------------------------ |
||||
|
||||
**************************************************************************************************/ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 |
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
/* use board specific hardware */ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_HW_WATCHDOG |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CDP_DEVICE_ID 20 |
||||
#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */ |
||||
#define CONFIG_CDP_PORT_ID "eth%d" |
||||
#define CONFIG_CDP_CAPABILITIES 0x00000010 |
||||
#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME |
||||
#define CONFIG_CDP_PLATFORM "Intracom NetTA2" |
||||
#define CONFIG_CDP_TRIGGER 0x20020001 |
||||
#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ |
||||
#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */ |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_CRC32_VERIFY 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
|
||||
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 |
||||
|
||||
/*************************************************************************************************/ |
||||
#endif /* __CONFIG_H */ |
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Reference in new issue