ppc4xx: Cleanup PMC405 board support

This patch fixes coding style for PMC405 board support.
Also some unneeded features/code is removed.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

board/esd/pmc405/pmc405.c

@@ -40,7 +40,6 @@ const unsigned char fpgadata[] =
 };
 int filesize = sizeof(fpgadata);
 
-
 int board_early_init_f (void)
 {
 	/*
@@ -55,23 +54,23 @@ int board_early_init_f (void)
 	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(uicer, 0x00000000); /* disable all ints */
+	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+	mtdcr(uictr, 0x10000000); /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
+	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
 
 	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 * EBC Configuration Register:
+	 * set ready timeout to 512 ebc-clks -> ca. 15 us
 	 */
 	mtebc (epcr, 0xa8400000);
 
 	/*
 	 * Setup GPIO pins
 	 */
-
 	mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
 					CONFIG_SYS_FPGA_DONE | \
 					CONFIG_SYS_XEREADY | \
@@ -85,26 +84,26 @@ int board_early_init_f (void)
 	}
 
 	out32(GPIO0_OR, 0);
-	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
+	/* setup for output */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \
+	      CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY);
 
-	/* - check if rev1_2 is low, then:
-	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
+	/*
+	 * - check if rev1_2 is low, then:
+	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
+	 *   in TCR to assert INTA# or SELFRST#
 	 */
-
 	return 0;
 }
 
-
-/* ------------------------------------------------------------------------- */
-
-
 int misc_init_r (void)
 {
 	/* adjust flash start and offset */
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
+	/* deassert EREADY# */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY);
 	return (0);
 }
 
@@ -113,16 +112,16 @@ ushort pmc405_pci_subsys_deviceid(void)
 	ulong val;
 	val = in32(GPIO0_IR);
 	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
-		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+		/* check monarch# signal */
+		if (val & CONFIG_SYS_NONMONARCH)
 			return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
-		}
 		return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
 	}
 	return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
 }
 
 /*
- * Check Board Identity:
+ * Check Board Identity
  */
 int checkboard (void)
 {
@@ -133,29 +132,25 @@ int checkboard (void)
 
 	puts ("Board: ");
 
-	if (i == -1) {
+	if (i == -1)
 		puts ("### No HW ID - assuming PMC405");
-	} else {
+	else
 		puts(str);
-	}
 
 	val = in32(GPIO0_IR);
 	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
 		puts(" rev1.2 (");
-		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+		if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
 			puts("non-");
-		}
 		puts("monarch)");
-	} else {
+	} else
 		puts(" <=rev1.1");
-	}
 
 	putc ('\n');
 
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP
@@ -166,43 +161,3 @@ void reset_phy(void)
 	lxt971_no_sleep();
 #endif
 }
-
-
-int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	ulong addr;
-	volatile uchar *ptr;
-	volatile uchar val;
-	int i;
-
-	addr = simple_strtol (argv[1], NULL, 16) + 0x16;
-
-	i = 0;
-	for (;;) {
-		ptr = (uchar *)addr;
-		for (i=0; i<8; i++) {
-			*ptr = i;
-			val = *ptr;
-
-			if (val != i) {
-				printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
-				return 0;
-			}
-
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			ptr++;
-		}
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	cantest,	3,	1,	do_cantest,
-	"Test CAN controller",
-	NULL
-	);

include/configs/PMC405.h

@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,16 +21,11 @@
  * MA 02111-1307 USA
  */
 
-/*
- * board/config.h - configuration options, board specific
- */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 /*
  * High Level Configuration Options
- * (easy to change)
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
@@ -45,13 +40,13 @@
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
-#undef	CONFIG_BOOTARGS
-#undef	CONFIG_BOOTCOMMAND
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
 
-#define CONFIG_PREBOOT                  /* enable preboot variable      */
+#define CONFIG_PREBOOT			/* enable preboot variable	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1	/* allow baudrate change	*/
 
 #define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
@@ -59,11 +54,8 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
+#define CONFIG_LXT971_NO_SLEEP	1	/* disable sleep mode in LXT971	*/
+#define CONFIG_RESET_PHY_R	1	/* use reset_phy()		*/
 
 /*
  * BOOTP options
@@ -73,7 +65,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -91,249 +82,253 @@
 #define CONFIG_CMD_UNIVERSE
 #define CONFIG_CMD_EEPROM
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible */
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	0xF0000500 /* RTC Base Address */
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
 
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
 
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_AUTO_COMPLETE		1       /* add autocompletion support */
 
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock */
+#define CONFIG_SYS_BASE_BAUD	691200
 
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_LOOPW		1	/* enable loopw command */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+#define CONFIG_SYS_RX_ETH_BUFFER	16
 
-/*-----------------------------------------------------------------------
+/*
  * PCI stuff
- *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1	/* don't skip host bridge config */
 
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable */
 
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408  /* PCI Device ID: Non-Monarch */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409     /* PCI Device ID: Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
 
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#if 1
-#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs       */
-#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                 */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
-#else /* old mapping */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-#endif
-/*-----------------------------------------------------------------------
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
+
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram	*/
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA  0xef000000	/* point to internal regs */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001	/* 16MB, enable */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address */
+
+/*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 
-/*-----------------------------------------------------------------------
+/*
  * FLASH organization
  */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000
 #define CONFIG_SYS_FLASH_INCREMENT	0x01000000
 
-#define CONFIG_SYS_FLASH_CFI         1       /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER  1       /* Use the common driver */
-#define CONFIG_SYS_FLASH_PROTECTION  1       /* don't use hardware protection        */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
-#define CONFIG_SYS_MAX_FLASH_BANKS   2       /* max num of flash banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT }
-#define CONFIG_SYS_MAX_FLASH_SECT    128     /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_CFI		1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		1 /* Use the common driver */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* don't use hardware protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2 /* max num of flash banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
+			CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
+#define CONFIG_SYS_MAX_FLASH_SECT	128 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on fli */
 
 /*
  * JFFS2 partitions - second bank contains u-boot
- *
+ * No command line, one static partition, whole device
  */
-/* No command line, one static partition, whole device */
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV		"nor0"
 #define CONFIG_JFFS2_PART_SIZE		0x01b00000
 #define CONFIG_JFFS2_PART_OFFSET	0x00400000
 
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
 /*
+ * mtdparts command line support
+ * Note: fake mtd_id used, no linux mtd map file
+ */
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=pmc405-0"
 #define MTDPARTS_DEFAULT	"mtdparts=pmc405-0:-(jffs2)"
-*/
 
-/*-----------------------------------------------------------------------
+/*
  * Environment Variable setup
  */
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_OFFSET	0x000
+#define CONFIG_ENV_SIZE		0x800 /* 2048 bytes may be used for env vars */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */
 
-/*-----------------------------------------------------------------------
+/*
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 
-/*-----------------------------------------------------------------------
+/*
  * External Bus Controller (EBC) Setup
  */
-#define FLASH0_BA	0xFF000000	    /* FLASH 0 Base Address		*/
-#define FLASH1_BA	0xFE000000	    /* FLASH 1 Base Address		*/
-#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
-#define NVRAM_BA        0xF0200000          /* NVRAM Base Address               */
+#define FLASH0_BA	0xFF000000	/* FLASH 0 Base Address	*/
+#define FLASH1_BA	0xFE000000	/* FLASH 1 Base Address	*/
+#define CAN_BA		0xF0000000	/* CAN Base Addres	*/
+#define RTC_BA		0xF0000500	/* RTC Base Address	*/
+#define NVRAM_BA	0xF0200000	/* NVRAM Base Address	*/
 
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
+/* Memory Bank 0 (Flash Bank 0) initialization */
 #define CONFIG_SYS_EBC_PB0AP	0x92015480
-#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR	(FLASH0_BA | 0x9A000)
 
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
+/* Memory Bank 1 (Flash Bank 1) initialization */
 #define CONFIG_SYS_EBC_PB1AP	0x92015480
-#define CONFIG_SYS_EBC_PB1CR	FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB1CR	(FLASH1_BA | 0x9A000)
 
-/* Memory Bank 2 (CAN0, 1, RTC) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
-#define CONFIG_SYS_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+/* Memory Bank 2 (CAN0, 1, RTC) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CONFIG_SYS_EBC_PB2AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR	(CAN_BA | 0x18000)
 
 /* Memory Bank 3 -> unused */
 
-/* Memory Bank 4 (NVRAM) initialization					*/
-#define CONFIG_SYS_EBC_PB4AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
-#define CONFIG_SYS_EBC_PB4CR	NVRAM_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+/* Memory Bank 4 (NVRAM) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CONFIG_SYS_EBC_PB4AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB4CR	(NVRAM_BA | 0x18000)
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024 /* 32kByte is enough for CPLD */
 
 /* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
-#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */
+#define CONFIG_SYS_FPGA_DATA		0x01000000 /* JTAG TDO pin (output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000 /* unused (ppc input) */
+#define CONFIG_SYS_FPGA_DONE		0x00008000 /* JTAG TDI pin (input) */
 
-#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+/* pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000
 
-/*-----------------------------------------------------------------------
+/*
  * GPIOs
  */
-#define CONFIG_SYS_NONMONARCH		(0x80000000 >> 14)   /* GPIO24 */
-#define CONFIG_SYS_XEREADY		(0x80000000 >> 15)   /* GPIO15 */
-#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 19)   /* GPIO19 */
-#define CONFIG_SYS_SELF_RST		(0x80000000 >> 21)   /* GPIO21 */
-#define CONFIG_SYS_REV1_2		(0x80000000 >> 23)   /* GPIO23 */
+#define CONFIG_SYS_NONMONARCH		(0x80000000 >> 14) /* GPIO14 */
+#define CONFIG_SYS_XEREADY		(0x80000000 >> 15) /* GPIO15 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 19) /* GPIO19 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 21) /* GPIO21 */
+#define CONFIG_SYS_REV1_2		(0x80000000 >> 23) /* GPIO23 */
 
-/*-----------------------------------------------------------------------
+/*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+/* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
+
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_OCM_DATA_SIZE
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -341,7 +336,7 @@
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
 
-#endif	/* __CONFIG_H */
+#endif /* __CONFIG_H */