dts: cadence_spi: Update documentation for DT bindings

Update documentation to reflect adopting the Linux DT bindings.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>

doc/device-tree-bindings/spi/spi-cadence.txt

@@ -6,7 +6,10 @@ Required properties:
 - reg			: 1.Physical base address and size of SPI registers map.
 			  2. Physical base address & size of NOR Flash.
 - clocks		: Clock phandles (see clock bindings for details).
-- sram-size		: spi controller sram size.
+- cdns,fifo-depth	: Size of the data FIFO in words.
+- cdns,fifo-width	: Bus width of the data FIFO in bytes.
+- cdns,trigger-address	: 32-bit indirect AHB trigger address.
+- cdns,is-decoded-cs	: Flag to indicate whether decoder is used or not.
 - status		: enable in requried dts.
 
 connected flash properties
@@ -15,14 +18,14 @@ connected flash properties
 - spi-max-frequency	: Max supported spi frequency.
 - page-size		: Flash page size.
 - block-size		: Flash memory block size.
-- tshsl-ns		: Added delay in master reference clocks (ref_clk) for
+- cdns,tshsl-ns		: Added delay in master reference clocks (ref_clk) for
 			  the length that the master mode chip select outputs
 			  are de-asserted between transactions.
-- tsd2d-ns		: Delay in master reference clocks (ref_clk) between one
+- cdns,tsd2d-ns		: Delay in master reference clocks (ref_clk) between one
 			  chip select being de-activated and the activation of
 			  another.
-- tchsh-ns		: Delay in master reference clocks between last bit of
+- cdns,tchsh-ns		: Delay in master reference clocks between last bit of
 			  current transaction and de-asserting the device chip
 			  select (n_ss_out).
-- tslch-ns		: Delay in master reference clocks between setting
+- cdns,tslch-ns		: Delay in master reference clocks between setting
 			  n_ss_out low and first bit transfer