From 1f553564116f47e4730e1cadbcf9bc24e550cfa6 Mon Sep 17 00:00:00 2001 From: Rajat Srivastava Date: Thu, 22 Mar 2018 13:30:55 +0530 Subject: [PATCH 01/13] spi: fsl_qspi: Introduce is_controller_busy function Some SoCs have different endianness of QSPI IP if compared to endianness of core. The function is_controller_busy() checks if the QSPI controller is busy or not, considering the endianness of the QSPI IP. Signed-off-by: Rajat Srivastava Reviewed-by: York Sun --- drivers/spi/fsl_qspi.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 79781b5..3684249 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -155,6 +155,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val) out_be32(addr, val) : out_le32(addr, val); } +static inline int is_controller_busy(const struct fsl_qspi_priv *priv) +{ + u32 val; + const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK | + QSPI_SR_IP_ACC_MASK; + unsigned int retry = 5; + + do { + val = qspi_read32(priv->flags, &priv->regs->sr); + + if ((~val & mask) == mask) + return 0; + + udelay(1); + } while (--retry); + + return -ETIMEDOUT; +} + /* QSPI support swapping the flash read/write data * in hardware for LS102xA, but not for VF610 */ static inline u32 qspi_endian_xchg(u32 data) @@ -1017,11 +1036,7 @@ static int fsl_qspi_probe(struct udevice *bus) priv->num_chipselect = plat->num_chipselect; /* make sure controller is not busy anywhere */ - ret = wait_for_bit_le32(&priv->regs->sr, - QSPI_SR_BUSY_MASK | - QSPI_SR_AHB_ACC_MASK | - QSPI_SR_IP_ACC_MASK, - false, 100, false); + ret = is_controller_busy(priv); if (ret) { debug("ERROR : The controller is busy\n"); @@ -1184,11 +1199,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev) priv = dev_get_priv(bus); /* make sure controller is not busy anywhere */ - ret = wait_for_bit_le32(&priv->regs->sr, - QSPI_SR_BUSY_MASK | - QSPI_SR_AHB_ACC_MASK | - QSPI_SR_IP_ACC_MASK, - false, 100, false); + ret = is_controller_busy(priv); if (ret) { debug("ERROR : The controller is busy\n"); From f195fad178979020b226671cafec9f9592860174 Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Sat, 24 Mar 2018 02:55:51 +0530 Subject: [PATCH 02/13] mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0 Number of ECC status registers i.e. (ECCSTATx) has been increased in IFC version 2.0.0 due to increase in SRAM size. This is causing eccstat array to over flow. So, replace eccstat array with u32 variable to make it fail-safe and independent of number of ECC status registers or SRAM size. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Jagdish Gediya Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 32 ++++++++++++-------------------- include/fsl_ifc.h | 4 ++-- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index a82913c..3cb4875 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -269,14 +269,9 @@ static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, /* returns nonzero if entire page is blank */ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, - u32 *eccstat, unsigned int bufnum) + u32 eccstat, unsigned int bufnum) { - u32 reg = eccstat[bufnum / 4]; - int errors; - - errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; - - return errors; + return (eccstat >> ((3 - bufnum % 4) * 8)) & 15; } /* @@ -290,7 +285,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; u32 time_start; - u32 eccstat[8] = {0}; + u32 eccstat; int i; /* set the chip select for NAND Transaction */ @@ -320,20 +315,17 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) if (ctrl->eccread) { int errors; int bufnum = ctrl->page & priv->bufnum_mask; - int sector = bufnum * chip->ecc.steps; - int sector_end = sector + chip->ecc.steps - 1; - - for (i = sector / 4; i <= sector_end / 4; i++) { - if (i >= ARRAY_SIZE(eccstat)) { - printf("%s: eccstat too small for %d\n", - __func__, i); - return -EIO; - } + int sector_start = bufnum * chip->ecc.steps; + int sector_end = sector_start + chip->ecc.steps - 1; + u32 *eccstat_regs; - eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); - } + eccstat_regs = ifc->ifc_nand.nand_eccstat; + eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); + + for (i = sector_start; i <= sector_end; i++) { + if ((i != sector_start) && !(i % 4)) + eccstat = ifc_in32(&eccstat_regs[i / 4]); - for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); if (errors == 15) { diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index d051e92..8120ca0 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -891,8 +891,8 @@ struct fsl_ifc_nand { u32 nand_erattr1; u32 res19[0x10]; u32 nand_fsr; - u32 res20[0x3]; - u32 nand_eccstat[6]; + u32 res20[0x1]; + u32 nand_eccstat[8]; u32 res21[0x1c]; u32 nanndcr; u32 res22[0x2]; From bda33d3c6c27b2579f4efdc0ef1d98560314c89d Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Mon, 26 Mar 2018 14:22:43 +0530 Subject: [PATCH 03/13] armv8: layerscape: Avoid code duplication for TZASC Instantiation TZASC controller configurations are similar. Put them in a macro and avoid code duplication. Signed-off-by: Priyanka Jain Signed-off-by: Sriram Dash Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 62 +++++++++++++++------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index e9d373e..ef3987e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -233,39 +233,45 @@ ENTRY(lowlevel_init) * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * placeholders. */ -#ifdef CONFIG_FSL_TZASC_1 - ldr x1, =TZASC_GATE_KEEPER(0) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) - ldr w0, [x1] /* Region-0 Attributes Register */ - orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ - orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ - str w0, [x1] +.macro tzasc_prog, xreg + + mov x12, TZASC1_BASE + mov x16, #0x10000 + mul x14, \xreg, x16 + add x14, x14,x12 + mov x1, #0x8 + add x1, x1, x14 + + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ + orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ + str w0, [x1] + + mov x1, #0x110 + add x1, x1, x14 + + ldr w0, [x1] /* Region-0 Attributes Register */ + orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str w0, [x1] + + mov x1, #0x114 + add x1, x1, x14 + + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] +.endm + +#ifdef CONFIG_FSL_TZASC_1 + mov x13, #0 + tzasc_prog x13 - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] #endif #ifdef CONFIG_FSL_TZASC_2 - ldr x1, =TZASC_GATE_KEEPER(1) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - - ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) - ldr w0, [x1] /* Region-1 Attributes Register */ - orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ - orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ - str w0, [x1] + mov x13, #1 + tzasc_prog x13 - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) - ldr w0, [x1] /* Region-1 Attributes Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] #endif isb dsb sy From 1cb551cf6a18f2b123bcd0c4365d0fedcffdf61b Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Mon, 26 Mar 2018 15:02:41 +0530 Subject: [PATCH 04/13] armv8: ls1088a: Move CONFIG_BOOTARGS and CONFIG_CMD_GREPENV to defconfig Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- configs/ls1088aqds_defconfig | 3 +++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 3 +++ configs/ls1088aqds_qspi_defconfig | 3 +++ configs/ls1088aqds_sdcard_ifc_defconfig | 3 +++ configs/ls1088aqds_sdcard_qspi_defconfig | 3 +++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 3 +++ configs/ls1088ardb_qspi_defconfig | 3 +++ configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 3 +++ configs/ls1088ardb_sdcard_qspi_defconfig | 3 +++ include/configs/ls1088a_common.h | 5 ----- 10 files changed, 27 insertions(+), 5 deletions(-) diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index f20dc3e..05dc2ac 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -8,9 +8,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index be3e098..20376be 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index cea6ca9..cf2b4e3 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 76ee120..39fa3d7 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y @@ -21,6 +23,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index ddb1e04..8d854da 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 23e064b..db95289 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index b05d50a..fbb75df 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 43472ac..17791b0 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -16,6 +16,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,6 +28,7 @@ CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 91fae2c..26966aa 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 0df9016..ea48421 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -148,7 +148,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #endif /* Command line configuration */ -#define CONFIG_CMD_GREPENV #define CONFIG_CMD_CACHE /* Miscellaneous configurable options */ @@ -195,10 +194,6 @@ unsigned long long get_qixis_addr(void); "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500 " \ - "ramdisk_size=0x3000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=256" #if defined(CONFIG_QSPI_BOOT) #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ "sf read 0x80200000 0xd00000 0x100000;"\ From b6bb93de75033d6d52392fff1d3f512b2feeadb6 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Thu, 12 Apr 2018 16:24:35 +0530 Subject: [PATCH 05/13] armv8: sec_firmware: Remove JR3 from device tree node in all cases JR3 was getting removed from device tree only if random number generation was successful. However, if SEC firmware is present, JR3 should be removed from device tree node irrespective of the random seed generation as SEC firmware reserves it for it's use. Not removing it in case of random number generation failure causes the kernel to crash. Random number generation was being called twice. This is not required. If SEC firmware is running, SIP call can be made to the SEC firmware to get the random number. This call itself would return failure if function is not supported. Duplicate calling of random number generation function has been removed. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++-- arch/arm/cpu/armv8/sec_firmware.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4afc046..fc9de73 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -414,8 +414,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ccsr_sec_t __iomem *sec; #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT - if (fdt_fixup_kaslr(blob)) - fdt_fixup_remove_jr(blob); + fdt_fixup_remove_jr(blob); + fdt_fixup_kaslr(blob); #endif sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 6a04eac..5d2d839 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -317,9 +317,7 @@ unsigned int sec_firmware_support_psci_version(void) */ bool sec_firmware_support_hwrng(void) { - uint8_t rand[8]; if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { - if (!sec_firmware_get_random(rand, 8)) return true; } @@ -428,8 +426,10 @@ int fdt_fixup_kaslr(void *fdt) #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) /* Check if random seed generation is supported */ - if (sec_firmware_support_hwrng() == false) + if (sec_firmware_support_hwrng() == false) { + printf("WARNING: SEC firmware not running, no kaslr-seed\n"); return 0; + } ret = sec_firmware_get_random(rand, 8); if (ret < 0) { From 11d5f7d895b2ed6bf511e84aa7c08ddde98e1d33 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Fri, 13 Apr 2018 12:28:45 +0530 Subject: [PATCH 06/13] armv8: ls1088aqds: Enable mdio commands on u-boot prompt Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- board/freescale/ls1088a/eth_ls1088aqds.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 9907fd2..40b1a0e 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -4,12 +4,14 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include #include From 7d3a532d5dd90841ca747a98158b334f4eeb42ef Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Wed, 18 Apr 2018 10:37:24 +0530 Subject: [PATCH 07/13] armv8: ls1088: Update 1900MT/s DDR timing to bring consistency Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- board/freescale/ls1088a/ddr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h index 764ed79..b35c4ae 100644 --- a/board/freescale/ls1088a/ddr.h +++ b/board/freescale/ls1088a/ddr.h @@ -30,12 +30,12 @@ static const struct board_specific_parameters udimm0[] = { #if defined(CONFIG_TARGET_LS1088ARDB) {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,}, {} #elif defined(CONFIG_TARGET_LS1088AQDS) {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, {} From 6a265aba302c924ae686042f5cf363904fe5bc24 Mon Sep 17 00:00:00 2001 From: Takuma Ueba Date: Mon, 23 Apr 2018 13:27:33 +0900 Subject: [PATCH 08/13] powerpc: mpc85xx: Improve Work-around for Erratum A005125 Work-around for Erratum A005125 must be applied to all cores. Signed-off-by: Yoshihisa Morizumi Signed-off-by: Takuma Ueba Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/release.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 5d212f3..d37e1cc 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -26,6 +26,13 @@ .globl __secondary_start_page .align 12 __secondary_start_page: +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + msync + isync + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x0080 + mtspr SPRN_HDBCR0, r3 +#endif /* First do some preliminary setup */ lis r3, HID0_EMCP@h /* enable machine check */ #ifndef CONFIG_E500MC From 8044900a5b97079396049d7e0d1d15b042a0e19a Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Tue, 24 Apr 2018 03:23:28 +0530 Subject: [PATCH 09/13] armv8: sec_firmware: Add support for multiple loadables Enable support for multiple loadable images in SEC firmware FIT image. Also add example "sec_firmware_ppa.its" file. Signed-off-by: Sumit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/sec_firmware.c | 53 +++++++++++++++++++++++++++++-------- doc/uImage.FIT/sec_firmware_ppa.its | 49 ++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 11 deletions(-) create mode 100644 doc/uImage.FIT/sec_firmware_ppa.its diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 5d2d839..a13c92e 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -115,25 +115,48 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img, u32 *loadable_l, u32 *loadable_h) { phys_addr_t sec_firmware_loadable_addr = 0; - int conf_node_off, ld_node_off; + int conf_node_off, ld_node_off, images; char *conf_node_name = NULL; const void *data; size_t size; ulong load; + const char *name, *str, *type; + int len; conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME; conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name); if (conf_node_off < 0) { printf("SEC Firmware: %s: no such config\n", conf_node_name); - return -ENOENT; + return -ENOENT; + } + + /* find the node holding the images information */ + images = fdt_path_offset(sec_firmware_img, FIT_IMAGES_PATH); + if (images < 0) { + printf("%s: Cannot find /images node: %d\n", __func__, images); + return -1; + } + + type = FIT_LOADABLE_PROP; + + name = fdt_getprop(sec_firmware_img, conf_node_off, type, &len); + if (!name) { + /* Loadables not present */ + return 0; } - ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off, - FIT_LOADABLE_PROP); - if (ld_node_off >= 0) { - printf("SEC Firmware: '%s' present in config\n", - FIT_LOADABLE_PROP); + printf("SEC Firmware: '%s' present in config\n", type); + + for (str = name; str && ((str - name) < len); + str = strchr(str, '\0') + 1) { + printf("%s: '%s'\n", type, str); + ld_node_off = fdt_subnode_offset(sec_firmware_img, images, str); + if (ld_node_off < 0) { + printf("cannot find image node '%s': %d\n", str, + ld_node_off); + return -EINVAL; + } /* Verify secure firmware image */ if (!(fit_image_verify(sec_firmware_img, ld_node_off))) { @@ -163,11 +186,19 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img, memcpy((void *)sec_firmware_loadable_addr, data, size); flush_dcache_range(sec_firmware_loadable_addr, sec_firmware_loadable_addr + size); - } - /* Populate address ptrs for loadable image with loadbale addr */ - out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK)); - out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT)); + /* Populate loadable address only for Trusted OS */ + if (!strcmp(str, "trustedOS@1")) { + /* + * Populate address ptrs for loadable image with + * loadbale addr + */ + out_le32(loadable_l, (sec_firmware_loadable_addr & + WORD_MASK)); + out_le32(loadable_h, (sec_firmware_loadable_addr >> + WORD_SHIFT)); + } + } return 0; } diff --git a/doc/uImage.FIT/sec_firmware_ppa.its b/doc/uImage.FIT/sec_firmware_ppa.its new file mode 100644 index 0000000..a7acde1 --- /dev/null +++ b/doc/uImage.FIT/sec_firmware_ppa.its @@ -0,0 +1,49 @@ +/dts-v1/; + +/* + * Example FIT image description file demonstrating the usage + * of SEC Firmware and multiple loadable images loaded by the u-boot. + * For booting PPA (SEC Firmware), "firmware" is searched and loaded. + * + * Multiple binaries will be loaded as "loadables" (if present) at their + * respective load offsets from firmware image address. + */ + +/{ + description = "PPA Firmware"; + #address-cells = <1>; + images { + firmware@1 { + description = "PPA Firmware: "; + data = /incbin/("../obj/monitor.bin"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + }; + trustedOS@1 { + description = "Trusted OS"; + data = /incbin/("../../tee.bin"); + type = "OS"; + arch = "arm64"; + compression = "none"; + load = <0x00200000>; + }; + fuse_scr { + description = "Fuse Script"; + data = /incbin/("../../fuse_scr.bin"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x00180000>; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "PPA Secure firmware"; + firmware = "firmware@1"; + loadables = "trustedOS@1", "fuse_scr"; + }; + }; +}; From 945fad57be827482091c6d39443d51052c7a8d7d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 25 Apr 2018 16:28:44 +0800 Subject: [PATCH 10/13] armv8/fsl-lsch2: correct QMAN clock Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7edc06d..546de33 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -469,6 +469,14 @@ config SYS_FSL_SDHC_CLK_DIV help This is the divider that is used to derive SDHC clock from Platform clock, in another word SDHC_clk = Platform_clk / this_divider. + +config SYS_FSL_QMAN_CLK_DIV + int "QMAN clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive QMAN clock from Platform + clock, in another word QMAN_clk = Platform_clk / this_divider. endmenu config RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8386678..723d7ea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -155,7 +155,9 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sys_info->freq_qman = sys_info->freq_systembus; + sys_info->freq_qman = (sys_info->freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_QMAN_CLK_DIV; #endif } From 8b40f22900f3618ab1b83d15d078ab6f75c7c800 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 25 Apr 2018 14:25:42 +0800 Subject: [PATCH 11/13] armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust Mask HRESET_B after cleared the the RCW_SRC, because in the workaround we override the RCW_SRC and if HRESET_B is issued after the override then SoC cannot find valid RCW as the RCW_SRC was overwritten and result in hang. So we need to mask HRESET_B in case user asserts it, and the PORESET_B should be asserted which leads to resampling of cfg_rcw_src pins and loading of correct RCW_SRC. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06fdd17..bfd6639 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -517,6 +517,7 @@ static void erratum_a010539(void) porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); + out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif } From e8c669a3e6ec9b33aea55e957024f97300b99c1c Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Wed, 2 May 2018 01:20:57 +0530 Subject: [PATCH 12/13] mtd: nand: fsl_ifc: Fix nand waitfunc return value As per the IFC hardware manual, Most significant byte in nand_fsr register is the outcome of NAND READ STATUS command. So status value need to be shifted as per the nand framework requirement. Signed-off-by: Jagdish Gediya Reviewed-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 3cb4875..a47226b 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -700,6 +700,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; u32 nand_fsr; + int status; if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; @@ -720,10 +721,10 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); + status = nand_fsr >> 24; /* Chip sometimes reporting write protect even when it's not */ - nand_fsr = nand_fsr | NAND_STATUS_WP; - return nand_fsr; + return status | NAND_STATUS_WP; } static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, From a6f2a6eafe0e5ad71c41341219ae3b187c1f738a Mon Sep 17 00:00:00 2001 From: Yogesh Gaur Date: Wed, 9 May 2018 10:52:17 +0530 Subject: [PATCH 13/13] driver: net: fsl-mc: updated copyright info Updated copyright info for the issues reported after running check-legal test. Signed-off-by: Yogesh Gaur Reviewed-by: York Sun --- drivers/net/fsl-mc/dpbp.c | 2 +- drivers/net/fsl-mc/dpio/dpio.c | 2 +- drivers/net/fsl-mc/dpmac.c | 2 +- drivers/net/fsl-mc/dpni.c | 2 +- drivers/net/fsl-mc/dprc.c | 2 +- drivers/net/fsl-mc/fsl_dpmng_cmd.h | 2 +- drivers/net/fsl-mc/mc.c | 4 ++-- drivers/net/ldpaa_eth/ldpaa_eth.c | 2 +- drivers/net/ldpaa_eth/ldpaa_eth.h | 2 +- include/fsl-mc/fsl_dpbp.h | 2 +- include/fsl-mc/fsl_dpio.h | 2 +- include/fsl-mc/fsl_dpmac.h | 2 +- include/fsl-mc/fsl_dpni.h | 2 +- include/fsl-mc/fsl_dprc.h | 2 +- include/fsl-mc/fsl_mc_cmd.h | 2 +- include/fsl-mc/fsl_mc_private.h | 2 +- 16 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c index 327bee9..c609efb 100644 --- a/drivers/net/fsl-mc/dpbp.c +++ b/drivers/net/fsl-mc/dpbp.c @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #include diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index 0bbb760..8884455 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c index 2aadd4a..43a2ff4 100644 --- a/drivers/net/fsl-mc/dpmac.c +++ b/drivers/net/fsl-mc/dpmac.c @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * Author: Prabhakar Kushwaha */ diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 5cf5eeb..443e430 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index 38d19a4..e0a2865 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h index 9e6f27a..e18c88d 100644 --- a/drivers/net/fsl-mc/fsl_dpmng_cmd.h +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright 2013-2016 Freescale Semiconductor Inc. +/* Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #ifndef __FSL_DPMNG_CMD_H diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 58612cf..982024e 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 NXP Semiconductors - * Copyright (C) 2014 Freescale Semiconductor + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #include #include diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 8688dd4..79facb4 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index 54cb633..ee784a5 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 8d7c14d..2278ac9 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ /*! diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index c300c94..7788e19 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 66cf3bf..1cea123 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * Author: Prabhakar Kushwaha */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 309d323..96d81d9 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #ifndef _FSL_DPNI_H diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 779d6f9..950ecb0 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -2,7 +2,7 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #ifndef _FSL_DPRC_H diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 179f669..591cda9 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright 2013-2016 Freescale Semiconductor Inc. +/* Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #ifndef __FSL_MC_CMD_H diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h index f4b5a99..ba0bc37 100644 --- a/include/fsl-mc/fsl_mc_private.h +++ b/include/fsl-mc/fsl_mc_private.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */