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Added initial eNET board support

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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
master
Graeme Russ 16 years ago committed by Wolfgang Denk
parent 0c0ccf401e
commit c620c01e96
10 changed files with 766 additions and 0 deletions
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  1. 1
      MAKEALL
  2. 3
      Makefile
  3. 57
      board/eNET/Makefile
  4. 24
      board/eNET/config.mk
  5. 167
      board/eNET/eNET.c
  6. 50
      board/eNET/eNET_start.S
  7. 90
      board/eNET/eNET_start16.S
  8. 35
      board/eNET/hardware.h
  9. 90
      board/eNET/u-boot.lds
  10. 249
      include/configs/eNET.h

1
MAKEALL
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@ -659,6 +659,7 @@ LIST_mips_el=" \
LIST_I486=" \
sc520_cdp \
sc520_eNET \
sc520_spunk \
sc520_spunk_rel \
"

3
Makefile
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@ -2996,6 +2996,9 @@ smdk6400_config : unconfig
sc520_cdp_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp
eNET_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 eNET
sc520_spunk_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk

57
board/eNET/Makefile
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@ -0,0 +1,57 @@
#
# (C) Copyright 2008
# Graeme Russ, graeme.russ@gmail.com.
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := eNET.o
SOBJS := eNET_start16.o eNET_start.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/eNET/config.mk
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@ -0,0 +1,24 @@
#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x38040000

167
board/eNET/eNET.c
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@ -0,0 +1,167 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/ic/sc520.h>
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif
#include "hardware.h"
DECLARE_GLOBAL_DATA_PTR;
#undef SC520_CDP_DEBUG
#ifdef SC520_CDP_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void init_sc520_enet (void)
{
/* Set CPU Speed to 100MHz */
write_mmcr_byte(SC520_CPUCTL, 1);
gd->cpu_clk = 100000000;
/* wait at least one millisecond */
asm("movl $0x2000,%%ecx\n"
"wait_loop: pushl %%ecx\n"
"popl %%ecx\n"
"loop wait_loop\n": : : "ecx");
/* turn on the SDRAM write buffer */
write_mmcr_byte(SC520_DBCTL, 0x11);
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
"andl $0x9fffffff, %%eax\n"
"movl %%eax, %%cr0\n" : : : "eax");
}
/*
* Miscellaneous platform dependent initializations
*/
int board_init(void)
{
init_sc520_enet();
write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */
write_mmcr_word(0x0cb0, 0x3333);
write_mmcr_word(0x0cb0, 0xcccc);
write_mmcr_word(0x0cb0, 0x0000);
/* Chip Select Configuration */
write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
write_mmcr_byte(SC520_ADDDECCTL, 0x02);
write_mmcr_byte(SC520_UART1CTL, 0x07);
write_mmcr_byte(SC520_SYSARBCTL,0x06);
write_mmcr_word(SC520_SYSARBMENB, 0x0003);
/* Crystal is 33.000MHz */
gd->bus_clk = 33000000;
return 0;
}
int dram_init(void)
{
init_sc520_dram();
return 0;
}
void show_boot_progress(int val)
{
uchar led_mask;
led_mask = 0x00;
if (val < 0)
led_mask |= LED_ERR_BITMASK;
led_mask |= (uchar)(val & 0x001f);
outb(led_mask, LED_LATCH_ADDRESS);
}
int last_stage_init(void)
{
int minor;
int major;
major = minor = 0;
printf("Serck Controls eNET\n");
return 0;
}
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
} else
return 0;
}

50
board/eNET/eNET_start.S
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@ -0,0 +1,50 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "hardware.h"
/* board early intialization */
.globl early_board_init
early_board_init:
/* No 32-bit board specific initialisation */
jmp *%ebp /* return to caller */
.globl show_boot_progress_asm
show_boot_progress_asm:
movb %al, %dl /* Create Working Copy */
andb $0x80, %dl /* Mask in only Error bit */
shrb $0x02, %dl /* Shift Error bit to Error LED */
andb $0x0f, %al /* Mask out 'Error' bit */
orb %dl, %al /* Mask in ERR LED */
movw $LED_LATCH_ADDRESS, %dx
outb %al, %dx
jmp *%ebp /* return to caller */
.globl cpu_halt_asm
cpu_halt_asm:
movb $0x0f, %al
movw $LED_LATCH_ADDRESS, %dx
outb %al, %dx
hlt
jmp cpu_halt_asm

90
board/eNET/eNET_start16.S
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@ -0,0 +1,90 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* 16bit initialization code.
* This code have to map the area of the boot flash
* that is used by U-boot to its final destination.
*/
/* #include <asm/ic/sc520_defs.h> */
#include "hardware.h"
.text
.section .start16, "ax"
.code16
.globl board_init16
board_init16:
/* Alias MMCR to 0xdf000 */
movw $0xfffc, %dx
movl $0x800df0cb, %eax
outl %eax, %dx
/* Set ds to point to MMCR alias */
movw $0xdf00, %ax
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
movl $0x00c0, %edi /* SC520_PAR14 */
movl $0x8bfff800, %eax /* TODO: Check this */
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
movl $0x00c4, %edi /* SC520_PAR15 */
movl $0x38201000, %eax
movl %eax, (%di)
/* Disable SDRAM write buffer */
movw $0x0040, %di /* SC520_DBCTL */
xorw %ax, %ax
movb %al, (%di)
/* Disabe MMCR alias */
movw $0xfffc, %dx
movl $0x000000cb, %eax
outl %eax, %dx
/* the return address is stored in bp */
jmp *%bp
.section .bios, "ax"
.code16
.globl realmode_reset
realmode_reset:
/* Alias MMCR to 0xdf000 */
movw $0xfffc, %dx
movl $0x800df0cb, %eax
outl %eax, %dx
/* Set ds to point to MMCR alias */
movw $0xdf00, %ax
movw %ax, %ds
/* issue software reset thorugh MMCR */
movl $0xd72, %edi
movb $0x01, %al
movb %al, (%di)
1: hlt
jmp 1

35
board/eNET/hardware.h
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/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef HARDWARE_H_
#define HARDWARE_H_
#define LED_LATCH_ADDRESS 0x1002
#define LED_RUN_BITMASK 0x01
#define LED_1_BITMASK 0x02
#define LED_2_BITMASK 0x04
#define LED_RX_BITMASK 0x08
#define LED_TX_BITMASK 0x10
#define LED_ERR_BITMASK 0x20
#endif /* HARDWARE_H_ */

90
board/eNET/u-boot.lds
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/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
ENTRY(_start)
SECTIONS
{
. = 0x38040000; /* Location of bootcode in flash */
.text : { *(.text); }
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
_i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
. = 0x03FF0000; /* Ram data segment to use */
_i386boot_romdata_dest = ABSOLUTE(.);
.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
_i386boot_romdata_start = LOADADDR(.data);
. = ALIGN(4);
.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_i386boot_cmd_start = LOADADDR(.u_boot_cmd);
_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
. = ALIGN(4);
_i386boot_bss_start = ABSOLUTE(.);
.bss (NOLOAD) : { *(.bss) }
_i386boot_bss_size = SIZEOF(.bss);
/* 16bit realmode trampoline code */
.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
_i386boot_realmode = LOADADDR(.realmode);
_i386boot_realmode_size = SIZEOF(.realmode);
/* 16bit BIOS emulation code (just enough to boot Linux) */
.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
_i386boot_bios = LOADADDR(.bios);
_i386boot_bios_size = SIZEOF(.bios);
/* The load addresses below assumes that the flash
* will be mapped so that 0x387f0000 == 0xffff0000
* at reset time
*
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
* The fff0 offset of reset is important, however.
*/
. = 0xfffffe00;
.start32 : AT (0x3807fe00) { *(.start32); }
. = 0xf800;
.start16 : AT (0x3807f800) { *(.start16); }
. = 0xfff0;
.reset : AT (0x3807fff0) { *(.reset); }
_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
}

249
include/configs/eNET.h
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/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Stuff still to be dealt with -
*/
#define CONFIG_RTC_MC146818
/*
* High Level Configuration Options
* (easy to change)
*/
#define DEBUG_PARSER
#define CONFIG_X86 1 /* Intel X86 CPU */
#define CONFIG_SC520 1 /* AMD SC520 */
#define CONFIG_SC520_SSI
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_LAST_STAGE_INIT 1
/*
* If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
* bottom (processor) board MUST be removed!
*/
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
/*-----------------------------------------------------------------------
* Video Configuration
*/
#undef CONFIG_VIDEO /* No Video Hardware */
#undef CONFIG_CFB_CONSOLE
/*
* Size of malloc() pool
*/
#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
/*-----------------------------------------------------------------------
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#undef CONFIG_CMD_IRQ /* IRQ Information */
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* SDRAM Configuration
*/
#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
#define CONFIG_NR_DRAM_BANKS 4
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
#undef CONFIG_SYS_SDRAM_REFRESH_RATE
#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
/*-----------------------------------------------------------------------
* CPU Features
*/
#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
#define CONFIG_SYS_RESET_GENERIC /* use triple-fault to reset cpu */
#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */
#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */
#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
* in the SC520 on the CDP */
/*-----------------------------------------------------------------------
* Memory organization
*/
#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* FLASH configuration
*/
#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_FLASH_BASE_1, \
CONFIG_SYS_FLASH_BASE_2}
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
/*-----------------------------------------------------------------------
* Environment configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \
CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*-----------------------------------------------------------------------
* PCI configuration
*/
#undef CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* pci plug-and-play */
#undef CONFIG_PCI_SCAN_SHOW
#undef CONFIG_SYS_FIRST_PCI_IRQ
#undef CONFIG_SYS_SECOND_PCI_IRQ
#undef CONFIG_SYS_THIRD_PCI_IRQ
#undef CONFIG_SYS_FORTH_PCI_IRQ
/*-----------------------------------------------------------------------
* Hardware watchdog configuration
*/
#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
/*-----------------------------------------------------------------------
* FPGA configuration
*/
#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
#ifndef __ASSEMBLER__
extern unsigned long ip;
#define PRINTIP asm ("call next_line\n" \
"next_line:\n" \
"pop %%eax\n" \
"movl %%eax, %0\n" \
:"=r"(ip) \
: /* No Input Registers */ \
:"%eax"); \
printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
#endif
#endif /* __CONFIG_H */
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