This adds initial support for the RTE RSK+ SH7203 board. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
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#
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# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
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# Copyright (C) 2008 Renesas Solutions Corp.
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#
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# u-boot/board/rsk7203/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := rsk7203.o
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SOBJS := lowlevel_init.o
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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#
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# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
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# Copyright (C) 2008 Renesas Solutions Corp.
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#
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# u-boot/board/rsk7203/config.mk
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# TEXT_BASE refers to image _after_ relocation.
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x0C7C0000
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@ -0,0 +1,265 @@ |
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/* |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/processor.h> |
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.global lowlevel_init
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.text |
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.align 2
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lowlevel_init: |
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/* Cache setting */ |
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mov.l CCR1_A ,r1 |
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mov.l CCR1_D ,r0 |
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mov.l r0,@r1
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/* ConfigurePortPins */ |
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mov.l PECRL3_A, r1 |
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mov.l PECRL3_D, r0 |
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mov.w r0,@r1
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mov.l PCCRL4_A, r1 |
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mov.l PCCRL4_D0, r0 |
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mov.w r0,@r1
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mov.l PECRL4_A, r1 |
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mov.l PECRL4_D0, r0 |
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mov.w r0,@r1
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mov.l PEIORL_A, r1 |
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mov.l PEIORL_D0, r0 |
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mov.w r0,@r1
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mov.l PCIORL_A, r1 |
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mov.l PCIORL_D, r0 |
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mov.w r0,@r1
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mov.l PFCRH2_A, r1 |
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mov.l PFCRH2_D, r0 |
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mov.w r0,@r1
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mov.l PFCRH3_A, r1 |
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mov.l PFCRH3_D, r0 |
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mov.w r0,@r1
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mov.l PFCRH1_A, r1 |
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mov.l PFCRH1_D, r0 |
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mov.w r0,@r1
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mov.l PFIORH_A, r1 |
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mov.l PFIORH_D, r0 |
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mov.w r0,@r1
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mov.l PECRL1_A, r1 |
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mov.l PECRL1_D0, r0 |
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mov.w r0,@r1
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mov.l PEIORL_A, r1 |
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mov.l PEIORL_D1, r0 |
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mov.w r0,@r1
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/* Configure Operating Frequency */ |
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mov.l WTCSR_A ,r1 |
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mov.l WTCSR_D0 ,r0 |
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mov.w r0,@r1
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mov.l WTCSR_A ,r1 |
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mov.l WTCSR_D1 ,r0 |
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mov.w r0,@r1
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mov.l WTCNT_A ,r1 |
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mov.l WTCNT_D ,r0 |
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mov.w r0,@r1
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/* Set clock mode*/ |
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mov.l FRQCR_A,r1 |
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mov.l FRQCR_D,r0 |
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mov.w r0,@r1
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/* Configure Bus And Memory */ |
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init_bsc_cs0: |
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mov.l PCCRL4_A,r1 |
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mov.l PCCRL4_D1,r0 |
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mov.w r0,@r1
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mov.l PECRL1_A,r1 |
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mov.l PECRL1_D1,r0 |
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mov.w r0,@r1
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mov.l CMNCR_A,r1 |
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mov.l CMNCR_D,r0 |
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mov.l r0,@r1
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mov.l SC0BCR_A,r1 |
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mov.l SC0BCR_D,r0 |
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mov.l r0,@r1
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mov.l CS0WCR_A,r1 |
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mov.l CS0WCR_D,r0 |
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mov.l r0,@r1
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init_bsc_cs1: |
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mov.l PECRL4_A,r1 |
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mov.l PECRL4_D1,r0 |
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mov.w r0,@r1
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mov.l CS1WCR_A,r1 |
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mov.l CS1WCR_D,r0 |
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mov.l r0,@r1
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init_sdram: |
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mov.l PCCRL2_A,r1 |
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mov.l PCCRL2_D,r0 |
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mov.w r0,@r1
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mov.l PCCRL4_A,r1 |
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mov.l PCCRL4_D2,r0 |
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mov.w r0,@r1
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mov.l PCCRL1_A,r1 |
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mov.l PCCRL1_D,r0 |
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mov.w r0,@r1
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mov.l PCCRL3_A,r1 |
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mov.l PCCRL3_D,r0 |
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mov.w r0,@r1
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mov.l CS3BCR_A,r1 |
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mov.l CS3BCR_D,r0 |
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mov.l r0,@r1
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mov.l CS3WCR_A,r1 |
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mov.l CS3WCR_D,r0 |
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mov.l r0,@r1
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mov.l SDCR_A,r1 |
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mov.l SDCR_D,r0 |
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mov.l r0,@r1
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mov.l RTCOR_A,r1 |
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mov.l RTCOR_D,r0 |
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mov.l r0,@r1
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mov.l RTCSR_A,r1 |
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mov.l RTCSR_D,r0 |
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mov.l r0,@r1
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/* wait 200us */ |
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mov.l REPEAT_D,r3 |
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mov #0,r2 |
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repeat0: |
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add #1,r2 |
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cmp/hs r3,r2 |
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bf repeat0 |
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nop |
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mov.l SDRAM_MODE, r1 |
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mov #0,r0 |
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mov.l r0, @r1
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nop |
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rts |
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.align 4
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CCR1_A: .long CCR1 |
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CCR1_D: .long 0x0000090B |
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PCCRL4_A: .long 0xFFFE3910 |
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PCCRL4_D0: .long 0x00000000 |
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PECRL4_A: .long 0xFFFE3A10 |
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PECRL4_D0: .long 0x00000000 |
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PECRL3_A: .long 0xFFFE3A12 |
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PECRL3_D: .long 0x00000000 |
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PEIORL_A: .long 0xFFFE3A06 |
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PEIORL_D0: .long 0x00001C00 |
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PEIORL_D1: .long 0x00001C02 |
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PCIORL_A: .long 0xFFFE3906 |
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PCIORL_D: .long 0x00004000 |
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PFCRH2_A: .long 0xFFFE3A8C |
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PFCRH2_D: .long 0x00000000 |
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PFCRH3_A: .long 0xFFFE3A8A |
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PFCRH3_D: .long 0x00000000 |
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PFCRH1_A: .long 0xFFFE3A8E |
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PFCRH1_D: .long 0x00000000 |
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PFIORH_A: .long 0xFFFE3A84 |
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PFIORH_D: .long 0x00000729 |
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PECRL1_A: .long 0xFFFE3A16 |
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PECRL1_D0: .long 0x00000033 |
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WTCSR_A: .long 0xFFFE0000 |
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WTCSR_D0: .long 0x0000A518 |
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WTCSR_D1: .long 0x0000A51D |
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WTCNT_A: .long 0xFFFE0002 |
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WTCNT_D: .long 0x00005A84 |
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FRQCR_A: .long 0xFFFE0010 |
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FRQCR_D: .long 0x00000104 |
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PCCRL4_D1: .long 0x00000010 |
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PECRL1_D1: .long 0x00000133 |
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CMNCR_A: .long 0xFFFC0000 |
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CMNCR_D: .long 0x00001810 |
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SC0BCR_A: .long 0xFFFC0004 |
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SC0BCR_D: .long 0x10000400 |
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CS0WCR_A: .long 0xFFFC0028 |
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CS0WCR_D: .long 0x00000B41 |
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PECRL4_D1: .long 0x00000100 |
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CS1WCR_A: .long 0xFFFC002C |
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CS1WCR_D: .long 0x00000B01 |
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PCCRL4_D2: .long 0x00000011 |
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PCCRL3_A: .long 0xFFFE3912 |
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PCCRL3_D: .long 0x00000011 |
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PCCRL2_A: .long 0xFFFE3914 |
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PCCRL2_D: .long 0x00001111 |
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PCCRL1_A: .long 0xFFFE3916 |
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PCCRL1_D: .long 0x00001010 |
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PDCRL4_A: .long 0xFFFE3990 |
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PDCRL4_D: .long 0x00000011 |
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PDCRL3_A: .long 0xFFFE3992 |
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PDCRL3_D: .long 0x00000011 |
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PDCRL2_A: .long 0xFFFE3994 |
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PDCRL2_D: .long 0x00001111 |
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PDCRL1_A: .long 0xFFFE3996 |
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PDCRL1_D: .long 0x00001000 |
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CS3BCR_A: .long 0xFFFC0010 |
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CS3BCR_D: .long 0x00004400 |
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CS3WCR_A: .long 0xFFFC0034 |
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CS3WCR_D: .long 0x00002892 |
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SDCR_A: .long 0xFFFC004C |
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SDCR_D: .long 0x00000809 |
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RTCOR_A: .long 0xFFFC0058 |
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RTCOR_D: .long 0xA55A0041 |
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RTCSR_A: .long 0xFFFC0050 |
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RTCSR_D: .long 0xa55a0010 |
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STBCR3_A: .long 0xFFFE0408 |
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STBCR3_D: .long 0x00000000 |
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STBCR4_A: .long 0xFFFE040C |
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STBCR4_D: .long 0x00000008 |
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STBCR5_A: .long 0xFFFE0410 |
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STBCR5_D: .long 0x00000000 |
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STBCR6_A: .long 0xFFFE0414 |
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STBCR6_D: .long 0x00000002 |
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SDRAM_MODE: .long 0xFFFC5040 |
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REPEAT_D: .long 0x00009C40 |
@ -0,0 +1,50 @@ |
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/*
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* u-boot/board/rsk7203/rsk7203.c |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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int checkboard(void) |
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{ |
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puts("BOARD: Renesas Technology RSK7203\n"); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gd->bd->bi_memstart = CFG_SDRAM_BASE; |
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gd->bd->bi_memsize = CFG_SDRAM_SIZE; |
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printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); |
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return 0; |
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} |
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void led_set_state(unsigned short value) |
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{ |
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} |
@ -0,0 +1,101 @@ |
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/* |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") |
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OUTPUT_ARCH(sh) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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/* |
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* Base address of internal SDRAM is 0x0C000000. |
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* |
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* NOTE: This address must match with the definition of |
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*TEXT_BASE in config.mk (in this directory). |
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*/ |
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. = 0x0C000000 + (8*1024*1024) - (256*1024); |
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PROVIDE (reloc_dst = .); |
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PROVIDE (_ftext = .); |
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PROVIDE (_fcode = .); |
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PROVIDE (_start = .); |
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.text : |
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{ |
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cpu/sh2/start.o (.text) |
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. = ALIGN(8192); |
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common/environment.o (.ppcenv) |
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. = ALIGN(8192); |
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common/environment.o (.ppcenvr) |
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. = ALIGN(8192); |
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*(.text) |
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. = ALIGN(4); |
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} =0xFF |
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PROVIDE (_ecode = .); |
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.rodata : |
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{ |
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*(.rodata) |
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. = ALIGN(4); |
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} |
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PROVIDE (_etext = .); |
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PROVIDE (_fdata = .); |
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.data : |
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{ |
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*(.data) |
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. = ALIGN(4); |
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} |
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PROVIDE (_edata = .); |
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PROVIDE (_fgot = .); |
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.got : |
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{ |
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*(.got) |
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. = ALIGN(4); |
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} |
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PROVIDE (_egot = .); |
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PROVIDE (__u_boot_cmd_start = .); |
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.u_boot_cmd : |
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{ |
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*(.u_boot_cmd) |
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. = ALIGN(4); |
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} |
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PROVIDE (__u_boot_cmd_end = .); |
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PROVIDE (reloc_dst_end = .); |
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PROVIDE (bss_start = .); |
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PROVIDE (__bss_start = .); |
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.bss : |
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{ |
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*(.bss) |
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. = ALIGN(4); |
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} |
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PROVIDE (bss_end = .); |
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PROVIDE (_end = .); |
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} |
@ -0,0 +1,107 @@ |
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/*
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* Configuation settings for the Renesas Technology RSK 7203 |
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* |
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* Copyright (C) 2008 Nobuhiro Iwamatsu |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __RSK7203_H |
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#define __RSK7203_H |
||||
|
||||
#undef DEBUG |
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#define CONFIG_SH 1 |
||||
#define CONFIG_SH2 1 |
||||
#define CONFIG_SH2A 1 |
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#define CONFIG_CPU_SH7203 1 |
||||
#define CONFIG_RSK7203 1 |
||||
|
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_CACHE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTARGS "console=ttySC0,115200" |
||||
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ |
||||
|
||||
#define CONFIG_VERSION_VARIABLE |
||||
#undef CONFIG_SHOW_BOOT_PROGRESS |
||||
|
||||
/* MEMORY */ |
||||
#define RSK7203_SDRAM_BASE 0x0C000000 |
||||
#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */ |
||||
#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024) |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ |
||||
#define CFG_PBSIZE 256 /* Buffer size for Console output */ |
||||
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ |
||||
/* Buffer size for Boot Arguments passed to kernel */ |
||||
#define CFG_BARGSIZE 512 |
||||
/* List of legal baudrate settings for this board */ |
||||
#define CFG_BAUDRATE_TABLE { 115200 } |
||||
|
||||
/* SCIF */ |
||||
#define CFG_SCIF_CONSOLE 1 |
||||
#define CONFIG_CONS_SCIF0 1 |
||||
|
||||
#define CFG_MEMTEST_START RSK7203_SDRAM_BASE |
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (3 * 1024 * 1024)) |
||||
|
||||
#define CFG_SDRAM_BASE RSK7203_SDRAM_BASE |
||||
#define CFG_SDRAM_SIZE (32 * 1024 * 1024) |
||||
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 1024 * 1024) |
||||
#define CFG_MONITOR_BASE RSK7203_FLASH_BASE_1 |
||||
#define CFG_MONITOR_LEN (128 * 1024) |
||||
#define CFG_MALLOC_LEN (256 * 1024) |
||||
#define CFG_GBL_DATA_SIZE 256 |
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024) |
||||
|
||||
/* FLASH */ |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#undef CFG_FLASH_QUIET_TEST |
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_BASE RSK7203_FLASH_BASE_1 |
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
#define CFG_MAX_FLASH_SECT 64 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE (64 * 1024) |
||||
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
||||
#define CFG_FLASH_ERASE_TOUT 12000 |
||||
#define CFG_FLASH_WRITE_TOUT 500 |
||||
|
||||
/* Board Clock */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ |
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) |
||||
|
||||
#endif /* __RSK7203_H */ |
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Reference in new issue