This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>master
Masahiro Yamada
9 years ago
committed by
Tom Rini
parent
8fe11b8901
commit
c6999e5f85
@ -1,12 +0,0 @@ |
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if TARGET_P3P440 |
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|
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config SYS_BOARD |
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default "p3p440" |
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config SYS_VENDOR |
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default "prodrive" |
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config SYS_CONFIG_NAME |
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default "p3p440" |
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endif |
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@ -1,6 +0,0 @@ |
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P3P440 BOARD |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/prodrive/p3p440/ |
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F: include/configs/p3p440.h |
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F: configs/p3p440_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = p3p440.o
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extra-y += init.o
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@ -1,16 +0,0 @@ |
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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@ -1,38 +0,0 @@ |
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/* |
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* (C) Copyright 2005 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <asm/mmu.h> |
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#include <config.h> |
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#include <asm/ppc4xx.h> |
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|
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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.globl tlbtab
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tlbtab: |
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tlbtab_start |
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tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
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tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
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tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX ) |
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tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX ) |
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) |
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tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) |
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tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) |
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tlbtab_end |
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@ -1,177 +0,0 @@ |
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/*
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* (C) Copyright 2005 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <command.h> |
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#include "p3p440.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void set_led(int color) |
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{ |
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switch (color) { |
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case LED_OFF: |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED); |
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break; |
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case LED_GREEN: |
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out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED); |
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break; |
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case LED_RED: |
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out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN); |
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break; |
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case LED_ORANGE: |
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out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED); |
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break; |
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} |
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} |
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static int is_monarch(void) |
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{ |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY); |
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udelay(1000); |
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if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO) |
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return 0; |
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else |
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return 1; |
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} |
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static void wait_for_pci_ready(void) |
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{ |
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/*
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* Configure EREADY_IO as input |
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*/ |
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO); |
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udelay(1000); |
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for (;;) { |
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if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO) |
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return; |
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} |
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} |
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int board_early_init_f(void) |
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{ |
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uint reg; |
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects |
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*-------------------------------------------------------------------*/ |
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mtdcr(EBC0_CFGADDR, EBC0_CFG); |
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reg = mfdcr(EBC0_CFGDATA); |
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mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ |
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/*--------------------------------------------------------------------
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* Setup pin multiplexing (GPIO/IRQ...) |
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*-------------------------------------------------------------------*/ |
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mtdcr(CPC0_GPIO, 0x03F01F80); |
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ |
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out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); |
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out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY); |
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc. |
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*-------------------------------------------------------------------*/ |
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mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC0ER, 0x00000000); /* disable all */ |
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mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ |
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mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ |
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mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ |
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mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
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mtdcr(UIC1ER, 0x00000000); /* disable all */ |
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */ |
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mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ |
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mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ |
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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char buf[64]; |
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int i = getenv_f("serial#", buf, sizeof(buf)); |
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printf("Board: P3P440"); |
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if (i > 0) { |
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puts(", serial# "); |
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puts(buf); |
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} |
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if (is_monarch()) { |
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puts(", Monarch"); |
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} else { |
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puts(", None-Monarch"); |
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} |
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putc('\n'); |
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return (0); |
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} |
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int misc_init_r (void) |
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{ |
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/*
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* Adjust flash start and offset to detected values |
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*/ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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/*
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* Check if only one FLASH bank is available |
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*/ |
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if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { |
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mtebc(PB1CR, 0); /* disable cs */ |
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mtebc(PB1AP, 0); |
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mtebc(PB2CR, 0); /* disable cs */ |
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mtebc(PB2AP, 0); |
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mtebc(PB3CR, 0); /* disable cs */ |
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mtebc(PB3AP, 0); |
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} |
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return 0; |
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} |
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/*************************************************************************
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* Override weak is_pci_host() |
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* |
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* This routine is called to determine if a pci scan should be |
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* performed. With various hardware environments (especially cPCI and |
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* PPMC) it's insufficient to depend on the state of the arbiter enable |
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* bit in the strap register, or generic host/adapter assumptions. |
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* |
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* Rather than hard-code a bad assumption in the general 440 code, the |
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* 440 pci code requires the board to decide at runtime. |
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* |
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* Return 0 for adapter mode, non-zero for host (monarch) mode. |
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* |
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* |
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************************************************************************/ |
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#if defined(CONFIG_PCI) |
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int is_pci_host(struct pci_controller *hose) |
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{ |
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if (is_monarch()) { |
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wait_for_pci_ready(); |
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return 1; /* return 1 for host controller */ |
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} else { |
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return 0; /* return 0 for adapter controller */ |
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} |
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} |
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#endif /* defined(CONFIG_PCI) */ |
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@ -1,24 +0,0 @@ |
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/*
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* (C) Copyright 2005 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __P3P440_H__ |
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#define __P3P440_H__ |
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#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11) |
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#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18) |
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#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20) |
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#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21) |
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#define CONFIG_SYS_LED_RED (0x80000000 >> 22) |
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#define LED_OFF 1 |
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#define LED_GREEN 2 |
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#define LED_RED 3 |
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#define LED_ORANGE 4 |
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long int fixed_sdram(void); |
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#endif /* __P3P440_H__ */ |
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@ -1,4 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_4xx=y |
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CONFIG_TARGET_P3P440=y |
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# CONFIG_CMD_SETEXPR is not set |
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@ -1,302 +0,0 @@ |
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/*
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* (C) Copyright 2005-2006 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/************************************************************************
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* board/config_p3p440.h - configuration for Prodrive P3P440 |
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***********************************************************************/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*-----------------------------------------------------------------------
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* High Level Configuration Options |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_P3P440 1 /* Board is P3P440 */ |
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#define CONFIG_440GP 1 /* Specifc GP support */ |
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#define CONFIG_440 1 /* ... PPC440 family */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the |
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* actual resources get mapped (not physical addresses) |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
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#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ |
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#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ |
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
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#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
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#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000) |
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM) |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ |
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
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/*-----------------------------------------------------------------------
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* DDR SDRAM |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ |
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#define CONFIG_SDRAM_ECC /* enable ECC support */ |
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#define CONFIG_SYS_SDRAM_TABLE { \ |
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{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
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{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ |
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/*-----------------------------------------------------------------------
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* Serial Port |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE 1 |
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#define CONFIG_SYS_NS16550_CLK get_serial_clock() |
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 } |
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/*-----------------------------------------------------------------------
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* I2C |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_PPC4XX |
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#define CONFIG_SYS_I2C_PPC4XX_CH0 |
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
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#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ |
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/*-----------------------------------------------------------------------
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* I2C RTC |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ |
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|
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/*-----------------------------------------------------------------------
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* I2C EEPROM (PCF8594C) for environment |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
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/* mask of address bits that overflow into the "EEPROM chip address" */ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ |
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/* 8 byte page write mode using */ |
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/* last 3 bits of the address */ |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ |
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/*-----------------------------------------------------------------------
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* Default configuration (environment varibles...) |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_PREBOOT "echo;" \ |
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"hostname=p3p440\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/p3p440/uImage\0" \
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"kernel_addr=ff800000\0" \
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"ramdisk_addr=ff810000\0" \
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"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"unlock=yes\0" \
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"" |
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#define CONFIG_BOOTCOMMAND "run net_nfs" |
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|
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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|
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#define CONFIG_BAUDRATE 115200 |
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|
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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|
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#define CONFIG_PPC4xx_EMAC |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_PHY_ADDR 0x1c /* PHY address */ |
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#define CONFIG_HAS_ETH1 |
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#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ |
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#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
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|
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#define CONFIG_NETCONSOLE /* include NetConsole support */ |
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|
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|
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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|
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|
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/*
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* Command line configuration. |
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*/ |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_DIAG |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_IRQ |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PCI |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_REGINFO |
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#define CONFIG_CMD_EEPROM |
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#define CONFIG_CMD_SNTP |
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|
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|
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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|
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/*-----------------------------------------------------------------------
|
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* Miscellaneous configurable options |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
||||
|
||||
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_FLASH0 0xFF800000 |
||||
#define CONFIG_SYS_FLASH1 0xFF000000 |
||||
#define CONFIG_SYS_FLASH2 0xFE800000 |
||||
#define CONFIG_SYS_FLASH3 0xFE000000 |
||||
#define CONFIG_SYS_USB 0xF0000000 |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x03050200 |
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB1AP 0x03050200 |
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB2AP 0x03050200 |
||||
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB3AP 0x03050200 |
||||
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 7 (USB controller) initialization */ |
||||
#define CONFIG_SYS_EBC_PB7AP 0x02015000 |
||||
#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue