Add support for the following DaVinci boards: - DV_EVM - SCHMOOGIE - SONATA Changes: - Split into separate board directories - Removed changes to MTD_DEBUG (or whatever it's called) - New CONFIG_CMD party line followed - Some cosmetic fixes, cleanup etc. - Patches against the latest U-Boot tree as of now. - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. Here is an excerpt from session log on SCHMOOGIE... U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com> Acked-by: Stefan Roese <sr@denx.de>master
parent
b0d2962faf
commit
c74b2108e3
@ -0,0 +1,52 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := dv_board.o
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SOBJS := board_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak *~ .depend
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,29 @@ |
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/* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* |
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* Board-specific low level initialization code. Called at the very end |
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* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no |
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* initialization required. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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.globl dv_board_init
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dv_board_init: |
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mov pc, lr |
@ -0,0 +1,39 @@ |
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Swaminathan <swami.iyer@ti.com>
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#
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# Davinci EVM board (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# Davinci EVM has 1 bank of 256 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 9000'0000
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# Visioneering Corp. Sonata board (ARM926EJS) cpu
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#
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# Sonata board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 8800'0000
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#
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# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
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#
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# Schmoogie board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 8800'0000
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#
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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#
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# we load ourself to 8108 '0000
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#
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#
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#Provide at least 16MB spacing between us and the Linux Kernel image
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TEXT_BASE = 0x81080000
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@ -0,0 +1,211 @@ |
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* Parts are shamelessly stolen from various TI sources, original copyright |
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* follows: |
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* ----------------------------------------------------------------- |
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* |
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* Copyright (C) 2004 Texas Instruments. |
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* |
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* ---------------------------------------------------------------------------- |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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* ---------------------------------------------------------------------------- |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/emac_defs.h> |
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#define MACH_TYPE_DAVINCI_EVM 901 |
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extern void i2c_init(int speed, int slaveaddr); |
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extern void timer_init(void); |
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extern int eth_hw_init(void); |
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extern phy_t phy; |
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/* Works on Always On power domain only (no PD argument) */ |
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void lpsc_on(unsigned int id) |
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{ |
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dv_reg_p mdstat, mdctl; |
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if (id >= DAVINCI_LPSC_GEM) |
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return; /* Don't work on DSP Power Domain */ |
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); |
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); |
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while (REG(PSC_PTSTAT) & 0x01) {;} |
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if ((*mdstat & 0x1f) == 0x03) |
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return; /* Already on and enabled */ |
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*mdctl |= 0x03; |
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/* Special treatment for some modules as for sprue14 p.7.4.2 */ |
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if ( (id == DAVINCI_LPSC_VPSSSLV) || |
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(id == DAVINCI_LPSC_EMAC) || |
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(id == DAVINCI_LPSC_EMAC_WRAPPER) || |
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(id == DAVINCI_LPSC_MDIO) || |
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(id == DAVINCI_LPSC_USB) || |
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(id == DAVINCI_LPSC_ATA) || |
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(id == DAVINCI_LPSC_VLYNQ) || |
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(id == DAVINCI_LPSC_UHPI) || |
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(id == DAVINCI_LPSC_DDR_EMIF) || |
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(id == DAVINCI_LPSC_AEMIF) || |
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(id == DAVINCI_LPSC_MMC_SD) || |
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(id == DAVINCI_LPSC_MEMSTICK) || |
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(id == DAVINCI_LPSC_McBSP) || |
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(id == DAVINCI_LPSC_GPIO) |
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) |
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*mdctl |= 0x200; |
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REG(PSC_PTCMD) = 0x01; |
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while (REG(PSC_PTSTAT) & 0x03) {;} |
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while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ |
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} |
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void dsp_on(void) |
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{ |
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int i; |
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if (REG(PSC_PDSTAT1) & 0x1f) |
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return; /* Already on */ |
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REG(PSC_GBLCTL) |= 0x01; |
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REG(PSC_PDCTL1) |= 0x01; |
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REG(PSC_PDCTL1) &= ~0x100; |
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; |
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; |
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; |
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; |
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REG(PSC_PTCMD) = 0x02; |
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for (i = 0; i < 100; i++) { |
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if (REG(PSC_EPCPR) & 0x02) |
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break; |
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} |
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REG(PSC_CHP_SHRTSW) = 0x01; |
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REG(PSC_PDCTL1) |= 0x100; |
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REG(PSC_EPCCR) = 0x02; |
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for (i = 0; i < 100; i++) { |
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if (!(REG(PSC_PTSTAT) & 0x02)) |
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break; |
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} |
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REG(PSC_GBLCTL) &= ~0x1f; |
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} |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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/* arch number of the board */ |
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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/* Workaround for TMS320DM6446 errata 1.3.22 */ |
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REG(PSC_SILVER_BULLET) = 0; |
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/* Power on required peripherals */ |
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lpsc_on(DAVINCI_LPSC_EMAC); |
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); |
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lpsc_on(DAVINCI_LPSC_MDIO); |
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lpsc_on(DAVINCI_LPSC_I2C); |
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lpsc_on(DAVINCI_LPSC_UART0); |
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lpsc_on(DAVINCI_LPSC_TIMER1); |
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lpsc_on(DAVINCI_LPSC_GPIO); |
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/* Powerup the DSP */ |
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dsp_on(); |
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/* Bringup UART0 out of reset */ |
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REG(UART0_PWREMU_MGMT) = 0x0000e003; |
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/* Enable GIO3.3V cells used for EMAC */ |
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REG(VDD3P3V_PWDN) = 0; |
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/* Enable UART0 MUX lines */ |
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REG(PINMUX1) |= 1; |
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/* Enable EMAC and AEMIF pins */ |
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REG(PINMUX0) = 0x80000c1f; |
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/* Enable I2C pin Mux */ |
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REG(PINMUX1) |= (1 << 7); |
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/* Set the Bus Priority Register to appropriate value */ |
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REG(VBPR) = 0x20; |
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timer_init(); |
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return(0); |
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} |
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int misc_init_r (void) |
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{ |
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u_int8_t tmp[20], buf[10]; |
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int i = 0; |
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int clk = 0; |
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clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); |
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printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); |
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printf ("DDR Clock : %dMHz\n", (clk / 2)); |
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/* Set Ethernet MAC address from EEPROM */ |
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if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { |
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printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); |
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} else { |
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tmp[0] = 0xff; |
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for (i = 0; i < 6; i++) |
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tmp[0] &= buf[i]; |
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if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { |
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sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", |
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
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setenv("ethaddr", (char *)&tmp[0]); |
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} |
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} |
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if (!eth_hw_init()) { |
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printf("ethernet init failed!\n"); |
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} else { |
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printf("ETH PHY : %s\n", phy.name); |
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} |
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i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); |
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setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); |
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return(0); |
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} |
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int dram_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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return(0); |
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} |
@ -0,0 +1,52 @@ |
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/* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
||||
* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN(4); |
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.text : |
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{ |
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cpu/arm926ejs/start.o (.text) |
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*(.text) |
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} |
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. = ALIGN(4); |
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.rodata : { *(.rodata) } |
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. = ALIGN(4); |
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.data : { *(.data) } |
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. = ALIGN(4); |
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.got : { *(.got) } |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = ALIGN(4); |
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__bss_start = .; |
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.bss : { *(.bss) } |
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_end = .; |
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} |
@ -0,0 +1,52 @@ |
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#
|
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# (C) Copyright 2000, 2001, 2002
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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|
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COBJS := dv_board.o
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SOBJS := board_init.o
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
|
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|
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
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|
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distclean: clean |
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rm -f $(LIB) core *.bak *~ .depend
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|
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#########################################################################
|
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# This is for $(obj).depend target
|
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
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@ -0,0 +1,29 @@ |
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/* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
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* |
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* Board-specific low level initialization code. Called at the very end |
||||
* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no |
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* initialization required. |
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* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <config.h> |
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|
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.globl dv_board_init
|
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dv_board_init: |
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|
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mov pc, lr |
@ -0,0 +1,39 @@ |
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#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Swaminathan <swami.iyer@ti.com>
|
||||
#
|
||||
# Davinci EVM board (ARM925EJS) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# Davinci EVM has 1 bank of 256 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 9000'0000
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# Visioneering Corp. Sonata board (ARM926EJS) cpu
|
||||
#
|
||||
# Sonata board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
|
||||
#
|
||||
# Schmoogie board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 8108 '0000
|
||||
#
|
||||
#
|
||||
|
||||
#Provide at least 16MB spacing between us and the Linux Kernel image
|
||||
TEXT_BASE = 0x81080000
|
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Parts are shamelessly stolen from various TI sources, original copyright |
||||
* follows: |
||||
* ----------------------------------------------------------------- |
||||
* |
||||
* Copyright (C) 2004 Texas Instruments. |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* ---------------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#define MACH_TYPE_SCHMOOGIE 1255 |
||||
|
||||
extern void i2c_init(int speed, int slaveaddr); |
||||
extern void timer_init(void); |
||||
extern int eth_hw_init(void); |
||||
extern phy_t phy; |
||||
|
||||
|
||||
/* Works on Always On power domain only (no PD argument) */ |
||||
void lpsc_on(unsigned int id) |
||||
{ |
||||
dv_reg_p mdstat, mdctl; |
||||
|
||||
if (id >= DAVINCI_LPSC_GEM) |
||||
return; /* Don't work on DSP Power Domain */ |
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); |
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); |
||||
|
||||
while (REG(PSC_PTSTAT) & 0x01) {;} |
||||
|
||||
if ((*mdstat & 0x1f) == 0x03) |
||||
return; /* Already on and enabled */ |
||||
|
||||
*mdctl |= 0x03; |
||||
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */ |
||||
if ( (id == DAVINCI_LPSC_VPSSSLV) || |
||||
(id == DAVINCI_LPSC_EMAC) || |
||||
(id == DAVINCI_LPSC_EMAC_WRAPPER) || |
||||
(id == DAVINCI_LPSC_MDIO) || |
||||
(id == DAVINCI_LPSC_USB) || |
||||
(id == DAVINCI_LPSC_ATA) || |
||||
(id == DAVINCI_LPSC_VLYNQ) || |
||||
(id == DAVINCI_LPSC_UHPI) || |
||||
(id == DAVINCI_LPSC_DDR_EMIF) || |
||||
(id == DAVINCI_LPSC_AEMIF) || |
||||
(id == DAVINCI_LPSC_MMC_SD) || |
||||
(id == DAVINCI_LPSC_MEMSTICK) || |
||||
(id == DAVINCI_LPSC_McBSP) || |
||||
(id == DAVINCI_LPSC_GPIO) |
||||
) |
||||
*mdctl |= 0x200; |
||||
|
||||
REG(PSC_PTCMD) = 0x01; |
||||
|
||||
while (REG(PSC_PTSTAT) & 0x03) {;} |
||||
while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ |
||||
} |
||||
|
||||
void dsp_on(void) |
||||
{ |
||||
int i; |
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f) |
||||
return; /* Already on */ |
||||
|
||||
REG(PSC_GBLCTL) |= 0x01; |
||||
REG(PSC_PDCTL1) |= 0x01; |
||||
REG(PSC_PDCTL1) &= ~0x100; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; |
||||
REG(PSC_PTCMD) = 0x02; |
||||
|
||||
for (i = 0; i < 100; i++) { |
||||
if (REG(PSC_EPCPR) & 0x02) |
||||
break; |
||||
} |
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01; |
||||
REG(PSC_PDCTL1) |= 0x100; |
||||
REG(PSC_EPCCR) = 0x02; |
||||
|
||||
for (i = 0; i < 100; i++) { |
||||
if (!(REG(PSC_PTSTAT) & 0x02)) |
||||
break; |
||||
} |
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f; |
||||
} |
||||
|
||||
|
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of the board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; |
||||
|
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
||||
|
||||
/* Workaround for TMS320DM6446 errata 1.3.22 */ |
||||
REG(PSC_SILVER_BULLET) = 0; |
||||
|
||||
/* Power on required peripherals */ |
||||
lpsc_on(DAVINCI_LPSC_EMAC); |
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); |
||||
lpsc_on(DAVINCI_LPSC_MDIO); |
||||
lpsc_on(DAVINCI_LPSC_I2C); |
||||
lpsc_on(DAVINCI_LPSC_UART0); |
||||
lpsc_on(DAVINCI_LPSC_TIMER1); |
||||
lpsc_on(DAVINCI_LPSC_GPIO); |
||||
|
||||
/* Powerup the DSP */ |
||||
dsp_on(); |
||||
|
||||
/* Bringup UART0 out of reset */ |
||||
REG(UART0_PWREMU_MGMT) = 0x0000e003; |
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */ |
||||
REG(VDD3P3V_PWDN) = 0; |
||||
|
||||
/* Enable UART0 MUX lines */ |
||||
REG(PINMUX1) |= 1; |
||||
|
||||
/* Enable EMAC and AEMIF pins */ |
||||
REG(PINMUX0) = 0x80000c1f; |
||||
|
||||
/* Enable I2C pin Mux */ |
||||
REG(PINMUX1) |= (1 << 7); |
||||
|
||||
/* Set the Bus Priority Register to appropriate value */ |
||||
REG(VBPR) = 0x20; |
||||
|
||||
timer_init(); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
u_int8_t tmp[20], buf[10]; |
||||
int i = 0; |
||||
int clk = 0; |
||||
|
||||
/* Set serial number from UID chip */ |
||||
u_int8_t crc_tbl[256] = { |
||||
0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, |
||||
0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, |
||||
0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, |
||||
0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, |
||||
0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, |
||||
0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, |
||||
0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, |
||||
0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, |
||||
0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, |
||||
0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, |
||||
0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, |
||||
0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, |
||||
0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, |
||||
0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, |
||||
0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, |
||||
0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, |
||||
0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, |
||||
0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, |
||||
0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, |
||||
0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, |
||||
0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, |
||||
0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, |
||||
0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, |
||||
0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, |
||||
0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, |
||||
0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, |
||||
0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, |
||||
0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, |
||||
0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, |
||||
0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, |
||||
0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, |
||||
0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 |
||||
}; |
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); |
||||
|
||||
printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); |
||||
printf ("DDR Clock : %dMHz\n", (clk / 2)); |
||||
|
||||
/* Set serial number from UID chip */ |
||||
if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { |
||||
printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); |
||||
forceenv("serial#", "FAILED"); |
||||
} else { |
||||
if (buf[0] != 0x70) { /* Device Family Code */ |
||||
printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); |
||||
forceenv("serial#", "FAILED"); |
||||
} |
||||
} |
||||
/* Now check CRC */ |
||||
tmp[0] = 0; |
||||
for (i = 0; i < 8; i++) |
||||
tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; |
||||
|
||||
if (tmp[0] != 0) { |
||||
printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); |
||||
forceenv("serial#", "FAILED"); |
||||
} else { |
||||
/* CRC OK, set "serial" env variable */ |
||||
sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", |
||||
buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); |
||||
forceenv("serial#", (char *)&tmp[0]); |
||||
} |
||||
|
||||
if (!eth_hw_init()) { |
||||
printf("ethernet init failed!\n"); |
||||
} else { |
||||
printf("ETH PHY : %s\n", phy.name); |
||||
} |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return(0); |
||||
} |
@ -0,0 +1,52 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
@ -0,0 +1,52 @@ |
||||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := dv_board.o
|
||||
SOBJS := board_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak *~ .depend
|
||||
|
||||
#########################################################################
|
||||
# This is for $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,100 @@ |
||||
/* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
* |
||||
* Board-specific low level initialization code. Called at the very end |
||||
* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no |
||||
* initialization required. |
||||
* |
||||
* For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer |
||||
* Sonata boards, AFAIK, don't use this so it's just return by default. Ask |
||||
* Visioneering if they reinvented the wheel once again to make sure :) |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
|
||||
.globl dv_board_init
|
||||
dv_board_init: |
||||
#ifdef SONATA_BOARD_GPIOWP |
||||
/* Set PINMUX0 to enable GPIO4 */ |
||||
ldr r0, _PINMUX0 |
||||
ldr r1, GPIO4_EN_MASK |
||||
ldr r2, [r0] |
||||
and r2, r2, r1 |
||||
str r2, [r0] |
||||
|
||||
/* Enable GPIO LPSC module */ |
||||
ldr r0, PTSTAT |
||||
|
||||
gpio_ptstat_loop1: |
||||
ldr r2, [r0] |
||||
tst r2, $0x00000001 |
||||
bne gpio_ptstat_loop1 |
||||
|
||||
ldr r1, MDCTL_GPIO |
||||
ldr r2, [r1] |
||||
and r2, r2, $0xfffffff8 |
||||
orr r2, r2, $0x00000003 |
||||
str r2, [r1] |
||||
|
||||
orr r2, r2, $0x00000200 |
||||
str r2, [r1] |
||||
|
||||
ldr r1, PTCMD |
||||
mov r2, $0x00000001 |
||||
str r2, [r1] |
||||
|
||||
gpio_ptstat_loop2: |
||||
ldr r2, [r0] |
||||
tst r2, $0x00000001 |
||||
bne gpio_ptstat_loop2 |
||||
|
||||
ldr r0, MDSTAT_GPIO |
||||
gpio_mdstat_loop: |
||||
ldr r2, [r0] |
||||
and r2, r2, $0x0000001f |
||||
teq r2, $0x00000003 |
||||
bne gpio_mdstat_loop |
||||
|
||||
/* GPIO4 -> output */ |
||||
ldr r0, GPIO_DIR01 |
||||
mov r1, $0x10 |
||||
ldr r2, [r0] |
||||
bic r2, r2, r0 |
||||
str r2, [r0] |
||||
|
||||
/* Set it to 0 (Write Protect) */ |
||||
ldr r0, GPIO_CLR_DATA01 |
||||
str r1, [r0] |
||||
#endif |
||||
|
||||
mov pc, lr |
||||
|
||||
#ifdef SONATA_BOARD_GPIOWP |
||||
.ltorg |
||||
|
||||
GPIO4_EN_MASK: |
||||
.word 0xf77fffff
|
||||
MDCTL_GPIO: |
||||
.word 0x01c41a68
|
||||
MDSTAT_GPIO: |
||||
.word 0x01c41868
|
||||
GPIO_DIR01: |
||||
.word 0x01c67010
|
||||
GPIO_CLR_DATA01: |
||||
.word 0x01c6701c
|
||||
#endif |
@ -0,0 +1,39 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Swaminathan <swami.iyer@ti.com>
|
||||
#
|
||||
# Davinci EVM board (ARM925EJS) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# Davinci EVM has 1 bank of 256 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 9000'0000
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# Visioneering Corp. Sonata board (ARM926EJS) cpu
|
||||
#
|
||||
# Sonata board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
|
||||
#
|
||||
# Schmoogie board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 8108 '0000
|
||||
#
|
||||
#
|
||||
|
||||
#Provide at least 16MB spacing between us and the Linux Kernel image
|
||||
TEXT_BASE = 0x81080000
|
@ -0,0 +1,208 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Parts are shamelessly stolen from various TI sources, original copyright |
||||
* follows: |
||||
* ----------------------------------------------------------------- |
||||
* |
||||
* Copyright (C) 2004 Texas Instruments. |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* ---------------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#define MACH_TYPE_SONATA 1254 |
||||
|
||||
extern void i2c_init(int speed, int slaveaddr); |
||||
extern void timer_init(void); |
||||
extern int eth_hw_init(void); |
||||
extern phy_t phy; |
||||
|
||||
|
||||
/* Works on Always On power domain only (no PD argument) */ |
||||
void lpsc_on(unsigned int id) |
||||
{ |
||||
dv_reg_p mdstat, mdctl; |
||||
|
||||
if (id >= DAVINCI_LPSC_GEM) |
||||
return; /* Don't work on DSP Power Domain */ |
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); |
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); |
||||
|
||||
while (REG(PSC_PTSTAT) & 0x01) {;} |
||||
|
||||
if ((*mdstat & 0x1f) == 0x03) |
||||
return; /* Already on and enabled */ |
||||
|
||||
*mdctl |= 0x03; |
||||
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */ |
||||
if ( (id == DAVINCI_LPSC_VPSSSLV) || |
||||
(id == DAVINCI_LPSC_EMAC) || |
||||
(id == DAVINCI_LPSC_EMAC_WRAPPER) || |
||||
(id == DAVINCI_LPSC_MDIO) || |
||||
(id == DAVINCI_LPSC_USB) || |
||||
(id == DAVINCI_LPSC_ATA) || |
||||
(id == DAVINCI_LPSC_VLYNQ) || |
||||
(id == DAVINCI_LPSC_UHPI) || |
||||
(id == DAVINCI_LPSC_DDR_EMIF) || |
||||
(id == DAVINCI_LPSC_AEMIF) || |
||||
(id == DAVINCI_LPSC_MMC_SD) || |
||||
(id == DAVINCI_LPSC_MEMSTICK) || |
||||
(id == DAVINCI_LPSC_McBSP) || |
||||
(id == DAVINCI_LPSC_GPIO) |
||||
) |
||||
*mdctl |= 0x200; |
||||
|
||||
REG(PSC_PTCMD) = 0x01; |
||||
|
||||
while (REG(PSC_PTSTAT) & 0x03) {;} |
||||
while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ |
||||
} |
||||
|
||||
void dsp_on(void) |
||||
{ |
||||
int i; |
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f) |
||||
return; /* Already on */ |
||||
|
||||
REG(PSC_GBLCTL) |= 0x01; |
||||
REG(PSC_PDCTL1) |= 0x01; |
||||
REG(PSC_PDCTL1) &= ~0x100; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; |
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; |
||||
REG(PSC_PTCMD) = 0x02; |
||||
|
||||
for (i = 0; i < 100; i++) { |
||||
if (REG(PSC_EPCPR) & 0x02) |
||||
break; |
||||
} |
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01; |
||||
REG(PSC_PDCTL1) |= 0x100; |
||||
REG(PSC_EPCCR) = 0x02; |
||||
|
||||
for (i = 0; i < 100; i++) { |
||||
if (!(REG(PSC_PTSTAT) & 0x02)) |
||||
break; |
||||
} |
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f; |
||||
} |
||||
|
||||
|
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of the board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_SONATA; |
||||
|
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
||||
|
||||
/* Workaround for TMS320DM6446 errata 1.3.22 */ |
||||
REG(PSC_SILVER_BULLET) = 0; |
||||
|
||||
/* Power on required peripherals */ |
||||
lpsc_on(DAVINCI_LPSC_EMAC); |
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); |
||||
lpsc_on(DAVINCI_LPSC_MDIO); |
||||
lpsc_on(DAVINCI_LPSC_I2C); |
||||
lpsc_on(DAVINCI_LPSC_UART0); |
||||
lpsc_on(DAVINCI_LPSC_TIMER1); |
||||
lpsc_on(DAVINCI_LPSC_GPIO); |
||||
|
||||
/* Powerup the DSP */ |
||||
dsp_on(); |
||||
|
||||
/* Bringup UART0 out of reset */ |
||||
REG(UART0_PWREMU_MGMT) = 0x0000e003; |
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */ |
||||
REG(VDD3P3V_PWDN) = 0; |
||||
|
||||
/* Enable UART0 MUX lines */ |
||||
REG(PINMUX1) |= 1; |
||||
|
||||
/* Enable EMAC and AEMIF pins */ |
||||
REG(PINMUX0) = 0x80000c1f; |
||||
|
||||
/* Enable I2C pin Mux */ |
||||
REG(PINMUX1) |= (1 << 7); |
||||
|
||||
/* Set the Bus Priority Register to appropriate value */ |
||||
REG(VBPR) = 0x20; |
||||
|
||||
timer_init(); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
u_int8_t tmp[20], buf[10]; |
||||
int i = 0; |
||||
int clk = 0; |
||||
|
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); |
||||
|
||||
printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); |
||||
printf ("DDR Clock : %dMHz\n", (clk / 2)); |
||||
|
||||
/* Set Ethernet MAC address from EEPROM */ |
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { |
||||
printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); |
||||
} else { |
||||
tmp[0] = 0xff; |
||||
for (i = 0; i < 6; i++) |
||||
tmp[0] &= buf[i]; |
||||
|
||||
if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { |
||||
sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", |
||||
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); |
||||
setenv("ethaddr", (char *)&tmp[0]); |
||||
} |
||||
} |
||||
|
||||
if (!eth_hw_init()) { |
||||
printf("ethernet init failed!\n"); |
||||
} else { |
||||
printf("ETH PHY : %s\n", phy.name); |
||||
} |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return(0); |
||||
} |
@ -0,0 +1,52 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o
|
||||
SOBJS = lowlevel_init.o reset.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,156 @@ |
||||
/*
|
||||
* National Semiconductor DP83848 PHY Driver for TI DaVinci |
||||
* (TMS320DM644x) based boards. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* -------------------------------------------------------- |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <net.h> |
||||
#include <dp83848.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
|
||||
int dp83848_is_phy_connected(int phy_addr) |
||||
{ |
||||
u_int16_t id1, id2; |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) |
||||
return(0); |
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) |
||||
return(0); |
||||
|
||||
if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) |
||||
return(1); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int dp83848_get_link_speed(int phy_addr) |
||||
{ |
||||
u_int16_t tmp; |
||||
volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) |
||||
return(0); |
||||
|
||||
if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ |
||||
return(0); |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) |
||||
return(0); |
||||
|
||||
/* Speed doesn't matter, there is no setting for it in EMAC... */ |
||||
if (tmp & DP83848_SPEED) { |
||||
if (tmp & DP83848_DUPLEX) { |
||||
/* set DM644x EMAC for Full Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; |
||||
} else { |
||||
/*set DM644x EMAC for Half Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; |
||||
} |
||||
|
||||
return(1); |
||||
} else { |
||||
if (tmp & DP83848_DUPLEX) { |
||||
/* set DM644x EMAC for Full Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; |
||||
} else { |
||||
/*set DM644x EMAC for Half Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; |
||||
} |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
|
||||
int dp83848_init_phy(int phy_addr) |
||||
{ |
||||
int ret = 1; |
||||
|
||||
if (!dp83848_get_link_speed(phy_addr)) { |
||||
/* Try another time */ |
||||
udelay(100000); |
||||
ret = dp83848_get_link_speed(phy_addr); |
||||
} |
||||
|
||||
/* Disable PHY Interrupts */ |
||||
dm644x_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); |
||||
|
||||
return(ret); |
||||
} |
||||
|
||||
|
||||
int dp83848_auto_negotiate(int phy_addr) |
||||
{ |
||||
u_int16_t tmp; |
||||
|
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) |
||||
return(0); |
||||
|
||||
/* Restart Auto_negotiation */ |
||||
tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ |
||||
tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ |
||||
dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); |
||||
|
||||
/* Set the Auto_negotiation Advertisement Register
|
||||
* MII advertising for Next page, 100BaseTxFD and HD, |
||||
* 10BaseTFD and HD, IEEE 802.3 |
||||
*/ |
||||
tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | |
||||
DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; |
||||
dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); |
||||
|
||||
|
||||
/* Read Control Register */ |
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) |
||||
return(0); |
||||
|
||||
tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; |
||||
dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); |
||||
|
||||
/* Restart Auto_negotiation */ |
||||
tmp |= DP83848_RESTART_AUTONEG; |
||||
dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); |
||||
|
||||
/*check AutoNegotiate complete */ |
||||
udelay(10000); |
||||
if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) |
||||
return(0); |
||||
|
||||
if (!(tmp & DP83848_AUTONEG_COMP)) |
||||
return(0); |
||||
|
||||
return (dp83848_get_link_speed(phy_addr)); |
||||
} |
||||
|
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
#endif /* CONFIG_DRIVER_ETHER */ |
@ -0,0 +1,652 @@ |
||||
/*
|
||||
* Ethernet driver for TI TMS320DM644x (DaVinci) chips. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright |
||||
* follows: |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* dm644x_emac.c |
||||
* |
||||
* TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM |
||||
* |
||||
* Copyright (C) 2005 Texas Instruments. |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* ---------------------------------------------------------------------------- |
||||
|
||||
* Modifications: |
||||
* ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. |
||||
* ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors |
||||
* |
||||
*/ |
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include <miiphy.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
|
||||
unsigned int emac_dbg = 0; |
||||
#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) |
||||
|
||||
/* Internal static functions */ |
||||
static int dm644x_eth_hw_init (void); |
||||
static int dm644x_eth_open (void); |
||||
static int dm644x_eth_close (void); |
||||
static int dm644x_eth_send_packet (volatile void *packet, int length); |
||||
static int dm644x_eth_rcv_packet (void); |
||||
static void dm644x_eth_mdio_enable(void); |
||||
|
||||
static int gen_init_phy(int phy_addr); |
||||
static int gen_is_phy_connected(int phy_addr); |
||||
static int gen_get_link_speed(int phy_addr); |
||||
static int gen_auto_negotiate(int phy_addr); |
||||
|
||||
/* Wrappers exported to the U-Boot proper */ |
||||
int eth_hw_init(void) |
||||
{ |
||||
return(dm644x_eth_hw_init()); |
||||
} |
||||
|
||||
int eth_init(bd_t * bd) |
||||
{ |
||||
return(dm644x_eth_open()); |
||||
} |
||||
|
||||
void eth_halt(void) |
||||
{ |
||||
dm644x_eth_close(); |
||||
} |
||||
|
||||
int eth_send(volatile void *packet, int length) |
||||
{ |
||||
return(dm644x_eth_send_packet(packet, length)); |
||||
} |
||||
|
||||
int eth_rx(void) |
||||
{ |
||||
return(dm644x_eth_rcv_packet()); |
||||
} |
||||
|
||||
void eth_mdio_enable(void) |
||||
{ |
||||
dm644x_eth_mdio_enable(); |
||||
} |
||||
/* End of wrappers */ |
||||
|
||||
|
||||
static u_int8_t dm644x_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
||||
|
||||
/*
|
||||
* This function must be called before emac_open() if you want to override |
||||
* the default mac address. |
||||
*/ |
||||
void dm644x_eth_set_mac_addr(const u_int8_t *addr) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) { |
||||
dm644x_eth_mac_addr[i] = addr[i]; |
||||
} |
||||
} |
||||
|
||||
/* EMAC Addresses */ |
||||
static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; |
||||
static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; |
||||
static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; |
||||
|
||||
/* EMAC descriptors */ |
||||
static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); |
||||
static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); |
||||
static volatile emac_desc *emac_rx_active_head = 0; |
||||
static volatile emac_desc *emac_rx_active_tail = 0; |
||||
static int emac_rx_queue_active = 0; |
||||
|
||||
/* Receive packet buffers */ |
||||
static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; |
||||
|
||||
/* PHY address for a discovered PHY (0xff - not found) */ |
||||
static volatile u_int8_t active_phy_addr = 0xff; |
||||
|
||||
phy_t phy; |
||||
|
||||
static void dm644x_eth_mdio_enable(void) |
||||
{ |
||||
u_int32_t clkdiv; |
||||
|
||||
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; |
||||
|
||||
adap_mdio->CONTROL = (clkdiv & 0xff) | |
||||
MDIO_CONTROL_ENABLE | |
||||
MDIO_CONTROL_FAULT | |
||||
MDIO_CONTROL_FAULT_ENABLE; |
||||
|
||||
while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} |
||||
} |
||||
|
||||
/*
|
||||
* Tries to find an active connected PHY. Returns 1 if address if found. |
||||
* If no active PHY (or more than one PHY) found returns 0. |
||||
* Sets active_phy_addr variable. |
||||
*/ |
||||
static int dm644x_eth_phy_detect(void) |
||||
{ |
||||
u_int32_t phy_act_state; |
||||
int i; |
||||
|
||||
active_phy_addr = 0xff; |
||||
|
||||
if ((phy_act_state = adap_mdio->ALIVE) == 0) |
||||
return(0); /* No active PHYs */ |
||||
|
||||
debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); |
||||
|
||||
for (i = 0; i < 32; i++) { |
||||
if (phy_act_state & (1 << i)) { |
||||
if (phy_act_state & ~(1 << i)) |
||||
return(0); /* More than one PHY */ |
||||
else { |
||||
active_phy_addr = i; |
||||
return(1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return(0); /* Just to make GCC happy */ |
||||
} |
||||
|
||||
|
||||
/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ |
||||
int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) |
||||
{ |
||||
int tmp; |
||||
|
||||
while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} |
||||
|
||||
adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | |
||||
MDIO_USERACCESS0_WRITE_READ | |
||||
((reg_num & 0x1f) << 21) | |
||||
((phy_addr & 0x1f) << 16); |
||||
|
||||
/* Wait for command to complete */ |
||||
while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} |
||||
|
||||
if (tmp & MDIO_USERACCESS0_ACK) { |
||||
*data = tmp & 0xffff; |
||||
return(1); |
||||
} |
||||
|
||||
*data = -1; |
||||
return(0); |
||||
} |
||||
|
||||
/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ |
||||
int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) |
||||
{ |
||||
|
||||
while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} |
||||
|
||||
adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | |
||||
MDIO_USERACCESS0_WRITE_WRITE | |
||||
((reg_num & 0x1f) << 21) | |
||||
((phy_addr & 0x1f) << 16) | |
||||
(data & 0xffff); |
||||
|
||||
/* Wait for command to complete */ |
||||
while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
/* PHY functions for a generic PHY */ |
||||
static int gen_init_phy(int phy_addr) |
||||
{ |
||||
int ret = 1; |
||||
|
||||
if (gen_get_link_speed(phy_addr)) { |
||||
/* Try another time */ |
||||
ret = gen_get_link_speed(phy_addr); |
||||
} |
||||
|
||||
return(ret); |
||||
} |
||||
|
||||
static int gen_is_phy_connected(int phy_addr) |
||||
{ |
||||
u_int16_t dummy; |
||||
|
||||
return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); |
||||
} |
||||
|
||||
static int gen_get_link_speed(int phy_addr) |
||||
{ |
||||
u_int16_t tmp; |
||||
|
||||
if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) |
||||
return(1); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
static int gen_auto_negotiate(int phy_addr) |
||||
{ |
||||
u_int16_t tmp; |
||||
|
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) |
||||
return(0); |
||||
|
||||
/* Restart Auto_negotiation */ |
||||
tmp |= PHY_BMCR_AUTON; |
||||
dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); |
||||
|
||||
/*check AutoNegotiate complete */ |
||||
udelay (10000); |
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) |
||||
return(0); |
||||
|
||||
if (!(tmp & PHY_BMSR_AUTN_COMP)) |
||||
return(0); |
||||
|
||||
return(gen_get_link_speed(phy_addr)); |
||||
} |
||||
/* End of generic PHY functions */ |
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
||||
static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) |
||||
{ |
||||
return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); |
||||
} |
||||
|
||||
static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) |
||||
{ |
||||
return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1); |
||||
} |
||||
|
||||
int dm644x_eth_miiphy_initialize(bd_t *bis) |
||||
{ |
||||
miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); |
||||
|
||||
return(1); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* This function initializes the emac hardware. It does NOT initialize |
||||
* EMAC modules power or pin multiplexors, that is done by board_init() |
||||
* much earlier in bootup process. Returns 1 on success, 0 otherwise. |
||||
*/ |
||||
static int dm644x_eth_hw_init(void) |
||||
{ |
||||
u_int32_t phy_id; |
||||
u_int16_t tmp; |
||||
int i; |
||||
|
||||
dm644x_eth_mdio_enable(); |
||||
|
||||
for (i = 0; i < 256; i++) { |
||||
if (adap_mdio->ALIVE) |
||||
break; |
||||
udelay(10); |
||||
} |
||||
|
||||
if (i >= 256) { |
||||
printf("No ETH PHY detected!!!\n"); |
||||
return(0); |
||||
} |
||||
|
||||
/* Find if a PHY is connected and get it's address */ |
||||
if (!dm644x_eth_phy_detect()) |
||||
return(0); |
||||
|
||||
/* Get PHY ID and initialize phy_ops for a detected PHY */ |
||||
if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { |
||||
active_phy_addr = 0xff; |
||||
return(0); |
||||
} |
||||
|
||||
phy_id = (tmp << 16) & 0xffff0000; |
||||
|
||||
if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { |
||||
active_phy_addr = 0xff; |
||||
return(0); |
||||
} |
||||
|
||||
phy_id |= tmp & 0x0000ffff; |
||||
|
||||
switch (phy_id) { |
||||
case PHY_LXT972: |
||||
sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); |
||||
phy.init = lxt972_init_phy; |
||||
phy.is_phy_connected = lxt972_is_phy_connected; |
||||
phy.get_link_speed = lxt972_get_link_speed; |
||||
phy.auto_negotiate = lxt972_auto_negotiate; |
||||
break; |
||||
case PHY_DP83848: |
||||
sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); |
||||
phy.init = dp83848_init_phy; |
||||
phy.is_phy_connected = dp83848_is_phy_connected; |
||||
phy.get_link_speed = dp83848_get_link_speed; |
||||
phy.auto_negotiate = dp83848_auto_negotiate; |
||||
break; |
||||
default: |
||||
sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); |
||||
phy.init = gen_init_phy; |
||||
phy.is_phy_connected = gen_is_phy_connected; |
||||
phy.get_link_speed = gen_get_link_speed; |
||||
phy.auto_negotiate = gen_auto_negotiate; |
||||
} |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
|
||||
/* Eth device open */ |
||||
static int dm644x_eth_open(void) |
||||
{ |
||||
dv_reg_p addr; |
||||
u_int32_t clkdiv, cnt; |
||||
volatile emac_desc *rx_desc; |
||||
|
||||
debug_emac("+ emac_open\n"); |
||||
|
||||
/* Reset EMAC module and disable interrupts in wrapper */ |
||||
adap_emac->SOFTRESET = 1; |
||||
while (adap_emac->SOFTRESET != 0) {;} |
||||
adap_ewrap->EWCTL = 0; |
||||
for (cnt = 0; cnt < 5; cnt++) { |
||||
clkdiv = adap_ewrap->EWCTL; |
||||
} |
||||
|
||||
rx_desc = emac_rx_desc; |
||||
|
||||
adap_emac->TXCONTROL = 0x01; |
||||
adap_emac->RXCONTROL = 0x01; |
||||
|
||||
/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ |
||||
/* Using channel 0 only - other channels are disabled */ |
||||
adap_emac->MACINDEX = 0; |
||||
adap_emac->MACADDRHI = |
||||
(dm644x_eth_mac_addr[3] << 24) | |
||||
(dm644x_eth_mac_addr[2] << 16) | |
||||
(dm644x_eth_mac_addr[1] << 8) | |
||||
(dm644x_eth_mac_addr[0]); |
||||
adap_emac->MACADDRLO = |
||||
(dm644x_eth_mac_addr[5] << 8) | |
||||
(dm644x_eth_mac_addr[4]); |
||||
|
||||
adap_emac->MACHASH1 = 0; |
||||
adap_emac->MACHASH2 = 0; |
||||
|
||||
/* Set source MAC address - REQUIRED */ |
||||
adap_emac->MACSRCADDRHI = |
||||
(dm644x_eth_mac_addr[3] << 24) | |
||||
(dm644x_eth_mac_addr[2] << 16) | |
||||
(dm644x_eth_mac_addr[1] << 8) | |
||||
(dm644x_eth_mac_addr[0]); |
||||
adap_emac->MACSRCADDRLO = |
||||
(dm644x_eth_mac_addr[4] << 8) | |
||||
(dm644x_eth_mac_addr[5]); |
||||
|
||||
/* Set DMA 8 TX / 8 RX Head pointers to 0 */ |
||||
addr = &adap_emac->TX0HDP; |
||||
for(cnt = 0; cnt < 16; cnt++) |
||||
*addr++ = 0; |
||||
|
||||
addr = &adap_emac->RX0HDP; |
||||
for(cnt = 0; cnt < 16; cnt++) |
||||
*addr++ = 0; |
||||
|
||||
/* Clear Statistics (do this before setting MacControl register) */ |
||||
addr = &adap_emac->RXGOODFRAMES; |
||||
for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) |
||||
*addr++ = 0; |
||||
|
||||
/* No multicast addressing */ |
||||
adap_emac->MACHASH1 = 0; |
||||
adap_emac->MACHASH2 = 0; |
||||
|
||||
/* Create RX queue and set receive process in place */ |
||||
emac_rx_active_head = emac_rx_desc; |
||||
for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { |
||||
rx_desc->next = (u_int32_t)(rx_desc + 1); |
||||
rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; |
||||
rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; |
||||
rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; |
||||
rx_desc++; |
||||
} |
||||
|
||||
/* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ |
||||
rx_desc--; |
||||
rx_desc->next = 0; |
||||
emac_rx_active_tail = rx_desc; |
||||
emac_rx_queue_active = 1; |
||||
|
||||
/* Enable TX/RX */ |
||||
adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; |
||||
adap_emac->RXBUFFEROFFSET = 0; |
||||
|
||||
/* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ |
||||
adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; |
||||
|
||||
/* Enable ch 0 only */ |
||||
adap_emac->RXUNICASTSET = 0x01; |
||||
|
||||
/* Enable MII interface and Full duplex mode */ |
||||
adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); |
||||
|
||||
/* Init MDIO & get link state */ |
||||
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; |
||||
adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); |
||||
|
||||
if (!phy.get_link_speed(active_phy_addr)) |
||||
return(0); |
||||
|
||||
/* Start receive process */ |
||||
adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; |
||||
|
||||
debug_emac("- emac_open\n"); |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
/* EMAC Channel Teardown */ |
||||
static void dm644x_eth_ch_teardown(int ch) |
||||
{ |
||||
dv_reg dly = 0xff; |
||||
dv_reg cnt; |
||||
|
||||
debug_emac("+ emac_ch_teardown\n"); |
||||
|
||||
if (ch == EMAC_CH_TX) { |
||||
/* Init TX channel teardown */ |
||||
adap_emac->TXTEARDOWN = 1; |
||||
for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { |
||||
/* Wait here for Tx teardown completion interrupt to occur
|
||||
* Note: A task delay can be called here to pend rather than |
||||
* occupying CPU cycles - anyway it has been found that teardown |
||||
* takes very few cpu cycles and does not affect functionality */ |
||||
dly--; |
||||
udelay(1); |
||||
if (dly == 0) |
||||
break; |
||||
} |
||||
adap_emac->TX0CP = cnt; |
||||
adap_emac->TX0HDP = 0; |
||||
} else { |
||||
/* Init RX channel teardown */ |
||||
adap_emac->RXTEARDOWN = 1; |
||||
for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { |
||||
/* Wait here for Rx teardown completion interrupt to occur
|
||||
* Note: A task delay can be called here to pend rather than |
||||
* occupying CPU cycles - anyway it has been found that teardown |
||||
* takes very few cpu cycles and does not affect functionality */ |
||||
dly--; |
||||
udelay(1); |
||||
if (dly == 0) |
||||
break; |
||||
} |
||||
adap_emac->RX0CP = cnt; |
||||
adap_emac->RX0HDP = 0; |
||||
} |
||||
|
||||
debug_emac("- emac_ch_teardown\n"); |
||||
} |
||||
|
||||
/* Eth device close */ |
||||
static int dm644x_eth_close(void) |
||||
{ |
||||
debug_emac("+ emac_close\n"); |
||||
|
||||
dm644x_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ |
||||
dm644x_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ |
||||
|
||||
/* Reset EMAC module and disable interrupts in wrapper */ |
||||
adap_emac->SOFTRESET = 1; |
||||
adap_ewrap->EWCTL = 0; |
||||
|
||||
debug_emac("- emac_close\n"); |
||||
return(1); |
||||
} |
||||
|
||||
static int tx_send_loop = 0; |
||||
|
||||
/*
|
||||
* This function sends a single packet on the network and returns |
||||
* positive number (number of bytes transmitted) or negative for error |
||||
*/ |
||||
static int dm644x_eth_send_packet(volatile void *packet, int length) |
||||
{ |
||||
int ret_status = -1; |
||||
tx_send_loop = 0; |
||||
|
||||
/* Return error if no link */ |
||||
if (!phy.get_link_speed(active_phy_addr)) |
||||
{ |
||||
printf("WARN: emac_send_packet: No link\n"); |
||||
return (ret_status); |
||||
} |
||||
|
||||
/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ |
||||
if (length < EMAC_MIN_ETHERNET_PKT_SIZE) |
||||
{ |
||||
length = EMAC_MIN_ETHERNET_PKT_SIZE; |
||||
} |
||||
|
||||
/* Populate the TX descriptor */ |
||||
emac_tx_desc->next = 0; |
||||
emac_tx_desc->buffer = (u_int8_t *)packet; |
||||
emac_tx_desc->buff_off_len = (length & 0xffff); |
||||
emac_tx_desc->pkt_flag_len = ((length & 0xffff) | |
||||
EMAC_CPPI_SOP_BIT | |
||||
EMAC_CPPI_OWNERSHIP_BIT | |
||||
EMAC_CPPI_EOP_BIT); |
||||
/* Send the packet */ |
||||
adap_emac->TX0HDP = (unsigned int)emac_tx_desc; |
||||
|
||||
/* Wait for packet to complete or link down */ |
||||
while (1) { |
||||
if (!phy.get_link_speed(active_phy_addr)) { |
||||
dm644x_eth_ch_teardown(EMAC_CH_TX); |
||||
return (ret_status); |
||||
} |
||||
if (adap_emac->TXINTSTATRAW & 0x01) { |
||||
ret_status = length; |
||||
break; |
||||
} |
||||
tx_send_loop++; |
||||
} |
||||
|
||||
return(ret_status); |
||||
} |
||||
|
||||
/*
|
||||
* This function handles receipt of a packet from the network |
||||
*/ |
||||
static int dm644x_eth_rcv_packet(void) |
||||
{ |
||||
volatile emac_desc *rx_curr_desc; |
||||
volatile emac_desc *curr_desc; |
||||
volatile emac_desc *tail_desc; |
||||
int status, ret = -1; |
||||
|
||||
rx_curr_desc = emac_rx_active_head; |
||||
status = rx_curr_desc->pkt_flag_len; |
||||
if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { |
||||
if (status & EMAC_CPPI_RX_ERROR_FRAME) { |
||||
/* Error in packet - discard it and requeue desc */ |
||||
printf("WARN: emac_rcv_pkt: Error in packet\n"); |
||||
} else { |
||||
NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); |
||||
ret = rx_curr_desc->buff_off_len & 0xffff; |
||||
} |
||||
|
||||
/* Ack received packet descriptor */ |
||||
adap_emac->RX0CP = (unsigned int)rx_curr_desc; |
||||
curr_desc = rx_curr_desc; |
||||
emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; |
||||
|
||||
if (status & EMAC_CPPI_EOQ_BIT) { |
||||
if (emac_rx_active_head) { |
||||
adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; |
||||
} else { |
||||
emac_rx_queue_active = 0; |
||||
printf("INFO:emac_rcv_packet: RX Queue not active\n"); |
||||
} |
||||
} |
||||
|
||||
/* Recycle RX descriptor */ |
||||
rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; |
||||
rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; |
||||
rx_curr_desc->next = 0; |
||||
|
||||
if (emac_rx_active_head == 0) { |
||||
printf("INFO: emac_rcv_pkt: active queue head = 0\n"); |
||||
emac_rx_active_head = curr_desc; |
||||
emac_rx_active_tail = curr_desc; |
||||
if (emac_rx_queue_active != 0) { |
||||
adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; |
||||
printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); |
||||
emac_rx_queue_active = 1; |
||||
} |
||||
} else { |
||||
tail_desc = emac_rx_active_tail; |
||||
emac_rx_active_tail = curr_desc; |
||||
tail_desc->next = (unsigned int)curr_desc; |
||||
status = tail_desc->pkt_flag_len; |
||||
if (status & EMAC_CPPI_EOQ_BIT) { |
||||
adap_emac->RX0HDP = (unsigned int)curr_desc; |
||||
status &= ~EMAC_CPPI_EOQ_BIT; |
||||
tail_desc->pkt_flag_len = status; |
||||
} |
||||
} |
||||
return(ret); |
||||
} |
||||
return(0); |
||||
} |
||||
|
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
@ -0,0 +1,351 @@ |
||||
/*
|
||||
* TI DaVinci (TMS320DM644x) I2C driver. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* -------------------------------------------------------- |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_DAVINCI_I2C |
||||
|
||||
#include <i2c.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/i2c_defs.h> |
||||
|
||||
#define CHECK_NACK() \ |
||||
do {\
|
||||
if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
|
||||
REG(I2C_CON) = 0;\
|
||||
return(1);\
|
||||
}\
|
||||
} while (0) |
||||
|
||||
|
||||
static int wait_for_bus(void) |
||||
{ |
||||
int stat, timeout; |
||||
|
||||
REG(I2C_STAT) = 0xffff; |
||||
|
||||
for (timeout = 0; timeout < 10; timeout++) { |
||||
if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { |
||||
REG(I2C_STAT) = 0xffff; |
||||
return(0); |
||||
} |
||||
|
||||
REG(I2C_STAT) = stat; |
||||
udelay(50000); |
||||
} |
||||
|
||||
REG(I2C_STAT) = 0xffff; |
||||
return(1); |
||||
} |
||||
|
||||
|
||||
static int poll_i2c_irq(int mask) |
||||
{ |
||||
int stat, timeout; |
||||
|
||||
for (timeout = 0; timeout < 10; timeout++) { |
||||
udelay(1000); |
||||
stat = REG(I2C_STAT); |
||||
if (stat & mask) { |
||||
return(stat); |
||||
} |
||||
} |
||||
|
||||
REG(I2C_STAT) = 0xffff; |
||||
return(stat | I2C_TIMEOUT); |
||||
} |
||||
|
||||
|
||||
void flush_rx(void) |
||||
{ |
||||
int dummy; |
||||
|
||||
while (1) { |
||||
if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) |
||||
break; |
||||
|
||||
dummy = REG(I2C_DRR); |
||||
REG(I2C_STAT) = I2C_STAT_RRDY; |
||||
udelay(1000); |
||||
} |
||||
} |
||||
|
||||
|
||||
void i2c_init(int speed, int slaveadd) |
||||
{ |
||||
u_int32_t div, psc; |
||||
|
||||
if (REG(I2C_CON) & I2C_CON_EN) { |
||||
REG(I2C_CON) = 0; |
||||
udelay (50000); |
||||
} |
||||
|
||||
psc = 2; |
||||
div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ |
||||
REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ |
||||
REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ |
||||
REG(I2C_SCLH) = div - REG(I2C_SCLL); |
||||
|
||||
REG(I2C_OA) = slaveadd; |
||||
REG(I2C_CNT) = 0; |
||||
|
||||
/* Interrupts must be enabled or I2C module won't work */ |
||||
REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | |
||||
I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; |
||||
|
||||
/* Now enable I2C controller (get it out of reset) */ |
||||
REG(I2C_CON) = I2C_CON_EN; |
||||
|
||||
udelay(1000); |
||||
} |
||||
|
||||
|
||||
int i2c_probe(u_int8_t chip) |
||||
{ |
||||
int rc = 1; |
||||
|
||||
if (chip == REG(I2C_OA)) { |
||||
return(rc); |
||||
} |
||||
|
||||
REG(I2C_CON) = 0; |
||||
if (wait_for_bus()) {return(1);} |
||||
|
||||
/* try to read one byte from current (or only) address */ |
||||
REG(I2C_CNT) = 1; |
||||
REG(I2C_SA) = chip; |
||||
REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); |
||||
udelay (50000); |
||||
|
||||
if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { |
||||
rc = 0; |
||||
flush_rx(); |
||||
REG(I2C_STAT) = 0xffff; |
||||
} else { |
||||
REG(I2C_STAT) = 0xffff; |
||||
REG(I2C_CON) |= I2C_CON_STP; |
||||
udelay(20000); |
||||
if (wait_for_bus()) {return(1);} |
||||
} |
||||
|
||||
flush_rx(); |
||||
REG(I2C_STAT) = 0xffff; |
||||
REG(I2C_CNT) = 0; |
||||
return(rc); |
||||
} |
||||
|
||||
|
||||
int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) |
||||
{ |
||||
u_int32_t tmp; |
||||
int i; |
||||
|
||||
if ((alen < 0) || (alen > 2)) { |
||||
printf("%s(): bogus address length %x\n", __FUNCTION__, alen); |
||||
return(1); |
||||
} |
||||
|
||||
if (wait_for_bus()) {return(1);} |
||||
|
||||
if (alen != 0) { |
||||
/* Start address phase */ |
||||
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; |
||||
REG(I2C_CNT) = alen; |
||||
REG(I2C_SA) = chip; |
||||
REG(I2C_CON) = tmp; |
||||
|
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
switch (alen) { |
||||
case 2: |
||||
/* Send address MSByte */ |
||||
if (tmp & I2C_STAT_XRDY) { |
||||
REG(I2C_DXR) = (addr >> 8) & 0xff; |
||||
} else { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
|
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
/* No break, fall through */ |
||||
case 1: |
||||
/* Send address LSByte */ |
||||
if (tmp & I2C_STAT_XRDY) { |
||||
REG(I2C_DXR) = addr & 0xff; |
||||
} else { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
|
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (!(tmp & I2C_STAT_ARDY)) { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Address phase is over, now read 'len' bytes and stop */ |
||||
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; |
||||
REG(I2C_CNT) = len & 0xffff; |
||||
REG(I2C_SA) = chip; |
||||
REG(I2C_CON) = tmp; |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (tmp & I2C_STAT_RRDY) { |
||||
buf[i] = REG(I2C_DRR); |
||||
} else { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
} |
||||
|
||||
tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (!(tmp & I2C_STAT_SCD)) { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
|
||||
flush_rx(); |
||||
REG(I2C_STAT) = 0xffff; |
||||
REG(I2C_CNT) = 0; |
||||
REG(I2C_CON) = 0; |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
|
||||
int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) |
||||
{ |
||||
u_int32_t tmp; |
||||
int i; |
||||
|
||||
if ((alen < 0) || (alen > 2)) { |
||||
printf("%s(): bogus address length %x\n", __FUNCTION__, alen); |
||||
return(1); |
||||
} |
||||
if (len < 0) { |
||||
printf("%s(): bogus length %x\n", __FUNCTION__, len); |
||||
return(1); |
||||
} |
||||
|
||||
if (wait_for_bus()) {return(1);} |
||||
|
||||
/* Start address phase */ |
||||
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; |
||||
REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; |
||||
REG(I2C_SA) = chip; |
||||
REG(I2C_CON) = tmp; |
||||
|
||||
switch (alen) { |
||||
case 2: |
||||
/* Send address MSByte */ |
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (tmp & I2C_STAT_XRDY) { |
||||
REG(I2C_DXR) = (addr >> 8) & 0xff; |
||||
} else { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
/* No break, fall through */ |
||||
case 1: |
||||
/* Send address LSByte */ |
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (tmp & I2C_STAT_XRDY) { |
||||
REG(I2C_DXR) = addr & 0xff; |
||||
} else { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
} |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (tmp & I2C_STAT_XRDY) { |
||||
REG(I2C_DXR) = buf[i]; |
||||
} else { |
||||
return(1); |
||||
} |
||||
} |
||||
|
||||
tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); |
||||
|
||||
CHECK_NACK(); |
||||
|
||||
if (!(tmp & I2C_STAT_SCD)) { |
||||
REG(I2C_CON) = 0; |
||||
return(1); |
||||
} |
||||
|
||||
flush_rx(); |
||||
REG(I2C_STAT) = 0xffff; |
||||
REG(I2C_CNT) = 0; |
||||
REG(I2C_CON) = 0; |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
|
||||
u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) |
||||
{ |
||||
u_int8_t tmp; |
||||
|
||||
i2c_read(chip, reg, 1, &tmp, 1); |
||||
return(tmp); |
||||
} |
||||
|
||||
|
||||
void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) |
||||
{ |
||||
u_int8_t tmp; |
||||
|
||||
i2c_write(chip, reg, 1, &tmp, 1); |
||||
} |
||||
|
||||
#endif /* CONFIG_DRIVER_DAVINCI_I2C */ |
@ -0,0 +1,707 @@ |
||||
/* |
||||
* Low-level board setup code for TI DaVinci SoC based boards. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
* |
||||
* Partially based on TI sources, original copyrights follow: |
||||
*/ |
||||
|
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
* |
||||
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 |
||||
* |
||||
* Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* Modified for DV-EVM board by Swaminathan S, Nov 2005 |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/*-------------------------------------------------------* |
||||
* Mask all IRQs by setting all bits in the EINT default * |
||||
*-------------------------------------------------------*/ |
||||
mov r1, $0 |
||||
ldr r0, =EINT_ENABLE0 |
||||
str r1, [r0] |
||||
ldr r0, =EINT_ENABLE1 |
||||
str r1, [r0] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Put the GEM in reset * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Put the GEM in reset */ |
||||
ldr r8, PSC_GEM_FLAG_CLEAR |
||||
ldr r6, MDCTL_GEM |
||||
ldr r7, [r6] |
||||
and r7, r7, r8 |
||||
str r7, [r6] |
||||
|
||||
/* Enable the Power Domain Transition Command */ |
||||
ldr r6, PTCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x02 |
||||
str r7, [r6] |
||||
|
||||
/* Check for Transition Complete(PTSTAT) */ |
||||
checkStatClkStopGem: |
||||
ldr r6, PTSTAT |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x02 |
||||
bne checkStatClkStopGem |
||||
|
||||
/* Check for GEM Reset Completion */ |
||||
checkGemStatClkStop: |
||||
ldr r6, MDSTAT_GEM |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x100 |
||||
bne checkGemStatClkStop |
||||
|
||||
/* Do this for enabling a WDT initiated reset this is a workaround |
||||
for a chip bug. Not required under normal situations */ |
||||
ldr r6, P1394 |
||||
mov r10, $0 |
||||
str r10, [r6] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Enable L1 & L2 Memories in Fast mode * |
||||
*------------------------------------------------------*/ |
||||
ldr r6, DFT_ENABLE |
||||
mov r10, $0x01 |
||||
str r10, [r6] |
||||
|
||||
ldr r6, MMARG_BRF0 |
||||
ldr r10, MMARG_BRF0_VAL |
||||
str r10, [r6] |
||||
|
||||
ldr r6, DFT_ENABLE |
||||
mov r10, $0 |
||||
str r10, [r6] |
||||
|
||||
/*------------------------------------------------------* |
||||
* DDR2 PLL Initialization * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ |
||||
mov r10, $0 |
||||
ldr r6, PLL2_CTL |
||||
ldr r7, PLL_CLKSRC_MASK |
||||
ldr r8, [r6] |
||||
and r8, r8, r7 |
||||
mov r9, r10, lsl $8 |
||||
orr r8, r8, r9 |
||||
str r8, [r6] |
||||
|
||||
/* Select the PLLEN source */ |
||||
ldr r7, PLL_ENSRC_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Bypass the PLL */ |
||||
ldr r7, PLL_BYPASS_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ |
||||
mov r10, $0x20 |
||||
WaitPPL2Loop: |
||||
subs r10, r10, $1 |
||||
bne WaitPPL2Loop |
||||
|
||||
/* Reset the PLL */ |
||||
ldr r7, PLL_RESET_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Power up the PLL */ |
||||
ldr r7, PLL_PWRUP_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Enable the PLL from Disable Mode */ |
||||
ldr r7, PLL_DISABLE_ENABLE_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Program the PLL Multiplier */ |
||||
ldr r6, PLL2_PLLM |
||||
mov r2, $0x17 /* 162 MHz */ |
||||
str r2, [r6] |
||||
|
||||
/* Program the PLL2 Divisor Value */ |
||||
ldr r6, PLL2_DIV2 |
||||
mov r3, $0x01 |
||||
str r3, [r6] |
||||
|
||||
/* Program the PLL2 Divisor Value */ |
||||
ldr r6, PLL2_DIV1 |
||||
mov r4, $0x0b /* 54 MHz */ |
||||
str r4, [r6] |
||||
|
||||
/* PLL2 DIV2 MMR */ |
||||
ldr r8, PLL2_DIV_MASK |
||||
ldr r6, PLL2_DIV2 |
||||
ldr r9, [r6] |
||||
and r8, r8, r9 |
||||
mov r9, $0x01 |
||||
mov r9, r9, lsl $15 |
||||
orr r8, r8, r9 |
||||
str r8, [r6] |
||||
|
||||
/* Program the GOSET bit to take new divider values */ |
||||
ldr r6, PLL2_PLLCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Wait for Done */ |
||||
ldr r6, PLL2_PLLSTAT |
||||
doneLoop_0: |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x01 |
||||
bne doneLoop_0 |
||||
|
||||
/* PLL2 DIV1 MMR */ |
||||
ldr r8, PLL2_DIV_MASK |
||||
ldr r6, PLL2_DIV1 |
||||
ldr r9, [r6] |
||||
and r8, r8, r9 |
||||
mov r9, $0x01 |
||||
mov r9, r9, lsl $15 |
||||
orr r8, r8, r9 |
||||
str r8, [r6] |
||||
|
||||
/* Program the GOSET bit to take new divider values */ |
||||
ldr r6, PLL2_PLLCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Wait for Done */ |
||||
ldr r6, PLL2_PLLSTAT |
||||
doneLoop: |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x01 |
||||
bne doneLoop |
||||
|
||||
/* Wait for PLL to Reset Properly */ |
||||
mov r10, $0x218 |
||||
ResetPPL2Loop: |
||||
subs r10, r10, $1 |
||||
bne ResetPPL2Loop |
||||
|
||||
/* Bring PLL out of Reset */ |
||||
ldr r6, PLL2_CTL |
||||
ldr r8, [r6] |
||||
orr r8, r8, $0x08 |
||||
str r8, [r6] |
||||
|
||||
/* Wait for PLL to Lock */ |
||||
ldr r10, PLL_LOCK_COUNT |
||||
PLL2Lock: |
||||
subs r10, r10, $1 |
||||
bne PLL2Lock |
||||
|
||||
/* Enable the PLL */ |
||||
ldr r6, PLL2_CTL |
||||
ldr r8, [r6] |
||||
orr r8, r8, $0x01 |
||||
str r8, [r6] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Issue Soft Reset to DDR Module * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Shut down the DDR2 LPSC Module */ |
||||
ldr r8, PSC_FLAG_CLEAR |
||||
ldr r6, MDCTL_DDR2 |
||||
ldr r7, [r6] |
||||
and r7, r7, r8 |
||||
orr r7, r7, $0x03 |
||||
str r7, [r6] |
||||
|
||||
/* Enable the Power Domain Transition Command */ |
||||
ldr r6, PTCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Check for Transition Complete(PTSTAT) */ |
||||
checkStatClkStop: |
||||
ldr r6, PTSTAT |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x01 |
||||
bne checkStatClkStop |
||||
|
||||
/* Check for DDR2 Controller Enable Completion */ |
||||
checkDDRStatClkStop: |
||||
ldr r6, MDSTAT_DDR2 |
||||
ldr r7, [r6] |
||||
and r7, r7, $0x1f |
||||
cmp r7, $0x03 |
||||
bne checkDDRStatClkStop |
||||
|
||||
/*------------------------------------------------------* |
||||
* Program DDR2 MMRs for 162MHz Setting * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Program PHY Control Register */ |
||||
ldr r6, DDRCTL |
||||
ldr r7, DDRCTL_VAL |
||||
str r7, [r6] |
||||
|
||||
/* Program SDRAM Bank Config Register */ |
||||
ldr r6, SDCFG |
||||
ldr r7, SDCFG_VAL |
||||
str r7, [r6] |
||||
|
||||
/* Program SDRAM TIM-0 Config Register */ |
||||
ldr r6, SDTIM0 |
||||
ldr r7, SDTIM0_VAL_162MHz |
||||
str r7, [r6] |
||||
|
||||
/* Program SDRAM TIM-1 Config Register */ |
||||
ldr r6, SDTIM1 |
||||
ldr r7, SDTIM1_VAL_162MHz |
||||
str r7, [r6] |
||||
|
||||
/* Program the SDRAM Bank Config Control Register */ |
||||
ldr r10, MASK_VAL |
||||
ldr r8, SDCFG |
||||
ldr r9, SDCFG_VAL |
||||
and r9, r9, r10 |
||||
str r9, [r8] |
||||
|
||||
/* Program SDRAM SDREF Config Register */ |
||||
ldr r6, SDREF |
||||
ldr r7, SDREF_VAL |
||||
str r7, [r6] |
||||
|
||||
/*------------------------------------------------------* |
||||
* Issue Soft Reset to DDR Module * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Issue a Dummy DDR2 read/write */ |
||||
ldr r8, DDR2_START_ADDR |
||||
ldr r7, DUMMY_VAL |
||||
str r7, [r8] |
||||
ldr r7, [r8] |
||||
|
||||
/* Shut down the DDR2 LPSC Module */ |
||||
ldr r8, PSC_FLAG_CLEAR |
||||
ldr r6, MDCTL_DDR2 |
||||
ldr r7, [r6] |
||||
and r7, r7, r8 |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Enable the Power Domain Transition Command */ |
||||
ldr r6, PTCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Check for Transition Complete(PTSTAT) */ |
||||
checkStatClkStop2: |
||||
ldr r6, PTSTAT |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x01 |
||||
bne checkStatClkStop2 |
||||
|
||||
/* Check for DDR2 Controller Enable Completion */ |
||||
checkDDRStatClkStop2: |
||||
ldr r6, MDSTAT_DDR2 |
||||
ldr r7, [r6] |
||||
and r7, r7, $0x1f |
||||
cmp r7, $0x01 |
||||
bne checkDDRStatClkStop2 |
||||
|
||||
/*------------------------------------------------------* |
||||
* Turn DDR2 Controller Clocks On * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Enable the DDR2 LPSC Module */ |
||||
ldr r6, MDCTL_DDR2 |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x03 |
||||
str r7, [r6] |
||||
|
||||
/* Enable the Power Domain Transition Command */ |
||||
ldr r6, PTCMD |
||||
ldr r7, [r6] |
||||
orr r7, r7, $0x01 |
||||
str r7, [r6] |
||||
|
||||
/* Check for Transition Complete(PTSTAT) */ |
||||
checkStatClkEn2: |
||||
ldr r6, PTSTAT |
||||
ldr r7, [r6] |
||||
ands r7, r7, $0x01 |
||||
bne checkStatClkEn2 |
||||
|
||||
/* Check for DDR2 Controller Enable Completion */ |
||||
checkDDRStatClkEn2: |
||||
ldr r6, MDSTAT_DDR2 |
||||
ldr r7, [r6] |
||||
and r7, r7, $0x1f |
||||
cmp r7, $0x03 |
||||
bne checkDDRStatClkEn2 |
||||
|
||||
/* DDR Writes and Reads */ |
||||
ldr r6, CFGTEST |
||||
mov r3, $0x01 |
||||
str r3, [r6] |
||||
|
||||
/*------------------------------------------------------* |
||||
* System PLL Initialization * |
||||
*------------------------------------------------------*/ |
||||
|
||||
/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ |
||||
mov r2, $0 |
||||
ldr r6, PLL1_CTL |
||||
ldr r7, PLL_CLKSRC_MASK |
||||
ldr r8, [r6] |
||||
and r8, r8, r7 |
||||
mov r9, r2, lsl $8 |
||||
orr r8, r8, r9 |
||||
str r8, [r6] |
||||
|
||||
/* Select the PLLEN source */ |
||||
ldr r7, PLL_ENSRC_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Bypass the PLL */ |
||||
ldr r7, PLL_BYPASS_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ |
||||
mov r10, $0x20 |
||||
|
||||
WaitLoop: |
||||
subs r10, r10, $1 |
||||
bne WaitLoop |
||||
|
||||
/* Reset the PLL */ |
||||
ldr r7, PLL_RESET_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Disable the PLL */ |
||||
orr r8, r8, $0x10 |
||||
str r8, [r6] |
||||
|
||||
/* Power up the PLL */ |
||||
ldr r7, PLL_PWRUP_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Enable the PLL from Disable Mode */ |
||||
ldr r7, PLL_DISABLE_ENABLE_MASK |
||||
and r8, r8, r7 |
||||
str r8, [r6] |
||||
|
||||
/* Program the PLL Multiplier */ |
||||
ldr r6, PLL1_PLLM |
||||
mov r3, $0x15 /* For 594MHz */ |
||||
str r3, [r6] |
||||
|
||||
/* Wait for PLL to Reset Properly */ |
||||
mov r10, $0xff |
||||
|
||||
ResetLoop: |
||||
subs r10, r10, $1 |
||||
bne ResetLoop |
||||
|
||||
/* Bring PLL out of Reset */ |
||||
ldr r6, PLL1_CTL |
||||
orr r8, r8, $0x08 |
||||
str r8, [r6] |
||||
|
||||
/* Wait for PLL to Lock */ |
||||
ldr r10, PLL_LOCK_COUNT |
||||
|
||||
PLL1Lock: |
||||
subs r10, r10, $1 |
||||
bne PLL1Lock |
||||
|
||||
/* Enable the PLL */ |
||||
orr r8, r8, $0x01 |
||||
str r8, [r6] |
||||
|
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
/*------------------------------------------------------* |
||||
* AEMIF configuration for NOR Flash (double check) * |
||||
*------------------------------------------------------*/ |
||||
ldr r0, _PINMUX0 |
||||
ldr r1, _DEV_SETTING |
||||
str r1, [r0] |
||||
|
||||
ldr r0, WAITCFG |
||||
ldr r1, WAITCFG_VAL |
||||
ldr r2, [r0] |
||||
orr r2, r2, r1 |
||||
str r2, [r0] |
||||
|
||||
ldr r0, ACFG3 |
||||
ldr r1, ACFG3_VAL |
||||
ldr r2, [r0] |
||||
and r1, r2, r1 |
||||
str r1, [r0] |
||||
|
||||
ldr r0, ACFG4 |
||||
ldr r1, ACFG4_VAL |
||||
ldr r2, [r0] |
||||
and r1, r2, r1 |
||||
str r1, [r0] |
||||
|
||||
ldr r0, ACFG5 |
||||
ldr r1, ACFG5_VAL |
||||
ldr r2, [r0] |
||||
and r1, r2, r1 |
||||
str r1, [r0] |
||||
|
||||
/*--------------------------------------* |
||||
* VTP manual Calibration * |
||||
*--------------------------------------*/ |
||||
ldr r0, VTPIOCR |
||||
ldr r1, VTP_MMR0 |
||||
str r1, [r0] |
||||
|
||||
ldr r0, VTPIOCR |
||||
ldr r1, VTP_MMR1 |
||||
str r1, [r0] |
||||
|
||||
/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ |
||||
ldr r10, VTP_LOCK_COUNT |
||||
VTPLock: |
||||
subs r10, r10, $1 |
||||
bne VTPLock |
||||
|
||||
ldr r6, DFT_ENABLE |
||||
mov r10, $0x01 |
||||
str r10, [r6] |
||||
|
||||
ldr r6, DDRVTPR |
||||
ldr r7, [r6] |
||||
and r7, r7, $0x1f |
||||
and r8, r7, $0x3e0 |
||||
orr r8, r7, r8 |
||||
ldr r7, VTP_RECAL |
||||
orr r8, r7, r8 |
||||
ldr r7, VTP_EN |
||||
orr r8, r7, r8 |
||||
str r8, [r0] |
||||
|
||||
|
||||
/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ |
||||
ldr r10, VTP_LOCK_COUNT |
||||
VTP1Lock: |
||||
subs r10, r10, $1 |
||||
bne VTP1Lock |
||||
|
||||
ldr r1, [r0] |
||||
ldr r2, VTP_MASK |
||||
and r2, r1, r2 |
||||
str r2, [r0] |
||||
|
||||
ldr r6, DFT_ENABLE |
||||
mov r10, $0 |
||||
str r10, [r6] |
||||
|
||||
/*
|
||||
* Call board-specific lowlevel init. |
||||
* That MUST be present and THAT returns |
||||
* back to arch calling code with "mov pc, lr." |
||||
*/ |
||||
b dv_board_init |
||||
|
||||
.ltorg |
||||
|
||||
_PINMUX0: |
||||
.word 0x01c40000 /* Device Configuration Registers */ |
||||
_PINMUX1: |
||||
.word 0x01c40004 /* Device Configuration Registers */ |
||||
|
||||
_DEV_SETTING: |
||||
.word 0x00000c1f
|
||||
|
||||
WAITCFG: |
||||
.word 0x01e00004
|
||||
WAITCFG_VAL: |
||||
.word 0
|
||||
ACFG3: |
||||
.word 0x01e00014
|
||||
ACFG3_VAL: |
||||
.word 0x3ffffffd
|
||||
ACFG4: |
||||
.word 0x01e00018
|
||||
ACFG4_VAL: |
||||
.word 0x3ffffffd
|
||||
ACFG5: |
||||
.word 0x01e0001c
|
||||
ACFG5_VAL: |
||||
.word 0x3ffffffd
|
||||
|
||||
MDCTL_DDR2: |
||||
.word 0x01c41a34
|
||||
MDSTAT_DDR2: |
||||
.word 0x01c41834
|
||||
|
||||
PTCMD: |
||||
.word 0x01c41120
|
||||
PTSTAT: |
||||
.word 0x01c41128
|
||||
|
||||
EINT_ENABLE0: |
||||
.word 0x01c48018
|
||||
EINT_ENABLE1: |
||||
.word 0x01c4801c
|
||||
|
||||
PSC_FLAG_CLEAR: |
||||
.word 0xffffffe0
|
||||
PSC_GEM_FLAG_CLEAR: |
||||
.word 0xfffffeff
|
||||
|
||||
/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ |
||||
DDRCTL: |
||||
.word 0x200000e4
|
||||
DDRCTL_VAL: |
||||
.word 0x50006405
|
||||
SDREF: |
||||
.word 0x2000000c
|
||||
SDREF_VAL: |
||||
.word 0x000005c3
|
||||
SDCFG: |
||||
.word 0x20000008
|
||||
SDCFG_VAL: |
||||
#ifdef DDR_4BANKS |
||||
.word 0x00178622
|
||||
#elif defined DDR_8BANKS |
||||
.word 0x00178632
|
||||
#else |
||||
#error "Unknown DDR configuration!!!" |
||||
#endif |
||||
SDTIM0: |
||||
.word 0x20000010
|
||||
SDTIM0_VAL_162MHz: |
||||
.word 0x28923211
|
||||
SDTIM1: |
||||
.word 0x20000014
|
||||
SDTIM1_VAL_162MHz: |
||||
.word 0x0016c722
|
||||
VTPIOCR: |
||||
.word 0x200000f0 /* VTP IO Control register */ |
||||
DDRVTPR: |
||||
.word 0x01c42030 /* DDR VPTR MMR */ |
||||
VTP_MMR0: |
||||
.word 0x201f
|
||||
VTP_MMR1: |
||||
.word 0xa01f
|
||||
DFT_ENABLE: |
||||
.word 0x01c4004c
|
||||
VTP_LOCK_COUNT: |
||||
.word 0x5b0
|
||||
VTP_MASK: |
||||
.word 0xffffdfff
|
||||
VTP_RECAL: |
||||
.word 0x40000
|
||||
VTP_EN: |
||||
.word 0x02000
|
||||
CFGTEST: |
||||
.word 0x80010000
|
||||
MASK_VAL: |
||||
.word 0x00000fff
|
||||
|
||||
/* GEM Power Up & LPSC Control Register */ |
||||
MDCTL_GEM: |
||||
.word 0x01c41a9c
|
||||
MDSTAT_GEM: |
||||
.word 0x01c4189c
|
||||
|
||||
/* For WDT reset chip bug */ |
||||
P1394: |
||||
.word 0x01c41a20
|
||||
|
||||
PLL_CLKSRC_MASK: |
||||
.word 0xfffffeff /* Mask the Clock Mode bit */ |
||||
PLL_ENSRC_MASK: |
||||
.word 0xffffffdf /* Select the PLLEN source */ |
||||
PLL_BYPASS_MASK: |
||||
.word 0xfffffffe /* Put the PLL in BYPASS */ |
||||
PLL_RESET_MASK: |
||||
.word 0xfffffff7 /* Put the PLL in Reset Mode */ |
||||
PLL_PWRUP_MASK: |
||||
.word 0xfffffffd /* PLL Power up Mask Bit */ |
||||
PLL_DISABLE_ENABLE_MASK: |
||||
.word 0xffffffef /* Enable the PLL from Disable */ |
||||
PLL_LOCK_COUNT: |
||||
.word 0x2000
|
||||
|
||||
/* PLL1-SYSTEM PLL MMRs */ |
||||
PLL1_CTL: |
||||
.word 0x01c40900
|
||||
PLL1_PLLM: |
||||
.word 0x01c40910
|
||||
|
||||
/* PLL2-SYSTEM PLL MMRs */ |
||||
PLL2_CTL: |
||||
.word 0x01c40d00
|
||||
PLL2_PLLM: |
||||
.word 0x01c40d10
|
||||
PLL2_DIV1: |
||||
.word 0x01c40d18
|
||||
PLL2_DIV2: |
||||
.word 0x01c40d1c
|
||||
PLL2_PLLCMD: |
||||
.word 0x01c40d38
|
||||
PLL2_PLLSTAT: |
||||
.word 0x01c40d3c
|
||||
PLL2_DIV_MASK: |
||||
.word 0xffff7fff
|
||||
|
||||
MMARG_BRF0: |
||||
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/ |
||||
MMARG_BRF0_VAL: |
||||
.word 0x00444400
|
||||
|
||||
DDR2_START_ADDR: |
||||
.word 0x80000000
|
||||
DUMMY_VAL: |
||||
.word 0xa55aa55a
|
@ -0,0 +1,142 @@ |
||||
/*
|
||||
* Intel LXT971/LXT972 PHY Driver for TI DaVinci |
||||
* (TMS320DM644x) based boards. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* -------------------------------------------------------- |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <net.h> |
||||
#include <lxt971a.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
|
||||
int lxt972_is_phy_connected(int phy_addr) |
||||
{ |
||||
u_int16_t id1, id2; |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) |
||||
return(0); |
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) |
||||
return(0); |
||||
|
||||
if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) |
||||
return(1); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
int lxt972_get_link_speed(int phy_addr) |
||||
{ |
||||
u_int16_t stat1, tmp; |
||||
volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) |
||||
return(0); |
||||
|
||||
if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ |
||||
return(0); |
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) |
||||
return(0); |
||||
|
||||
tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; |
||||
|
||||
dm644x_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); |
||||
/* Read back */ |
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) |
||||
return(0); |
||||
|
||||
|
||||
/* Speed doesn't matter, there is no setting for it in EMAC... */ |
||||
if (stat1 & PHY_LXT971_STAT2_100BTX) { |
||||
if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { |
||||
/* set DM644x EMAC for Full Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; |
||||
} else { |
||||
/*set DM644x EMAC for Half Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; |
||||
} |
||||
|
||||
return(1); |
||||
} else { |
||||
if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { |
||||
/* set DM644x EMAC for Full Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; |
||||
} else { |
||||
/*set DM644x EMAC for Half Duplex */ |
||||
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; |
||||
} |
||||
|
||||
return(1); |
||||
} |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
|
||||
int lxt972_init_phy(int phy_addr) |
||||
{ |
||||
int ret = 1; |
||||
|
||||
if (!lxt972_get_link_speed(phy_addr)) { |
||||
/* Try another time */ |
||||
ret = lxt972_get_link_speed(phy_addr); |
||||
} |
||||
|
||||
/* Disable PHY Interrupts */ |
||||
dm644x_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); |
||||
|
||||
return(ret); |
||||
} |
||||
|
||||
|
||||
int lxt972_auto_negotiate(int phy_addr) |
||||
{ |
||||
u_int16_t tmp; |
||||
|
||||
|
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) |
||||
return(0); |
||||
|
||||
/* Restart Auto_negotiation */ |
||||
tmp |= PHY_COMMON_CTRL_RES_AUTO; |
||||
dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); |
||||
|
||||
/*check AutoNegotiate complete */ |
||||
udelay (10000); |
||||
if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) |
||||
return(0); |
||||
|
||||
if (!(tmp & PHY_COMMON_STAT_AN_COMP)) |
||||
return(0); |
||||
|
||||
return (lxt972_get_link_speed(phy_addr)); |
||||
} |
||||
|
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
#endif /* CONFIG_DRIVER_ETHER */ |
@ -0,0 +1,389 @@ |
||||
/*
|
||||
* NAND driver for TI DaVinci based boards. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Based on Linux DaVinci NAND driver by TI. Original copyright follows: |
||||
*/ |
||||
|
||||
/*
|
||||
* |
||||
* linux/drivers/mtd/nand/nand_davinci.c |
||||
* |
||||
* NAND Flash Driver |
||||
* |
||||
* Copyright (C) 2006 Texas Instruments. |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* Overview: |
||||
* This is a device driver for the NAND flash device found on the |
||||
* DaVinci board which utilizes the Samsung k9k2g08 part. |
||||
* |
||||
Modifications: |
||||
ver. 1.0: Feb 2005, Vinod/Sudhakar |
||||
- |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CFG_USE_NAND |
||||
#if !defined(CFG_NAND_LEGACY) |
||||
|
||||
#include <nand.h> |
||||
#include <asm/arch/nand_defs.h> |
||||
#include <asm/arch/emif_defs.h> |
||||
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; |
||||
|
||||
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; |
||||
|
||||
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
||||
|
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
IO_ADDR_W |= MASK_CLE; |
||||
break; |
||||
case NAND_CTL_SETALE: |
||||
IO_ADDR_W |= MASK_ALE; |
||||
break; |
||||
} |
||||
|
||||
this->IO_ADDR_W = (void *)IO_ADDR_W; |
||||
} |
||||
|
||||
/* Set WP on deselect, write enable on select */ |
||||
static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) |
||||
{ |
||||
#define GPIO_SET_DATA01 0x01c67018 |
||||
#define GPIO_CLR_DATA01 0x01c6701c |
||||
#define GPIO_NAND_WP (1 << 4) |
||||
#ifdef SONATA_BOARD_GPIOWP |
||||
if (chip < 0) { |
||||
REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; |
||||
} else { |
||||
REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; |
||||
} |
||||
#endif |
||||
} |
||||
|
||||
#ifdef CFG_NAND_HW_ECC |
||||
#ifdef CFG_NAND_LARGEPAGE |
||||
static struct nand_oobinfo davinci_nand_oobinfo = { |
||||
.useecc = MTD_NANDECC_AUTOPLACE, |
||||
.eccbytes = 12, |
||||
.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, |
||||
.oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} } |
||||
}; |
||||
#elif defined(CFG_NAND_SMALLPAGE) |
||||
static struct nand_oobinfo davinci_nand_oobinfo = { |
||||
.useecc = MTD_NANDECC_AUTOPLACE, |
||||
.eccbytes = 3, |
||||
.eccpos = {0, 1, 2}, |
||||
.oobfree = { {6, 2}, {8, 8} } |
||||
}; |
||||
#else |
||||
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" |
||||
#endif |
||||
|
||||
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) |
||||
{ |
||||
emifregs emif_addr; |
||||
int dummy; |
||||
|
||||
emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
||||
|
||||
dummy = emif_addr->NANDF1ECC; |
||||
dummy = emif_addr->NANDF2ECC; |
||||
dummy = emif_addr->NANDF3ECC; |
||||
dummy = emif_addr->NANDF4ECC; |
||||
|
||||
emif_addr->NANDFCR |= (1 << 8); |
||||
} |
||||
|
||||
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) |
||||
{ |
||||
u_int32_t ecc = 0; |
||||
emifregs emif_base_addr; |
||||
|
||||
emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
||||
|
||||
if (region == 1) |
||||
ecc = emif_base_addr->NANDF1ECC; |
||||
else if (region == 2) |
||||
ecc = emif_base_addr->NANDF2ECC; |
||||
else if (region == 3) |
||||
ecc = emif_base_addr->NANDF3ECC; |
||||
else if (region == 4) |
||||
ecc = emif_base_addr->NANDF4ECC; |
||||
|
||||
return(ecc); |
||||
} |
||||
|
||||
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
||||
{ |
||||
u_int32_t tmp; |
||||
int region, n; |
||||
struct nand_chip *this = mtd->priv; |
||||
|
||||
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; |
||||
|
||||
region = 1; |
||||
while (n--) { |
||||
tmp = nand_davinci_readecc(mtd, region); |
||||
*ecc_code++ = tmp; |
||||
*ecc_code++ = tmp >> 16; |
||||
*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); |
||||
region++; |
||||
} |
||||
return(0); |
||||
} |
||||
|
||||
static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) |
||||
{ |
||||
u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); |
||||
|
||||
ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); |
||||
ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); |
||||
ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); |
||||
} |
||||
|
||||
static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) |
||||
{ |
||||
u_int32_t i; |
||||
u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; |
||||
u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; |
||||
u_int8_t ecc_bit[24]; |
||||
u_int8_t ecc_sum = 0; |
||||
u_int8_t find_bit = 0; |
||||
u_int32_t find_byte = 0; |
||||
int is_ecc_ff; |
||||
|
||||
is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); |
||||
|
||||
nand_davinci_gen_true_ecc(ecc_nand); |
||||
nand_davinci_gen_true_ecc(ecc_calc); |
||||
|
||||
for (i = 0; i <= 2; i++) { |
||||
*(ecc_nand + i) = ~(*(ecc_nand + i)); |
||||
*(ecc_calc + i) = ~(*(ecc_calc + i)); |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
tmp0_bit[i] = *ecc_nand % 2; |
||||
*ecc_nand = *ecc_nand / 2; |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
tmp1_bit[i] = *(ecc_nand + 1) % 2; |
||||
*(ecc_nand + 1) = *(ecc_nand + 1) / 2; |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
tmp2_bit[i] = *(ecc_nand + 2) % 2; |
||||
*(ecc_nand + 2) = *(ecc_nand + 2) / 2; |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
comp0_bit[i] = *ecc_calc % 2; |
||||
*ecc_calc = *ecc_calc / 2; |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
comp1_bit[i] = *(ecc_calc + 1) % 2; |
||||
*(ecc_calc + 1) = *(ecc_calc + 1) / 2; |
||||
} |
||||
|
||||
for (i = 0; i < 8; i++) { |
||||
comp2_bit[i] = *(ecc_calc + 2) % 2; |
||||
*(ecc_calc + 2) = *(ecc_calc + 2) / 2; |
||||
} |
||||
|
||||
for (i = 0; i< 6; i++) |
||||
ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; |
||||
|
||||
for (i = 0; i < 8; i++) |
||||
ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; |
||||
|
||||
for (i = 0; i < 8; i++) |
||||
ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; |
||||
|
||||
ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; |
||||
ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; |
||||
|
||||
for (i = 0; i < 24; i++) |
||||
ecc_sum += ecc_bit[i]; |
||||
|
||||
switch (ecc_sum) { |
||||
case 0: |
||||
/* Not reached because this function is not called if
|
||||
ECC values are equal */ |
||||
return 0; |
||||
case 1: |
||||
/* Uncorrectable error */ |
||||
DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); |
||||
return(-1); |
||||
case 12: |
||||
/* Correctable error */ |
||||
find_byte = (ecc_bit[23] << 8) + |
||||
(ecc_bit[21] << 7) + |
||||
(ecc_bit[19] << 6) + |
||||
(ecc_bit[17] << 5) + |
||||
(ecc_bit[15] << 4) + |
||||
(ecc_bit[13] << 3) + |
||||
(ecc_bit[11] << 2) + |
||||
(ecc_bit[9] << 1) + |
||||
ecc_bit[7]; |
||||
|
||||
find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; |
||||
|
||||
DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); |
||||
|
||||
page_data[find_byte] ^= (1 << find_bit); |
||||
|
||||
return(0); |
||||
default: |
||||
if (is_ecc_ff) { |
||||
if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) |
||||
return(0); |
||||
} |
||||
DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); |
||||
return(-1); |
||||
} |
||||
} |
||||
|
||||
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) |
||||
{ |
||||
struct nand_chip *this; |
||||
int block_count = 0, i, rc; |
||||
|
||||
this = mtd->priv; |
||||
block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; |
||||
for (i = 0; i < block_count; i++) { |
||||
if (memcmp(read_ecc, calc_ecc, 3) != 0) { |
||||
rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); |
||||
if (rc < 0) { |
||||
return(rc); |
||||
} |
||||
} |
||||
read_ecc += 3; |
||||
calc_ecc += 3; |
||||
dat += 512; |
||||
} |
||||
return(0); |
||||
} |
||||
#endif |
||||
|
||||
static int nand_davinci_dev_ready(struct mtd_info *mtd) |
||||
{ |
||||
emifregs emif_addr; |
||||
|
||||
emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
||||
|
||||
return(emif_addr->NANDFSR & 0x1); |
||||
} |
||||
|
||||
static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state) |
||||
{ |
||||
while(!nand_davinci_dev_ready(mtd)) {;} |
||||
*NAND_CE0CLE = NAND_STATUS; |
||||
return(*NAND_CE0DATA); |
||||
} |
||||
|
||||
static void nand_flash_init(void) |
||||
{ |
||||
u_int32_t acfg1 = 0x3ffffffc; |
||||
u_int32_t acfg2 = 0x3ffffffc; |
||||
u_int32_t acfg3 = 0x3ffffffc; |
||||
u_int32_t acfg4 = 0x3ffffffc; |
||||
emifregs emif_regs; |
||||
|
||||
/*------------------------------------------------------------------*
|
||||
* NAND FLASH CHIP TIMEOUT @ 459 MHz * |
||||
* * |
||||
* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * |
||||
* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * |
||||
* * |
||||
*------------------------------------------------------------------*/ |
||||
acfg1 = 0 |
||||
| (0 << 31 ) /* selectStrobe */ |
||||
| (0 << 30 ) /* extWait */ |
||||
| (1 << 26 ) /* writeSetup 10 ns */ |
||||
| (3 << 20 ) /* writeStrobe 40 ns */ |
||||
| (1 << 17 ) /* writeHold 10 ns */ |
||||
| (1 << 13 ) /* readSetup 10 ns */ |
||||
| (5 << 7 ) /* readStrobe 60 ns */ |
||||
| (1 << 4 ) /* readHold 10 ns */ |
||||
| (3 << 2 ) /* turnAround ?? ns */ |
||||
| (0 << 0 ) /* asyncSize 8-bit bus */ |
||||
; |
||||
|
||||
emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
||||
|
||||
emif_regs->AWCCR |= 0x10000000; |
||||
emif_regs->AB1CR = acfg1; /* 0x08244128 */; |
||||
emif_regs->AB2CR = acfg2; |
||||
emif_regs->AB3CR = acfg3; |
||||
emif_regs->AB4CR = acfg4; |
||||
emif_regs->NANDFCR = 0x00000101; |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; |
||||
nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; |
||||
nand->chip_delay = 0; |
||||
nand->select_chip = nand_davinci_select_chip; |
||||
#ifdef CFG_NAND_USE_FLASH_BBT |
||||
nand->options = NAND_USE_FLASH_BBT; |
||||
#endif |
||||
#ifdef CFG_NAND_HW_ECC |
||||
#ifdef CFG_NAND_LARGEPAGE |
||||
nand->eccmode = NAND_ECC_HW12_2048; |
||||
#elif defined(CFG_NAND_SMALLPAGE) |
||||
nand->eccmode = NAND_ECC_HW3_512; |
||||
#else |
||||
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" |
||||
#endif |
||||
nand->autooob = &davinci_nand_oobinfo; |
||||
nand->calculate_ecc = nand_davinci_calculate_ecc; |
||||
nand->correct_data = nand_davinci_correct_data; |
||||
nand->enable_hwecc = nand_davinci_enable_hwecc; |
||||
#else |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
#endif |
||||
|
||||
/* Set address of hardware control function */ |
||||
nand->hwcontrol = nand_davinci_hwcontrol; |
||||
|
||||
nand->dev_ready = nand_davinci_dev_ready; |
||||
nand->waitfunc = nand_davinci_waitfunc; |
||||
|
||||
nand_flash_init(); |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
#else |
||||
#error "U-Boot legacy NAND support not available for DaVinci chips" |
||||
#endif |
||||
#endif /* CFG_USE_NAND */ |
@ -0,0 +1,77 @@ |
||||
/* |
||||
* Processor reset using WDT for TI TMS320DM644x SoC. |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
* |
||||
* ----------------------------------------------------- |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
.globl reset_cpu
|
||||
reset_cpu: |
||||
ldr r0, WDT_TGCR |
||||
mov r1, $0x08 |
||||
str r1, [r0] |
||||
ldr r1, [r0] |
||||
orr r1, r1, $0x03 |
||||
str r1, [r0] |
||||
mov r1, $0 |
||||
ldr r0, WDT_TIM12 |
||||
str r1, [r0] |
||||
ldr r0, WDT_TIM34 |
||||
str r1, [r0] |
||||
ldr r0, WDT_PRD12 |
||||
str r1, [r0] |
||||
ldr r0, WDT_PRD34 |
||||
str r1, [r0] |
||||
ldr r0, WDT_TCR |
||||
ldr r1, [r0] |
||||
orr r1, r1, $0x40 |
||||
str r1, [r0] |
||||
ldr r0, WDT_WDTCR |
||||
ldr r1, [r0] |
||||
orr r1, r1, $0x4000 |
||||
str r1, [r0] |
||||
ldr r1, WDTCR_VAL1 |
||||
str r1, [r0] |
||||
ldr r1, WDTCR_VAL2 |
||||
str r1, [r0] |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
reset_cpu_loop: |
||||
b reset_cpu_loop |
||||
|
||||
WDT_TGCR: |
||||
.word 0x01c21c24
|
||||
WDT_TIM12: |
||||
.word 0x01c21c10
|
||||
WDT_TIM34: |
||||
.word 0x01c21c14
|
||||
WDT_PRD12: |
||||
.word 0x01c21c18
|
||||
WDT_PRD34: |
||||
.word 0x01c21c1c
|
||||
WDT_TCR: |
||||
.word 0x01c21c20
|
||||
WDT_WDTCR: |
||||
.word 0x01c21c28
|
||||
WDTCR_VAL1: |
||||
.word 0xa5c64000
|
||||
WDTCR_VAL2: |
||||
.word 0xda7e4000
|
@ -0,0 +1,165 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments <www.ti.com> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002-2004 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com> |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <arm926ejs.h> |
||||
|
||||
typedef volatile struct { |
||||
u_int32_t pid12; |
||||
u_int32_t emumgt_clksped; |
||||
u_int32_t gpint_en; |
||||
u_int32_t gpdir_dat; |
||||
u_int32_t tim12; |
||||
u_int32_t tim34; |
||||
u_int32_t prd12; |
||||
u_int32_t prd34; |
||||
u_int32_t tcr; |
||||
u_int32_t tgcr; |
||||
u_int32_t wdtcr; |
||||
u_int32_t tlgc; |
||||
u_int32_t tlmr; |
||||
} davinci_timer; |
||||
|
||||
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; |
||||
|
||||
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) |
||||
#define READ_TIMER timer->tim34 |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastinc; |
||||
|
||||
int timer_init(void) |
||||
{ |
||||
/* We are using timer34 in unchained 32-bit mode, full speed */ |
||||
timer->tcr = 0x0; |
||||
timer->tgcr = 0x0; |
||||
timer->tgcr = 0x06; |
||||
timer->tim34 = 0x0; |
||||
timer->prd34 = TIMER_LOAD_VAL; |
||||
lastinc = 0; |
||||
timer->tcr = 0x80 << 16; |
||||
timestamp = 0; |
||||
|
||||
return(0); |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer(ulong base) |
||||
{ |
||||
return(get_timer_masked() - base); |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
void udelay(unsigned long usec) |
||||
{ |
||||
udelay_masked(usec); |
||||
} |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
lastinc = READ_TIMER; |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer_raw(void) |
||||
{ |
||||
ulong now = READ_TIMER; |
||||
|
||||
if (now >= lastinc) { |
||||
/* normal mode */ |
||||
timestamp += now - lastinc; |
||||
} else { |
||||
/* overflow ... */ |
||||
timestamp += now + TIMER_LOAD_VAL - lastinc; |
||||
} |
||||
lastinc = now; |
||||
return timestamp; |
||||
} |
||||
|
||||
ulong get_timer_masked(void) |
||||
{ |
||||
return(get_timer_raw() / TIMER_LOAD_VAL); |
||||
} |
||||
|
||||
void udelay_masked(unsigned long usec) |
||||
{ |
||||
ulong tmo; |
||||
ulong endtime; |
||||
signed long diff; |
||||
|
||||
tmo = CFG_HZ_CLOCK / 1000; |
||||
tmo *= usec; |
||||
tmo /= 1000; |
||||
|
||||
endtime = get_timer_raw() + tmo; |
||||
|
||||
do { |
||||
ulong now = get_timer_raw(); |
||||
diff = endtime - now; |
||||
} while (diff >= 0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
return(get_timer(0)); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk(void) |
||||
{ |
||||
ulong tbclk; |
||||
|
||||
tbclk = CFG_HZ; |
||||
return(tbclk); |
||||
} |
@ -0,0 +1,311 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Based on: |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* dm644x_emac.h |
||||
* |
||||
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM |
||||
* |
||||
* Copyright (C) 2005 Texas Instruments. |
||||
* |
||||
* ---------------------------------------------------------------------------- |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* ---------------------------------------------------------------------------- |
||||
|
||||
* Modifications: |
||||
* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _DM644X_EMAC_H_ |
||||
#define _DM644X_EMAC_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
#define EMAC_BASE_ADDR (0x01c80000) |
||||
#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) |
||||
#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) |
||||
#define EMAC_MDIO_BASE_ADDR (0x01c84000) |
||||
|
||||
/* MDIO module input frequency */ |
||||
#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ |
||||
/* MDIO clock output frequency */ |
||||
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ |
||||
|
||||
/* Ethernet Min/Max packet size */ |
||||
#define EMAC_MIN_ETHERNET_PKT_SIZE 60 |
||||
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 |
||||
#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ |
||||
|
||||
/* Number of RX packet buffers
|
||||
* NOTE: Only 1 buffer supported as of now |
||||
*/ |
||||
#define EMAC_MAX_RX_BUFFERS 10 |
||||
|
||||
|
||||
/***********************************************
|
||||
******** Internally used macros *************** |
||||
***********************************************/ |
||||
|
||||
#define EMAC_CH_TX 1 |
||||
#define EMAC_CH_RX 0 |
||||
|
||||
/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
|
||||
* reserve space for 64 descriptors max |
||||
*/ |
||||
#define EMAC_RX_DESC_BASE 0x0 |
||||
#define EMAC_TX_DESC_BASE 0x1000 |
||||
|
||||
/* EMAC Teardown value */ |
||||
#define EMAC_TEARDOWN_VALUE 0xfffffffc |
||||
|
||||
/* MII Status Register */ |
||||
#define MII_STATUS_REG 1 |
||||
|
||||
/* Number of statistics registers */ |
||||
#define EMAC_NUM_STATS 36 |
||||
|
||||
|
||||
/* EMAC Descriptor */ |
||||
typedef volatile struct _emac_desc |
||||
{ |
||||
u_int32_t next; /* Pointer to next descriptor in chain */ |
||||
u_int8_t *buffer; /* Pointer to data buffer */ |
||||
u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ |
||||
u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ |
||||
} emac_desc; |
||||
|
||||
/* CPPI bit positions */ |
||||
#define EMAC_CPPI_SOP_BIT (0x80000000) |
||||
#define EMAC_CPPI_EOP_BIT (0x40000000) |
||||
#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) |
||||
#define EMAC_CPPI_EOQ_BIT (0x10000000) |
||||
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) |
||||
#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) |
||||
|
||||
#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) |
||||
|
||||
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) |
||||
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) |
||||
|
||||
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) |
||||
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) |
||||
|
||||
|
||||
#define MDIO_CONTROL_IDLE (0x80000000) |
||||
#define MDIO_CONTROL_ENABLE (0x40000000) |
||||
#define MDIO_CONTROL_FAULT_ENABLE (0x40000) |
||||
#define MDIO_CONTROL_FAULT (0x80000) |
||||
#define MDIO_USERACCESS0_GO (0x80000000) |
||||
#define MDIO_USERACCESS0_WRITE_READ (0x0) |
||||
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) |
||||
#define MDIO_USERACCESS0_ACK (0x20000000) |
||||
|
||||
/* Ethernet MAC Registers Structure */ |
||||
typedef struct { |
||||
dv_reg TXIDVER; |
||||
dv_reg TXCONTROL; |
||||
dv_reg TXTEARDOWN; |
||||
u_int8_t RSVD0[4]; |
||||
dv_reg RXIDVER; |
||||
dv_reg RXCONTROL; |
||||
dv_reg RXTEARDOWN; |
||||
u_int8_t RSVD1[100]; |
||||
dv_reg TXINTSTATRAW; |
||||
dv_reg TXINTSTATMASKED; |
||||
dv_reg TXINTMASKSET; |
||||
dv_reg TXINTMASKCLEAR; |
||||
dv_reg MACINVECTOR; |
||||
u_int8_t RSVD2[12]; |
||||
dv_reg RXINTSTATRAW; |
||||
dv_reg RXINTSTATMASKED; |
||||
dv_reg RXINTMASKSET; |
||||
dv_reg RXINTMASKCLEAR; |
||||
dv_reg MACINTSTATRAW; |
||||
dv_reg MACINTSTATMASKED; |
||||
dv_reg MACINTMASKSET; |
||||
dv_reg MACINTMASKCLEAR; |
||||
u_int8_t RSVD3[64]; |
||||
dv_reg RXMBPENABLE; |
||||
dv_reg RXUNICASTSET; |
||||
dv_reg RXUNICASTCLEAR; |
||||
dv_reg RXMAXLEN; |
||||
dv_reg RXBUFFEROFFSET; |
||||
dv_reg RXFILTERLOWTHRESH; |
||||
u_int8_t RSVD4[8]; |
||||
dv_reg RX0FLOWTHRESH; |
||||
dv_reg RX1FLOWTHRESH; |
||||
dv_reg RX2FLOWTHRESH; |
||||
dv_reg RX3FLOWTHRESH; |
||||
dv_reg RX4FLOWTHRESH; |
||||
dv_reg RX5FLOWTHRESH; |
||||
dv_reg RX6FLOWTHRESH; |
||||
dv_reg RX7FLOWTHRESH; |
||||
dv_reg RX0FREEBUFFER; |
||||
dv_reg RX1FREEBUFFER; |
||||
dv_reg RX2FREEBUFFER; |
||||
dv_reg RX3FREEBUFFER; |
||||
dv_reg RX4FREEBUFFER; |
||||
dv_reg RX5FREEBUFFER; |
||||
dv_reg RX6FREEBUFFER; |
||||
dv_reg RX7FREEBUFFER; |
||||
dv_reg MACCONTROL; |
||||
dv_reg MACSTATUS; |
||||
dv_reg EMCONTROL; |
||||
dv_reg FIFOCONTROL; |
||||
dv_reg MACCONFIG; |
||||
dv_reg SOFTRESET; |
||||
u_int8_t RSVD5[88]; |
||||
dv_reg MACSRCADDRLO; |
||||
dv_reg MACSRCADDRHI; |
||||
dv_reg MACHASH1; |
||||
dv_reg MACHASH2; |
||||
dv_reg BOFFTEST; |
||||
dv_reg TPACETEST; |
||||
dv_reg RXPAUSE; |
||||
dv_reg TXPAUSE; |
||||
u_int8_t RSVD6[16]; |
||||
dv_reg RXGOODFRAMES; |
||||
dv_reg RXBCASTFRAMES; |
||||
dv_reg RXMCASTFRAMES; |
||||
dv_reg RXPAUSEFRAMES; |
||||
dv_reg RXCRCERRORS; |
||||
dv_reg RXALIGNCODEERRORS; |
||||
dv_reg RXOVERSIZED; |
||||
dv_reg RXJABBER; |
||||
dv_reg RXUNDERSIZED; |
||||
dv_reg RXFRAGMENTS; |
||||
dv_reg RXFILTERED; |
||||
dv_reg RXQOSFILTERED; |
||||
dv_reg RXOCTETS; |
||||
dv_reg TXGOODFRAMES; |
||||
dv_reg TXBCASTFRAMES; |
||||
dv_reg TXMCASTFRAMES; |
||||
dv_reg TXPAUSEFRAMES; |
||||
dv_reg TXDEFERRED; |
||||
dv_reg TXCOLLISION; |
||||
dv_reg TXSINGLECOLL; |
||||
dv_reg TXMULTICOLL; |
||||
dv_reg TXEXCESSIVECOLL; |
||||
dv_reg TXLATECOLL; |
||||
dv_reg TXUNDERRUN; |
||||
dv_reg TXCARRIERSENSE; |
||||
dv_reg TXOCTETS; |
||||
dv_reg FRAME64; |
||||
dv_reg FRAME65T127; |
||||
dv_reg FRAME128T255; |
||||
dv_reg FRAME256T511; |
||||
dv_reg FRAME512T1023; |
||||
dv_reg FRAME1024TUP; |
||||
dv_reg NETOCTETS; |
||||
dv_reg RXSOFOVERRUNS; |
||||
dv_reg RXMOFOVERRUNS; |
||||
dv_reg RXDMAOVERRUNS; |
||||
u_int8_t RSVD7[624]; |
||||
dv_reg MACADDRLO; |
||||
dv_reg MACADDRHI; |
||||
dv_reg MACINDEX; |
||||
u_int8_t RSVD8[244]; |
||||
dv_reg TX0HDP; |
||||
dv_reg TX1HDP; |
||||
dv_reg TX2HDP; |
||||
dv_reg TX3HDP; |
||||
dv_reg TX4HDP; |
||||
dv_reg TX5HDP; |
||||
dv_reg TX6HDP; |
||||
dv_reg TX7HDP; |
||||
dv_reg RX0HDP; |
||||
dv_reg RX1HDP; |
||||
dv_reg RX2HDP; |
||||
dv_reg RX3HDP; |
||||
dv_reg RX4HDP; |
||||
dv_reg RX5HDP; |
||||
dv_reg RX6HDP; |
||||
dv_reg RX7HDP; |
||||
dv_reg TX0CP; |
||||
dv_reg TX1CP; |
||||
dv_reg TX2CP; |
||||
dv_reg TX3CP; |
||||
dv_reg TX4CP; |
||||
dv_reg TX5CP; |
||||
dv_reg TX6CP; |
||||
dv_reg TX7CP; |
||||
dv_reg RX0CP; |
||||
dv_reg RX1CP; |
||||
dv_reg RX2CP; |
||||
dv_reg RX3CP; |
||||
dv_reg RX4CP; |
||||
dv_reg RX5CP; |
||||
dv_reg RX6CP; |
||||
dv_reg RX7CP; |
||||
} emac_regs; |
||||
|
||||
/* EMAC Wrapper Registers Structure */ |
||||
typedef struct { |
||||
u_int8_t RSVD0[4100]; |
||||
dv_reg EWCTL; |
||||
dv_reg EWINTTCNT; |
||||
} ewrap_regs; |
||||
|
||||
|
||||
/* EMAC MDIO Registers Structure */ |
||||
typedef struct { |
||||
dv_reg VERSION; |
||||
dv_reg CONTROL; |
||||
dv_reg ALIVE; |
||||
dv_reg LINK; |
||||
dv_reg LINKINTRAW; |
||||
dv_reg LINKINTMASKED; |
||||
u_int8_t RSVD0[8]; |
||||
dv_reg USERINTRAW; |
||||
dv_reg USERINTMASKED; |
||||
dv_reg USERINTMASKSET; |
||||
dv_reg USERINTMASKCLEAR; |
||||
u_int8_t RSVD1[80]; |
||||
dv_reg USERACCESS0; |
||||
dv_reg USERPHYSEL0; |
||||
dv_reg USERACCESS1; |
||||
dv_reg USERPHYSEL1; |
||||
} mdio_regs; |
||||
|
||||
int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); |
||||
int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); |
||||
|
||||
typedef struct |
||||
{ |
||||
char name[64]; |
||||
int (*init)(int phy_addr); |
||||
int (*is_phy_connected)(int phy_addr); |
||||
int (*get_link_speed)(int phy_addr); |
||||
int (*auto_negotiate)(int phy_addr); |
||||
} phy_t; |
||||
|
||||
#define PHY_LXT972 (0x001378e2) |
||||
int lxt972_is_phy_connected(int phy_addr); |
||||
int lxt972_get_link_speed(int phy_addr); |
||||
int lxt972_init_phy(int phy_addr); |
||||
int lxt972_auto_negotiate(int phy_addr); |
||||
|
||||
#define PHY_DP83848 (0x20005c90) |
||||
int dp83848_is_phy_connected(int phy_addr); |
||||
int dp83848_get_link_speed(int phy_addr); |
||||
int dp83848_init_phy(int phy_addr); |
||||
int dp83848_auto_negotiate(int phy_addr); |
||||
|
||||
#endif /* _DM644X_EMAC_H_ */ |
@ -0,0 +1,61 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _EMIF_DEFS_H_ |
||||
#define _EMIF_DEFS_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
typedef struct { |
||||
dv_reg ERCSR; |
||||
dv_reg AWCCR; |
||||
dv_reg SDBCR; |
||||
dv_reg SDRCR; |
||||
dv_reg AB1CR; |
||||
dv_reg AB2CR; |
||||
dv_reg AB3CR; |
||||
dv_reg AB4CR; |
||||
dv_reg SDTIMR; |
||||
dv_reg DDRSR; |
||||
dv_reg DDRPHYCR; |
||||
dv_reg DDRPHYSR; |
||||
dv_reg TOTAR; |
||||
dv_reg TOTACTR; |
||||
dv_reg DDRPHYID_REV; |
||||
dv_reg SDSRETR; |
||||
dv_reg EIRR; |
||||
dv_reg EIMR; |
||||
dv_reg EIMSR; |
||||
dv_reg EIMCR; |
||||
dv_reg IOCTRLR; |
||||
dv_reg IOSTATR; |
||||
u_int8_t RSVD0[8]; |
||||
dv_reg NANDFCR; |
||||
dv_reg NANDFSR; |
||||
u_int8_t RSVD1[8]; |
||||
dv_reg NANDF1ECC; |
||||
dv_reg NANDF2ECC; |
||||
dv_reg NANDF3ECC; |
||||
dv_reg NANDF4ECC; |
||||
} emif_registers; |
||||
|
||||
typedef emif_registers *emifregs; |
||||
#endif |
@ -0,0 +1,166 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Based on: |
||||
* |
||||
* ------------------------------------------------------------------------- |
||||
* |
||||
* linux/include/asm-arm/arch-davinci/hardware.h |
||||
* |
||||
* Copyright (C) 2006 Texas Instruments. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
* You should have received a copy of the GNU General Public License along |
||||
* with this program; if not, write to the Free Software Foundation, Inc., |
||||
* 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
*/ |
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H |
||||
|
||||
#include <config.h> |
||||
#include <asm/sizes.h> |
||||
|
||||
#define REG(addr) (*(volatile unsigned int *)(addr)) |
||||
#define REG_P(addr) ((volatile unsigned int *)(addr)) |
||||
|
||||
typedef volatile unsigned int dv_reg; |
||||
typedef volatile unsigned int * dv_reg_p; |
||||
|
||||
/*
|
||||
* Base register addresses |
||||
*/ |
||||
#define DAVINCI_DMA_3PCC_BASE (0x01c00000) |
||||
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) |
||||
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) |
||||
#define DAVINCI_UART0_BASE (0x01c20000) |
||||
#define DAVINCI_UART1_BASE (0x01c20400) |
||||
#define DAVINCI_UART2_BASE (0x01c20800) |
||||
#define DAVINCI_I2C_BASE (0x01c21000) |
||||
#define DAVINCI_TIMER0_BASE (0x01c21400) |
||||
#define DAVINCI_TIMER1_BASE (0x01c21800) |
||||
#define DAVINCI_WDOG_BASE (0x01c21c00) |
||||
#define DAVINCI_PWM0_BASE (0x01c22000) |
||||
#define DAVINCI_PWM1_BASE (0x01c22400) |
||||
#define DAVINCI_PWM2_BASE (0x01c22800) |
||||
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) |
||||
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) |
||||
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) |
||||
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) |
||||
#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000) |
||||
#define DAVINCI_ARM_INTC_BASE (0x01c48000) |
||||
#define DAVINCI_IEEE1394_BASE (0x01c60000) |
||||
#define DAVINCI_USB_OTG_BASE (0x01c64000) |
||||
#define DAVINCI_CFC_ATA_BASE (0x01c66000) |
||||
#define DAVINCI_SPI_BASE (0x01c66800) |
||||
#define DAVINCI_GPIO_BASE (0x01c67000) |
||||
#define DAVINCI_UHPI_BASE (0x01c67800) |
||||
#define DAVINCI_VPSS_REGS_BASE (0x01c70000) |
||||
#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000) |
||||
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000) |
||||
#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000) |
||||
#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000) |
||||
#define DAVINCI_IMCOP_BASE (0x01cc0000) |
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000) |
||||
#define DAVINCI_VLYNQ_BASE (0x01e01000) |
||||
#define DAVINCI_MCBSP_BASE (0x01e02000) |
||||
#define DAVINCI_MMC_SD_BASE (0x01e10000) |
||||
#define DAVINCI_MS_BASE (0x01e20000) |
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) |
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) |
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) |
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) |
||||
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000) |
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */ |
||||
#define DAVINCI_GPSC_ARMDOMAIN 0 |
||||
#define DAVINCI_GPSC_DSPDOMAIN 1 |
||||
|
||||
#define DAVINCI_LPSC_VPSSMSTR 0 |
||||
#define DAVINCI_LPSC_VPSSSLV 1 |
||||
#define DAVINCI_LPSC_TPCC 2 |
||||
#define DAVINCI_LPSC_TPTC0 3 |
||||
#define DAVINCI_LPSC_TPTC1 4 |
||||
#define DAVINCI_LPSC_EMAC 5 |
||||
#define DAVINCI_LPSC_EMAC_WRAPPER 6 |
||||
#define DAVINCI_LPSC_MDIO 7 |
||||
#define DAVINCI_LPSC_IEEE1394 8 |
||||
#define DAVINCI_LPSC_USB 9 |
||||
#define DAVINCI_LPSC_ATA 10 |
||||
#define DAVINCI_LPSC_VLYNQ 11 |
||||
#define DAVINCI_LPSC_UHPI 12 |
||||
#define DAVINCI_LPSC_DDR_EMIF 13 |
||||
#define DAVINCI_LPSC_AEMIF 14 |
||||
#define DAVINCI_LPSC_MMC_SD 15 |
||||
#define DAVINCI_LPSC_MEMSTICK 16 |
||||
#define DAVINCI_LPSC_McBSP 17 |
||||
#define DAVINCI_LPSC_I2C 18 |
||||
#define DAVINCI_LPSC_UART0 19 |
||||
#define DAVINCI_LPSC_UART1 20 |
||||
#define DAVINCI_LPSC_UART2 21 |
||||
#define DAVINCI_LPSC_SPI 22 |
||||
#define DAVINCI_LPSC_PWM0 23 |
||||
#define DAVINCI_LPSC_PWM1 24 |
||||
#define DAVINCI_LPSC_PWM2 25 |
||||
#define DAVINCI_LPSC_GPIO 26 |
||||
#define DAVINCI_LPSC_TIMER0 27 |
||||
#define DAVINCI_LPSC_TIMER1 28 |
||||
#define DAVINCI_LPSC_TIMER2 29 |
||||
#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 |
||||
#define DAVINCI_LPSC_ARM 31 |
||||
#define DAVINCI_LPSC_SCR2 32 |
||||
#define DAVINCI_LPSC_SCR3 33 |
||||
#define DAVINCI_LPSC_SCR4 34 |
||||
#define DAVINCI_LPSC_CROSSBAR 35 |
||||
#define DAVINCI_LPSC_CFG27 36 |
||||
#define DAVINCI_LPSC_CFG3 37 |
||||
#define DAVINCI_LPSC_CFG5 38 |
||||
#define DAVINCI_LPSC_GEM 39 |
||||
#define DAVINCI_LPSC_IMCOP 40 |
||||
|
||||
/* Some PSC defines */ |
||||
#define PSC_CHP_SHRTSW (0x01c40038) |
||||
#define PSC_GBLCTL (0x01c41010) |
||||
#define PSC_EPCPR (0x01c41070) |
||||
#define PSC_EPCCR (0x01c41078) |
||||
#define PSC_PTCMD (0x01c41120) |
||||
#define PSC_PTSTAT (0x01c41128) |
||||
#define PSC_PDSTAT (0x01c41200) |
||||
#define PSC_PDSTAT1 (0x01c41204) |
||||
#define PSC_PDCTL (0x01c41300) |
||||
#define PSC_PDCTL1 (0x01c41304) |
||||
|
||||
#define PSC_MDCTL_BASE (0x01c41a00) |
||||
#define PSC_MDSTAT_BASE (0x01c41800) |
||||
|
||||
#define VDD3P3V_PWDN (0x01c40048) |
||||
#define UART0_PWREMU_MGMT (0x01c20030) |
||||
|
||||
#define PSC_SILVER_BULLET (0x01c41a20) |
||||
|
||||
/* Some PLL defines */ |
||||
#define PLL1_PLLM (0x01c40910) |
||||
#define PLL2_PLLM (0x01c40d10) |
||||
#define PLL2_DIV2 (0x01c40d1c) |
||||
|
||||
/* Miscellania... */ |
||||
#define VBPR (0x20000020) |
||||
#define PINMUX0 (0x01c40000) |
||||
#define PINMUX1 (0x01c40004) |
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */ |
@ -0,0 +1,94 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _DAVINCI_I2C_H_ |
||||
#define _DAVINCI_I2C_H_ |
||||
|
||||
#define I2C_WRITE 0 |
||||
#define I2C_READ 1 |
||||
|
||||
#define I2C_BASE 0x01c21000 |
||||
|
||||
#define I2C_OA (I2C_BASE + 0x00) |
||||
#define I2C_IE (I2C_BASE + 0x04) |
||||
#define I2C_STAT (I2C_BASE + 0x08) |
||||
#define I2C_SCLL (I2C_BASE + 0x0c) |
||||
#define I2C_SCLH (I2C_BASE + 0x10) |
||||
#define I2C_CNT (I2C_BASE + 0x14) |
||||
#define I2C_DRR (I2C_BASE + 0x18) |
||||
#define I2C_SA (I2C_BASE + 0x1c) |
||||
#define I2C_DXR (I2C_BASE + 0x20) |
||||
#define I2C_CON (I2C_BASE + 0x24) |
||||
#define I2C_IV (I2C_BASE + 0x28) |
||||
#define I2C_PSC (I2C_BASE + 0x30) |
||||
|
||||
/* I2C masks */ |
||||
|
||||
/* I2C Interrupt Enable Register (I2C_IE): */ |
||||
#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ |
||||
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
||||
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
||||
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
||||
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
||||
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
||||
|
||||
/* I2C Status Register (I2C_STAT): */ |
||||
|
||||
#define I2C_STAT_BB (1 << 12) /* Bus busy */ |
||||
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
||||
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
||||
#define I2C_STAT_AAS (1 << 9) /* Address as slave */ |
||||
#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ |
||||
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
||||
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
||||
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
||||
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
||||
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
||||
|
||||
|
||||
/* I2C Interrupt Code Register (I2C_INTCODE): */ |
||||
|
||||
#define I2C_INTCODE_MASK 7 |
||||
#define I2C_INTCODE_NONE 0 |
||||
#define I2C_INTCODE_AL 1 /* Arbitration lost */ |
||||
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ |
||||
#define I2C_INTCODE_ARDY 3 /* Register access ready */ |
||||
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ |
||||
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ |
||||
#define I2C_INTCODE_SCD 6 /* Stop condition detect */ |
||||
|
||||
|
||||
/* I2C Configuration Register (I2C_CON): */ |
||||
|
||||
#define I2C_CON_EN (1 << 5) /* I2C module enable */ |
||||
#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ |
||||
#define I2C_CON_MST (1 << 10) /* Master/slave mode */ |
||||
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ |
||||
#define I2C_CON_XA (1 << 8) /* Expand address */ |
||||
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ |
||||
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ |
||||
|
||||
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ |
||||
|
||||
#endif |
@ -0,0 +1,161 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* Parts shamelesly stolen from Linux Kernel source tree. |
||||
* |
||||
* ------------------------------------------------------------ |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _NAND_DEFS_H_ |
||||
#define _NAND_DEFS_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
#define MASK_CLE 0x10 |
||||
#define MASK_ALE 0x0a |
||||
|
||||
#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10)) |
||||
#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a)) |
||||
#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE) |
||||
|
||||
typedef struct { |
||||
u_int32_t NRCSR; |
||||
u_int32_t AWCCR; |
||||
u_int8_t RSVD0[8]; |
||||
u_int32_t AB1CR; |
||||
u_int32_t AB2CR; |
||||
u_int32_t AB3CR; |
||||
u_int32_t AB4CR; |
||||
u_int8_t RSVD1[32]; |
||||
u_int32_t NIRR; |
||||
u_int32_t NIMR; |
||||
u_int32_t NIMSR; |
||||
u_int32_t NIMCR; |
||||
u_int8_t RSVD2[16]; |
||||
u_int32_t NANDFCR; |
||||
u_int32_t NANDFSR; |
||||
u_int8_t RSVD3[8]; |
||||
u_int32_t NANDF1ECC; |
||||
u_int32_t NANDF2ECC; |
||||
u_int32_t NANDF3ECC; |
||||
u_int32_t NANDF4ECC; |
||||
u_int8_t RSVD4[4]; |
||||
u_int32_t IODFTECR; |
||||
u_int32_t IODFTGCR; |
||||
u_int8_t RSVD5[4]; |
||||
u_int32_t IODFTMRLR; |
||||
u_int32_t IODFTMRMR; |
||||
u_int32_t IODFTMRMSBR; |
||||
u_int8_t RSVD6[20]; |
||||
u_int32_t MODRNR; |
||||
u_int8_t RSVD7[76]; |
||||
u_int32_t CE0DATA; |
||||
u_int32_t CE0ALE; |
||||
u_int32_t CE0CLE; |
||||
u_int8_t RSVD8[4]; |
||||
u_int32_t CE1DATA; |
||||
u_int32_t CE1ALE; |
||||
u_int32_t CE1CLE; |
||||
u_int8_t RSVD9[4]; |
||||
u_int32_t CE2DATA; |
||||
u_int32_t CE2ALE; |
||||
u_int32_t CE2CLE; |
||||
u_int8_t RSVD10[4]; |
||||
u_int32_t CE3DATA; |
||||
u_int32_t CE3ALE; |
||||
u_int32_t CE3CLE; |
||||
} nand_registers; |
||||
|
||||
typedef volatile nand_registers *nandregs; |
||||
|
||||
#define NAND_READ_START 0x00 |
||||
#define NAND_READ_END 0x30 |
||||
#define NAND_STATUS 0x70 |
||||
|
||||
#ifdef CFG_NAND_HW_ECC |
||||
#define NAND_Ecc_P1e (1 << 0) |
||||
#define NAND_Ecc_P2e (1 << 1) |
||||
#define NAND_Ecc_P4e (1 << 2) |
||||
#define NAND_Ecc_P8e (1 << 3) |
||||
#define NAND_Ecc_P16e (1 << 4) |
||||
#define NAND_Ecc_P32e (1 << 5) |
||||
#define NAND_Ecc_P64e (1 << 6) |
||||
#define NAND_Ecc_P128e (1 << 7) |
||||
#define NAND_Ecc_P256e (1 << 8) |
||||
#define NAND_Ecc_P512e (1 << 9) |
||||
#define NAND_Ecc_P1024e (1 << 10) |
||||
#define NAND_Ecc_P2048e (1 << 11) |
||||
|
||||
#define NAND_Ecc_P1o (1 << 16) |
||||
#define NAND_Ecc_P2o (1 << 17) |
||||
#define NAND_Ecc_P4o (1 << 18) |
||||
#define NAND_Ecc_P8o (1 << 19) |
||||
#define NAND_Ecc_P16o (1 << 20) |
||||
#define NAND_Ecc_P32o (1 << 21) |
||||
#define NAND_Ecc_P64o (1 << 22) |
||||
#define NAND_Ecc_P128o (1 << 23) |
||||
#define NAND_Ecc_P256o (1 << 24) |
||||
#define NAND_Ecc_P512o (1 << 25) |
||||
#define NAND_Ecc_P1024o (1 << 26) |
||||
#define NAND_Ecc_P2048o (1 << 27) |
||||
|
||||
#define TF(v) (v ? 1 : 0) |
||||
|
||||
#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) |
||||
#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) |
||||
#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) |
||||
#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) |
||||
#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) |
||||
#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) |
||||
#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) |
||||
#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) |
||||
|
||||
#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) |
||||
#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) |
||||
#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) |
||||
#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) |
||||
#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) |
||||
#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) |
||||
#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) |
||||
#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) |
||||
|
||||
#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) |
||||
#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) |
||||
#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) |
||||
#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) |
||||
#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) |
||||
#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) |
||||
#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) |
||||
#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) |
||||
|
||||
#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) |
||||
#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) |
||||
#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) |
||||
#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) |
||||
#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) |
||||
#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) |
||||
#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) |
||||
#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) |
||||
|
||||
#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) |
||||
#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) |
||||
#endif |
||||
|
||||
#endif |
@ -0,0 +1,214 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*
|
||||
* Define this to make U-Boot skip low level initialization when loaded |
||||
* by initial bootloader. Not required by NAND U-Boot version but IS |
||||
* required for a NOR version used to burn the real NOR U-Boot into |
||||
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive |
||||
* so it is NOT possible to build a U-Boot with both NAND and NOR routines. |
||||
* NOR U-Boot is loaded directly from Flash so it must perform all the |
||||
* low level initialization itself. NAND version is loaded by an initial |
||||
* bootloader (UBL in TI-ese) that performs such an initialization so it's |
||||
* skipped in NAND version. The third DaVinci boot mode loads a bootloader |
||||
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) |
||||
* performing low level init prior to loading. All that means we can NOT use |
||||
* NAND version to put U-Boot into NOR because it doesn't have NOR support and |
||||
* we can NOT use NOR version because it performs low level initialization |
||||
* effectively destroying itself in DDR memory. That's why a separate NOR |
||||
* version with this define is needed. It is loaded via UART, then one uses |
||||
* it to somehow download a proper NOR version built WITHOUT this define to |
||||
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze |
||||
* NOR support into the initial bootloader so it won't be needed but DaVinci |
||||
* static RAM might be too small for this (I have something like 2Kbytes left |
||||
* as of now, without NOR support) so this might've not happened... |
||||
* |
||||
#define CONFIG_NOR_UART_BOOT |
||||
*/ |
||||
|
||||
/*=======*/ |
||||
/* Board */ |
||||
/*=======*/ |
||||
#define DV_EVM |
||||
#define CFG_NAND_SMALLPAGE |
||||
#define CFG_USE_NOR |
||||
/*===================*/ |
||||
/* SoC Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
||||
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ |
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ |
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ |
||||
#define CFG_HZ 1000 |
||||
/*====================================================*/ |
||||
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ |
||||
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ |
||||
/*====================================================*/ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
/*=============*/ |
||||
/* Memory Info */ |
||||
/*=============*/ |
||||
#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ |
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ |
||||
#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
||||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ |
||||
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ |
||||
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ |
||||
/*====================*/ |
||||
/* Serial Driver info */ |
||||
/*====================*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ |
||||
#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ |
||||
#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
/*===================*/ |
||||
/* I2C Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CONFIG_DRIVER_DAVINCI_I2C |
||||
#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ |
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ |
||||
/*==================================*/ |
||||
/* Network & Ethernet Configuration */ |
||||
/*==================================*/ |
||||
#define CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_MII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
/*=====================*/ |
||||
/* Flash & Environment */ |
||||
/*=====================*/ |
||||
#ifdef CFG_USE_NAND |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_NO_FLASH |
||||
#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#ifdef CFG_NAND_SMALLPAGE |
||||
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ |
||||
#define CFG_ENV_SIZE SZ_16K |
||||
#else |
||||
#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ |
||||
#define CFG_ENV_SIZE SZ_128K |
||||
#endif |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
#define CFG_NAND_BASE 0x02000000 |
||||
#define CFG_NAND_HW_ECC |
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
#define DEF_BOOTM "" |
||||
#elif defined(CFG_USE_NOR) |
||||
#ifdef CONFIG_NOR_UART_BOOT |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
#else |
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||
#endif |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_NO_FLASH |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ |
||||
#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ |
||||
#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) |
||||
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ |
||||
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ |
||||
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) |
||||
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ |
||||
#endif |
||||
/*==============================*/ |
||||
/* U-Boot general configuration */ |
||||
/*==============================*/ |
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#undef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CFG_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
/*===================*/ |
||||
/* Linux Information */ |
||||
/*===================*/ |
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100 |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" |
||||
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" |
||||
/*=================*/ |
||||
/* U-Boot commands */ |
||||
/*=================*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_EEPROM |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#ifdef CFG_USE_NAND |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_NAND |
||||
#elif defined(CFG_USE_NOR) |
||||
#define CONFIG_CMD_JFFS2 |
||||
#else |
||||
#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" |
||||
#endif |
||||
/*=======================*/ |
||||
/* KGDB support (if any) */ |
||||
/*=======================*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,157 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*=======*/ |
||||
/* Board */ |
||||
/*=======*/ |
||||
#define SCHMOOGIE |
||||
#define CFG_NAND_LARGEPAGE |
||||
#define CFG_USE_NAND |
||||
/*===================*/ |
||||
/* SoC Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
||||
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ |
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ |
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ |
||||
#define CFG_HZ 1000 |
||||
/*=============*/ |
||||
/* Memory Info */ |
||||
/*=============*/ |
||||
#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ |
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ |
||||
#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
||||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ |
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ |
||||
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ |
||||
/*====================*/ |
||||
/* Serial Driver info */ |
||||
/*====================*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ |
||||
#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ |
||||
#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
/*===================*/ |
||||
/* I2C Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CONFIG_DRIVER_DAVINCI_I2C |
||||
#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ |
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ |
||||
/*==================================*/ |
||||
/* Network & Ethernet Configuration */ |
||||
/*==================================*/ |
||||
#define CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_MII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
/*=====================*/ |
||||
/* Flash & Environment */ |
||||
/*=====================*/ |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_NO_FLASH |
||||
#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ |
||||
#define CFG_ENV_SIZE SZ_128K |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
#define CFG_NAND_BASE 0x02000000 |
||||
#define CFG_NAND_HW_ECC |
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
/*=====================*/ |
||||
/* Board related stuff */ |
||||
/*=====================*/ |
||||
#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ |
||||
#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ |
||||
#define CONFIG_HAS_UID |
||||
#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ |
||||
#define CFG_UID_ADDR 0x50 /* UID chip I2C address */ |
||||
/*==============================*/ |
||||
/* U-Boot general configuration */ |
||||
/*==============================*/ |
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#undef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CFG_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
/*===================*/ |
||||
/* Linux Information */ |
||||
/*===================*/ |
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100 |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" |
||||
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" |
||||
/*=================*/ |
||||
/* U-Boot commands */ |
||||
/*=================*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_NAND |
||||
#undef CONFIG_CMD_EEPROM |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
/*=======================*/ |
||||
/* KGDB support (if any) */ |
||||
/*=======================*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*
|
||||
* Define this to make U-Boot skip low level initialization when loaded |
||||
* by initial bootloader. Not required by NAND U-Boot version but IS |
||||
* required for a NOR version used to burn the real NOR U-Boot into |
||||
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive |
||||
* so it is NOT possible to build a U-Boot with both NAND and NOR routines. |
||||
* NOR U-Boot is loaded directly from Flash so it must perform all the |
||||
* low level initialization itself. NAND version is loaded by an initial |
||||
* bootloader (UBL in TI-ese) that performs such an initialization so it's |
||||
* skipped in NAND version. The third DaVinci boot mode loads a bootloader |
||||
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) |
||||
* performing low level init prior to loading. All that means we can NOT use |
||||
* NAND version to put U-Boot into NOR because it doesn't have NOR support and |
||||
* we can NOT use NOR version because it performs low level initialization |
||||
* effectively destroying itself in DDR memory. That's why a separate NOR |
||||
* version with this define is needed. It is loaded via UART, then one uses |
||||
* it to somehow download a proper NOR version built WITHOUT this define to |
||||
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze |
||||
* NOR support into the initial bootloader so it won't be needed but DaVinci |
||||
* static RAM might be too small for this (I have something like 2Kbytes left |
||||
* as of now, without NOR support) so this might've not happened... |
||||
* |
||||
#define CONFIG_NOR_UART_BOOT |
||||
*/ |
||||
|
||||
/*=======*/ |
||||
/* Board */ |
||||
/*=======*/ |
||||
#define SONATA_BOARD |
||||
#define CFG_NAND_SMALLPAGE |
||||
#define CFG_USE_NOR |
||||
/*===================*/ |
||||
/* SoC Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
||||
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ |
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ |
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ |
||||
#define CFG_HZ 1000 |
||||
/*====================================================*/ |
||||
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ |
||||
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ |
||||
/*====================================================*/ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
/*=============*/ |
||||
/* Memory Info */ |
||||
/*=============*/ |
||||
#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ |
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ |
||||
#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
||||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ |
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ |
||||
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ |
||||
/*====================*/ |
||||
/* Serial Driver info */ |
||||
/*====================*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ |
||||
#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ |
||||
#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
/*===================*/ |
||||
/* I2C Configuration */ |
||||
/*===================*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CONFIG_DRIVER_DAVINCI_I2C |
||||
#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ |
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ |
||||
/*==================================*/ |
||||
/* Network & Ethernet Configuration */ |
||||
/*==================================*/ |
||||
#define CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_MII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
/*=====================*/ |
||||
/* Flash & Environment */ |
||||
/*=====================*/ |
||||
#ifdef CFG_USE_NAND |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_NO_FLASH |
||||
#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ |
||||
#define CFG_ENV_SIZE SZ_16K |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
#define CFG_NAND_BASE 0x02000000 |
||||
#define CFG_NAND_HW_ECC |
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
#define DEF_BOOTM "" |
||||
#elif defined(CFG_USE_NOR) |
||||
#ifdef CONFIG_NOR_UART_BOOT |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
#else |
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT |
||||
#endif |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_NO_FLASH |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ |
||||
#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ |
||||
#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) |
||||
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ |
||||
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ |
||||
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) |
||||
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ |
||||
#endif |
||||
/*==============================*/ |
||||
/* U-Boot general configuration */ |
||||
/*==============================*/ |
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#undef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CFG_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
/*===================*/ |
||||
/* Linux Information */ |
||||
/*===================*/ |
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100 |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" |
||||
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" |
||||
/*=================*/ |
||||
/* U-Boot commands */ |
||||
/*=================*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_EEPROM |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#ifdef CFG_USE_NAND |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_NAND |
||||
#elif defined(CFG_USE_NOR) |
||||
#define CONFIG_CMD_JFFS2 |
||||
#else |
||||
#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" |
||||
#endif |
||||
/*=======================*/ |
||||
/* KGDB support (if any) */ |
||||
/*=======================*/ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,88 @@ |
||||
/*
|
||||
* DP83848 ethernet Physical layer |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* as published by the Free Software Foundation; either version |
||||
* 2 of the License, or (at your option) any later version. |
||||
*/ |
||||
|
||||
|
||||
/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ |
||||
|
||||
#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ |
||||
#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ |
||||
#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ |
||||
#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ |
||||
#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ |
||||
#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ |
||||
#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ |
||||
#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ |
||||
#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ |
||||
#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ |
||||
|
||||
/*--Bit definitions: DP83848_CTL_REG */ |
||||
#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ |
||||
#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ |
||||
#define DP83848_SPEED_SELECT (1 << 13) |
||||
#define DP83848_AUTONEG (1 << 12) |
||||
#define DP83848_POWER_DOWN (1 << 11) |
||||
#define DP83848_ISOLATE (1 << 10) |
||||
#define DP83848_RESTART_AUTONEG (1 << 9) |
||||
#define DP83848_DUPLEX_MODE (1 << 8) |
||||
#define DP83848_COLLISION_TEST (1 << 7) |
||||
|
||||
/*--Bit definitions: DP83848_STAT_REG */ |
||||
#define DP83848_100BASE_T4 (1 << 15) |
||||
#define DP83848_100BASE_TX_FD (1 << 14) |
||||
#define DP83848_100BASE_TX_HD (1 << 13) |
||||
#define DP83848_10BASE_T_FD (1 << 12) |
||||
#define DP83848_10BASE_T_HD (1 << 11) |
||||
#define DP83848_MF_PREAMB_SUPPR (1 << 6) |
||||
#define DP83848_AUTONEG_COMP (1 << 5) |
||||
#define DP83848_RMT_FAULT (1 << 4) |
||||
#define DP83848_AUTONEG_ABILITY (1 << 3) |
||||
#define DP83848_LINK_STATUS (1 << 2) |
||||
#define DP83848_JABBER_DETECT (1 << 1) |
||||
#define DP83848_EXTEND_CAPAB (1 << 0) |
||||
|
||||
/*--definitions: DP83848_PHYID1 */ |
||||
#define DP83848_PHYID1_OUI 0x2000 |
||||
#define DP83848_PHYID2_OUI 0x5c90 |
||||
|
||||
/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ |
||||
#define DP83848_NP (1 << 15) |
||||
#define DP83848_ACK (1 << 14) |
||||
#define DP83848_RF (1 << 13) |
||||
#define DP83848_PAUSE (1 << 10) |
||||
#define DP83848_T4 (1 << 9) |
||||
#define DP83848_TX_FDX (1 << 8) |
||||
#define DP83848_TX_HDX (1 << 7) |
||||
#define DP83848_10_FDX (1 << 6) |
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#define DP83848_10_HDX (1 << 5) |
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#define DP83848_AN_IEEE_802_3 0x0001 |
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|
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/*--Bit definitions: DP83848_ANER */ |
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#define DP83848_PDF (1 << 4) |
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#define DP83848_LP_NP_ABLE (1 << 3) |
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#define DP83848_NP_ABLE (1 << 2) |
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#define DP83848_PAGE_RX (1 << 1) |
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#define DP83848_LP_AN_ABLE (1 << 0) |
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|
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/*--Bit definitions: DP83848_PHY_STAT */ |
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#define DP83848_RX_ERR_LATCH (1 << 13) |
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#define DP83848_POLARITY_STAT (1 << 12) |
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#define DP83848_FALSE_CAR_SENSE (1 << 11) |
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#define DP83848_SIG_DETECT (1 << 10) |
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#define DP83848_DESCRAM_LOCK (1 << 9) |
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#define DP83848_PAGE_RCV (1 << 8) |
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#define DP83848_PHY_RMT_FAULT (1 << 6) |
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#define DP83848_JABBER (1 << 5) |
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#define DP83848_AUTONEG_COMPLETE (1 << 4) |
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#define DP83848_LOOPBACK_STAT (1 << 3) |
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#define DP83848_DUPLEX (1 << 2) |
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#define DP83848_SPEED (1 << 1) |
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#define DP83848_LINK (1 << 0) |
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Reference in new issue