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@ -374,6 +374,7 @@ config ARCH_B4420 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config ARCH_B4860 |
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bool |
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@ -398,6 +399,7 @@ config ARCH_B4860 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config ARCH_BSC9131 |
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bool |
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@ -410,6 +412,7 @@ config ARCH_BSC9131 |
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select SYS_FSL_HAS_SEC |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select FSL_IFC |
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config ARCH_BSC9132 |
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bool |
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@ -426,6 +429,7 @@ config ARCH_BSC9132 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_IFC |
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config ARCH_C29X |
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bool |
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@ -438,6 +442,7 @@ config ARCH_C29X |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_6 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_IFC |
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config ARCH_MPC8536 |
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bool |
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@ -450,6 +455,7 @@ config ARCH_MPC8536 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_MPC8540 |
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bool |
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@ -473,6 +479,7 @@ config ARCH_MPC8544 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_MPC8548 |
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bool |
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@ -519,6 +526,7 @@ config ARCH_MPC8569 |
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select SYS_FSL_HAS_SEC |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select FSL_ELBC |
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config ARCH_MPC8572 |
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bool |
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@ -533,6 +541,7 @@ config ARCH_MPC8572 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1010 |
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bool |
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@ -553,6 +562,7 @@ config ARCH_P1010 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_IFC |
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config ARCH_P1011 |
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bool |
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@ -566,6 +576,7 @@ config ARCH_P1011 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1020 |
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bool |
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@ -579,6 +590,7 @@ config ARCH_P1020 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1021 |
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bool |
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@ -592,6 +604,7 @@ config ARCH_P1021 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1022 |
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bool |
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@ -607,6 +620,7 @@ config ARCH_P1022 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1023 |
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bool |
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@ -618,6 +632,7 @@ config ARCH_P1023 |
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select SYS_FSL_HAS_SEC |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select FSL_ELBC |
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config ARCH_P1024 |
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bool |
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@ -631,6 +646,7 @@ config ARCH_P1024 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P1025 |
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bool |
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@ -644,6 +660,7 @@ config ARCH_P1025 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P2020 |
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bool |
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@ -658,6 +675,7 @@ config ARCH_P2020 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_2 |
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select SYS_PPC_E500_USE_DEBUG_TLB |
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select FSL_ELBC |
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config ARCH_P2041 |
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bool |
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@ -679,6 +697,7 @@ config ARCH_P2041 |
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select SYS_FSL_QORIQ_CHASSIS1 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select FSL_ELBC |
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config ARCH_P3041 |
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bool |
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@ -702,6 +721,7 @@ config ARCH_P3041 |
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select SYS_FSL_QORIQ_CHASSIS1 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select FSL_ELBC |
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config ARCH_P4080 |
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bool |
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@ -736,6 +756,7 @@ config ARCH_P4080 |
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select SYS_FSL_QORIQ_CHASSIS1 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select FSL_ELBC |
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config ARCH_P5020 |
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bool |
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@ -756,6 +777,7 @@ config ARCH_P5020 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_ELBC |
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config ARCH_P5040 |
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bool |
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@ -776,6 +798,7 @@ config ARCH_P5040 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_ELBC |
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config ARCH_QEMU_E500 |
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bool |
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@ -795,6 +818,7 @@ config ARCH_T1023 |
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select SYS_FSL_QORIQ_CHASSIS2 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_5 |
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select FSL_IFC |
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config ARCH_T1024 |
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bool |
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@ -811,6 +835,7 @@ config ARCH_T1024 |
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select SYS_FSL_QORIQ_CHASSIS2 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_5 |
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select FSL_IFC |
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config ARCH_T1040 |
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bool |
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@ -828,6 +853,7 @@ config ARCH_T1040 |
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select SYS_FSL_QORIQ_CHASSIS2 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_5 |
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select FSL_IFC |
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config ARCH_T1042 |
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bool |
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@ -845,6 +871,7 @@ config ARCH_T1042 |
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select SYS_FSL_QORIQ_CHASSIS2 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_5 |
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select FSL_IFC |
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config ARCH_T2080 |
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bool |
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@ -866,6 +893,7 @@ config ARCH_T2080 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config ARCH_T2081 |
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bool |
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@ -885,6 +913,7 @@ config ARCH_T2081 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config ARCH_T4160 |
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bool |
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@ -905,6 +934,7 @@ config ARCH_T4160 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config ARCH_T4240 |
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bool |
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@ -928,6 +958,7 @@ config ARCH_T4240 |
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select SYS_FSL_SEC_BE |
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select SYS_FSL_SEC_COMPAT_4 |
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select SYS_PPC64 |
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select FSL_IFC |
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config BOOKE |
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bool |
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@ -1260,6 +1291,12 @@ config SYS_PPC64 |
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config SYS_PPC_E500_USE_DEBUG_TLB |
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bool |
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config FSL_IFC |
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bool |
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config FSL_ELBC |
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bool |
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config SYS_PPC_E500_DEBUG_TLB |
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int "Temporary TLB entry for external debugger" |
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depends on SYS_PPC_E500_USE_DEBUG_TLB |
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@ -1284,6 +1321,40 @@ config SYS_PPC_E500_DEBUG_TLB |
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symbol should be set to the TLB1 entry to be used for this |
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purpose. If unsure, do not change. |
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config SYS_FSL_IFC_CLK_DIV |
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int "Divider of platform clock" |
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depends on FSL_IFC |
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default 2 if ARCH_B4420 || \ |
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ARCH_B4860 || \ |
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ARCH_T1024 || \ |
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ARCH_T1023 || \ |
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ARCH_T1040 || \ |
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ARCH_T1042 || \ |
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ARCH_T4160 || \ |
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ARCH_T4240 |
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default 1 |
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help |
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Defines divider of platform clock(clock input to |
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IFC controller). |
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config SYS_FSL_LBC_CLK_DIV |
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int "Divider of platform clock" |
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depends on FSL_ELBC || ARCH_MPC8540 || \ |
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ARCH_MPC8548 || ARCH_MPC8541 || \ |
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ARCH_MPC8555 || ARCH_MPC8560 || \ |
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ARCH_MPC8568 |
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default 2 if ARCH_P2041 || \ |
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ARCH_P3041 || \ |
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ARCH_P4080 || \ |
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ARCH_P5020 || \ |
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ARCH_P5040 |
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default 1 |
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help |
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Defines divider of platform clock(clock input to |
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eLBC controller). |
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source "board/freescale/b4860qds/Kconfig" |
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source "board/freescale/bsc9131rdb/Kconfig" |
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source "board/freescale/bsc9132qds/Kconfig" |
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