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ColdFire: Add MCF5227x cpu and MCF52277EVB support-2

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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>
master
TsiChungLiew 17 years ago
parent 1552af70ec
commit c875810279
8 changed files with 1171 additions and 0 deletions
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  1. 48
      cpu/mcf5227x/Makefile
  2. 31
      cpu/mcf5227x/config.mk
  3. 75
      cpu/mcf5227x/cpu.c
  4. 146
      cpu/mcf5227x/cpu_init.c
  5. 52
      cpu/mcf5227x/interrupts.c
  6. 120
      cpu/mcf5227x/speed.c
  7. 356
      cpu/mcf5227x/start.S
  8. 343
      include/asm-m68k/immap_5227x.h

48
cpu/mcf5227x/Makefile
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#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
# CFLAGS += -DET_DEBUG
LIB = lib$(CPU).a
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

31
cpu/mcf5227x/config.mk
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#
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2)
PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif

75
cpu/mcf5227x/cpu.c
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/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
rcm->rcr |= RCM_RCR_SOFTRST;
/* we don't return! */
return 0;
};
int checkcpu(void)
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
case 0x6c:
id = 52277;
break;
}
if (id) {
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
ver);
printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
(int)(gd->cpu_clk / 1000000),
(int)(gd->bus_clk / 1000000),
(int)(gd->flb_clk / 1000000));
printf(" INP CLK %d Mhz VCO CLK %d Mhz\n",
(int)(gd->inp_clk / 1000000),
(int)(gd->vco_clk / 1000000));
}
return 0;
}

146
cpu/mcf5227x/cpu_init.c
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/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/rtc.h>
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
/* Workaround, must place before fbcs */
pll->psr = 0x12;
scm1->mpr = 0x77777777;
scm1->pacra = 0;
scm1->pacrb = 0;
scm1->pacrc = 0;
scm1->pacrd = 0;
scm1->pacre = 0;
scm1->pacrf = 0;
scm1->pacrg = 0;
scm1->pacri = 0;
#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
fbcs->csar0 = CFG_CS0_BASE;
fbcs->cscr0 = CFG_CS0_CTRL;
fbcs->csmr0 = CFG_CS0_MASK;
#endif
#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
fbcs->csar1 = CFG_CS1_BASE;
fbcs->cscr1 = CFG_CS1_CTRL;
fbcs->csmr1 = CFG_CS1_MASK;
#endif
#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
fbcs->csar2 = CFG_CS2_BASE;
fbcs->cscr2 = CFG_CS2_CTRL;
fbcs->csmr2 = CFG_CS2_MASK;
#endif
#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
fbcs->csar3 = CFG_CS3_BASE;
fbcs->cscr3 = CFG_CS3_CTRL;
fbcs->csmr3 = CFG_CS3_MASK;
#endif
#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
fbcs->csar4 = CFG_CS4_BASE;
fbcs->cscr4 = CFG_CS4_CTRL;
fbcs->csmr4 = CFG_CS4_MASK;
#endif
#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
fbcs->csar5 = CFG_CS5_BASE;
fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK;
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
#endif
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r(void)
{
#ifdef CONFIG_MCFTMR
volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
u32 oscillator = CFG_RTC_OSCILLATOR;
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
#endif
return (0);
}
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
gpio->par_uart &=
(GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
gpio->par_uart |=
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
gpio->par_uart &=
(GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
gpio->par_uart |=
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
gpio->par_dspi &=
(GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
gpio->par_dspi =
(GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
}
}

52
cpu/mcf5227x/interrupts.c
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/*
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrh0 |= 0xFFFFFFFF;
intp->imrl0 |= 0xFFFFFFFF;
enable_interrupts();
return 0;
}
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
intp->imrh0 &= ~CFG_TMRINTR_MASK;
}
#endif

120
cpu/mcf5227x/speed.c
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/*
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Low Power Divider specifications
*/
#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
#define CLOCK_PLL_FVCO_MAX 540000000
#define CLOCK_PLL_FVCO_MIN 300000000
#define CLOCK_PLL_FSYS_MAX 266666666
#define CLOCK_PLL_FSYS_MIN 100000000
#define MHZ 1000000
void clock_enter_limp(int lpdiv)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
if (lpdiv < CLOCK_LPD_MIN)
lpdiv = CLOCK_LPD_MIN;
if (lpdiv > CLOCK_LPD_MAX)
lpdiv = CLOCK_LPD_MAX;
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
/* Enable Limp Mode */
ccm->misccr |= CCM_MISCCR_LIMP;
}
/*
* brief Exit Limp mode
* warning The PLL should be set and locked prior to exiting Limp mode
*/
void clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
/* Exit Limp mode */
ccm->misccr &= ~CCM_MISCCR_LIMP;
/* Wait for the PLL to lock */
while (!(pll->psr & PLL_PSR_LOCK)) ;
}
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
bootmode = (ccm->ccr & 0x000C) >> 2;
pcrvalue = pll->pcr & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr != 0x1E) {
/* serial mode */
} else {
/* Normal Mode */
vco = pfdr * CFG_INPUT_CLKSRC;
gd->vco_clk = vco;
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->flb_clk = vco / temp; /* flexbus clock */
gd->bus_clk = gd->flb_clk;
}
return (0);
}

356
cpu/mcf5227x/start.S
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/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
/* last three long word reserved for cache status */
#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@;
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte;
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
vector02: .long _FAULT /* Access Error */
vector03: .long _FAULT /* Address Error */
vector04: .long _FAULT /* Illegal Instruction */
vector05: .long _FAULT /* Reserved */
vector06: .long _FAULT /* Reserved */
vector07: .long _FAULT /* Reserved */
vector08: .long _FAULT /* Privilege Violation */
vector09: .long _FAULT /* Trace */
vector0A: .long _FAULT /* Unimplemented A-Line */
vector0B: .long _FAULT /* Unimplemented F-Line */
vector0C: .long _FAULT /* Debug Interrupt */
vector0D: .long _FAULT /* Reserved */
vector0E: .long _FAULT /* Format Error */
vector0F: .long _FAULT /* Unitialized Int. */
/* Reserved */
vector10_17:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector18: .long _FAULT /* Spurious Interrupt */
vector19: .long _FAULT /* Autovector Level 1 */
vector1A: .long _FAULT /* Autovector Level 2 */
vector1B: .long _FAULT /* Autovector Level 3 */
vector1C: .long _FAULT /* Autovector Level 4 */
vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
/* Reserved */
vector30_3F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector64_127:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector128_191:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
move.l #(CACR_STATUS), %a3 /* CACR */
move.l %d0, (%a1)
move.l %d0, (%a2)
move.l %d0, (%a3)
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
bsr cpu_init_f /* run low-level CPU init code (from flash) */
bsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/*------------------------------------------------------------------------------*/
/* exception code */
.globl _fault
_fault:
jmp _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/*------------------------------------------------------------------------------*/
/* cache functions */
.globl icache_enable
icache_enable:
move.l #0x01200000, %d0 /* Invalid cache */
movec %d0, %CACR
move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0
move.l #0x81600610, %d0 /* Enable cache */
movec %d0, %CACR
move.l #(ICACHE_STATUS), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
.globl icache_disable
icache_disable:
move.l #0x01F00000, %d0 /* Setup cache mask */
movec %d0, %CACR /* Invalidate icache */
clr.l %d0
movec %d0, %ACR0
movec %d0, %ACR1
move.l #(ICACHE_STATUS), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl icache_status
icache_status:
move.l #(ICACHE_STATUS), %a1
move.l (%a1), %d0
rts
.globl icache_invalid
icache_invalid:
move.l #0x80600610, %d0 /* Invalidate icache */
movec %d0, %CACR /* Enable and invalidate cache */
rts
.globl dcache_enable
dcache_enable:
move.l #0x01200000, %d0 /* Invalid cache */
movec %d0, %CACR
move.l #0x81300610, %d0
movec %d0, %CACR
move.l #(DCACHE_STATUS), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
.globl dcache_disable
dcache_disable:
move.l #0x81600610, %d0 /* Setup cache mask */
movec %d0, %CACR /* Invalidate icache */
move.l #(DCACHE_STATUS), %a1
moveq #0, %d0
move.l %d0, (%a1)
rts
.globl dcache_invalid
dcache_invalid:
move.l #0x81100610, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable and invalidate cache */
rts
.globl dcache_status
dcache_status:
move.l #(DCACHE_STATUS), %a1
move.l (%a1), %d0
rts
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"

343
include/asm-m68k/immap_5227x.h
Unescape View File

@ -0,0 +1,343 @@
/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5227X__
#define __IMMAP_5227X__
/* Module Base Addresses */
#define MMAP_SCM1 (CFG_MBAR + 0x00000000)
#define MMAP_XBS (CFG_MBAR + 0x00004000)
#define MMAP_FBCS (CFG_MBAR + 0x00008000)
#define MMAP_CAN (CFG_MBAR + 0x00020000)
#define MMAP_RTC (CFG_MBAR + 0x0003C000)
#define MMAP_SCM2 (CFG_MBAR + 0x00040010)
#define MMAP_SCM3 (CFG_MBAR + 0x00040070)
#define MMAP_EDMA (CFG_MBAR + 0x00044000)
#define MMAP_INTC0 (CFG_MBAR + 0x00048000)
#define MMAP_INTC1 (CFG_MBAR + 0x0004C000)
#define MMAP_IACK (CFG_MBAR + 0x00054000)
#define MMAP_I2C (CFG_MBAR + 0x00058000)
#define MMAP_DSPI (CFG_MBAR + 0x0005C000)
#define MMAP_UART0 (CFG_MBAR + 0x00060000)
#define MMAP_UART1 (CFG_MBAR + 0x00064000)
#define MMAP_UART2 (CFG_MBAR + 0x00068000)
#define MMAP_DTMR0 (CFG_MBAR + 0x00070000)
#define MMAP_DTMR1 (CFG_MBAR + 0x00074000)
#define MMAP_DTMR2 (CFG_MBAR + 0x00078000)
#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000)
#define MMAP_PIT0 (CFG_MBAR + 0x00080000)
#define MMAP_PIT1 (CFG_MBAR + 0x00084000)
#define MMAP_PWM (CFG_MBAR + 0x00090000)
#define MMAP_EPORT (CFG_MBAR + 0x00094000)
#define MMAP_RCM (CFG_MBAR + 0x000A0000)
#define MMAP_CCM (CFG_MBAR + 0x000A0004)
#define MMAP_GPIO (CFG_MBAR + 0x000A4000)
#define MMAP_ADC (CFG_MBAR + 0x000A8000)
#define MMAP_LCD (CFG_MBAR + 0x000AC000)
#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800)
#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00)
#define MMAP_USBHW (CFG_MBAR + 0x000B0000)
#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100)
#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140)
#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0)
#define MMAP_SDRAM (CFG_MBAR + 0x000B8000)
#define MMAP_SSI (CFG_MBAR + 0x000BC000)
#define MMAP_PLL (CFG_MBAR + 0x000C0000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u16 ccr; /* Chip Configuration (Rd-only) */
u16 resv1;
u16 rcon; /* Reset Configuration (Rd-only) */
u16 cir; /* Chip Identification (Rd-only) */
u32 resv2;
u16 misccr; /* Miscellaneous Control */
u16 cdr; /* Clock Divider */
u16 uocsr; /* USB On-the-Go Controller Status */
u16 resv4;
u16 sbfsr; /* Serial Boot Status */
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_be; /* 0x00 */
u8 podr_cs; /* 0x01 */
u8 podr_fbctl; /* 0x02 */
u8 podr_i2c; /* 0x03 */
u8 rsvd1; /* 0x04 */
u8 podr_uart; /* 0x05 */
u8 podr_dspi; /* 0x06 */
u8 podr_timer; /* 0x07 */
u8 podr_lcdctl; /* 0x08 */
u8 podr_lcddatah; /* 0x09 */
u8 podr_lcddatam; /* 0x0A */
u8 podr_lcddatal; /* 0x0B */
/* Port Data Direction Registers */
u8 pddr_be; /* 0x0C */
u8 pddr_cs; /* 0x0D */
u8 pddr_fbctl; /* 0x0E */
u8 pddr_i2c; /* 0x0F */
u8 rsvd2; /* 0x10 */
u8 pddr_uart; /* 0x11 */
u8 pddr_dspi; /* 0x12 */
u8 pddr_timer; /* 0x13 */
u8 pddr_lcdctl; /* 0x14 */
u8 pddr_lcddatah; /* 0x15 */
u8 pddr_lcddatam; /* 0x16 */
u8 pddr_lcddatal; /* 0x17 */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_be; /* 0x18 */
u8 ppdsdr_cs; /* 0x19 */
u8 ppdsdr_fbctl; /* 0x1A */
u8 ppdsdr_i2c; /* 0x1B */
u8 rsvd3; /* 0x1C */
u8 ppdsdr_uart; /* 0x1D */
u8 ppdsdr_dspi; /* 0x1E */
u8 ppdsdr_timer; /* 0x1F */
u8 ppdsdr_lcdctl; /* 0x20 */
u8 ppdsdr_lcddatah; /* 0x21 */
u8 ppdsdr_lcddatam; /* 0x22 */
u8 ppdsdr_lcddatal; /* 0x23 */
/* Port Clear Output Data Registers */
u8 pclrr_be; /* 0x24 */
u8 pclrr_cs; /* 0x25 */
u8 pclrr_fbctl; /* 0x26 */
u8 pclrr_i2c; /* 0x27 */
u8 rsvd4; /* 0x28 */
u8 pclrr_uart; /* 0x29 */
u8 pclrr_dspi; /* 0x2A */
u8 pclrr_timer; /* 0x2B */
u8 pclrr_lcdctl; /* 0x2C */
u8 pclrr_lcddatah; /* 0x2D */
u8 pclrr_lcddatam; /* 0x2E */
u8 pclrr_lcddatal; /* 0x2F */
/* Pin Assignment Registers */
u8 par_be; /* 0x30 */
u8 par_cs; /* 0x31 */
u8 par_fbctl; /* 0x32 */
u8 par_i2c; /* 0x33 */
u16 par_uart; /* 0x34 */
u8 par_dspi; /* 0x36 */
u8 par_timer; /* 0x37 */
u8 par_lcdctl; /* 0x38 */
u8 par_irq; /* 0x39 */
u16 rsvd6; /* 0x3A - 0x3B */
u32 par_lcdh; /* 0x3C */
u32 par_lcdl; /* 0x40 */
/* Mode select control registers */
u8 mscr_fb; /* 0x44 */
u8 mscr_sdram; /* 0x45 */
u16 rsvd7; /* 0x46 - 0x47 */
u8 dscr_dspi; /* 0x48 */
u8 dscr_timer; /* 0x49 */
u8 dscr_i2c; /* 0x4A */
u8 dscr_lcd; /* 0x4B */
u8 dscr_debug; /* 0x4C */
u8 dscr_clkrst; /* 0x4D */
u8 dscr_irq; /* 0x4E */
u8 dscr_uart; /* 0x4F */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* Mode/Extended Mode */
u32 sdcr; /* Control */
u32 sdcfg1; /* Configuration 1 */
u32 sdcfg2; /* Chip Select */
u8 resv0[0x100];
u32 sdcs0; /* Mode/Extended Mode */
u32 sdcs1; /* Mode/Extended Mode */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control */
u32 psr; /* PLL Status */
} pll_t;
/* System Control Module register */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 */
u32 pacrb; /* 0x24 */
u32 pacrc; /* 0x28 */
u32 pacrd; /* 0x2C */
u32 rsvd2[4];
u32 pacre; /* 0x40 */
u32 pacrf; /* 0x44 */
u32 pacrg; /* 0x48 */
u32 rsvd3;
u32 pacri; /* 0x50 */
} scm1_t;
typedef struct scm2_ctrl {
u8 res1[3]; /* 0x00 - 0x02 */
u8 wcr; /* 0x03 wakeup control */
u16 res2; /* 0x04 - 0x05 */
u16 cwcr; /* 0x06 Core Watchdog Control */
u8 res3[3]; /* 0x08 - 0x0A */
u8 cwsr; /* 0x0B Core Watchdog Service */
u8 res4[2]; /* 0x0C - 0x0D */
u8 scmisr; /* 0x0F Interrupt Status */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration */
} scm2_t;
typedef struct scm3_ctrl {
u32 cfadr; /* 0x00 Core Fault Address */
u8 res7; /* 0x04 */
u8 cfier; /* 0x05 Core Fault Interrupt Enable */
u8 cfloc; /* 0x06 Core Fault Location */
u8 cfatr; /* 0x07 Core Fault Attributes */
u32 cfdtr; /* 0x08 Core Fault Data */
} scm3_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5227X__ */
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