Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: George G. Davis <gdavis@mvista.com>master
Wolfgang Denk
14 years ago
committed by
Albert ARIBAUD
parent
689d0fa36a
commit
c91e90db8c
@ -1,53 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# 2004 (c) MontaVista Software, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := assabet.o
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SOBJS := setup.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,131 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* 2004 (c) MontaVista Software, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <SA-1100.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Board dependent initialisation |
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*/ |
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#define ECOR 0x8000 |
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#define ECOR_RESET 0x80 |
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#define ECOR_LEVEL_IRQ 0x40 |
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#define ECOR_WR_ATTRIB 0x04 |
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#define ECOR_ENABLE 0x01 |
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#define ECSR 0x8002 |
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#define ECSR_IOIS8 0x20 |
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#define ECSR_PWRDWN 0x04 |
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#define ECSR_INT 0x02 |
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#define SMC_IO_SHIFT 2 |
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#define NCR_0 (*((volatile u_char *)(0x100000a0))) |
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#define NCR_ENET_OSC_EN (1<<3) |
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static inline u8 |
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readb(volatile u8 * p) |
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{ |
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return *p; |
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} |
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static inline void |
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writeb(u8 v, volatile u8 * p) |
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{ |
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*p = v; |
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} |
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static void |
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smc_init(void) |
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{ |
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u8 ecor; |
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u8 ecsr; |
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volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); |
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NCR_0 |= NCR_ENET_OSC_EN; |
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udelay(100); |
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ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; |
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writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); |
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udelay(100); |
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/*
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* The device will ignore all writes to the enable bit while |
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* reset is asserted, even if the reset bit is cleared in the |
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* same write. Must clear reset first, then enable the device. |
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*/ |
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writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); |
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writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); |
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/*
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* Set the appropriate byte/word mode. |
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*/ |
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ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; |
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ecsr |= ECSR_IOIS8; |
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writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); |
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udelay(100); |
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} |
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static void |
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neponset_init(void) |
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{ |
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smc_init(); |
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} |
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int |
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board_init(void) |
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{ |
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gd->bd->bi_arch_number = MACH_TYPE_ASSABET; |
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gd->bd->bi_boot_params = 0xc0000100; |
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neponset_init(); |
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return 0; |
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} |
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int |
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dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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return (0); |
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} |
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_LAN91C96 |
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rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
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@ -1,7 +0,0 @@ |
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#
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# SA-1110 based Intel Assabet board
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#
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# The Intel Assabet 1 bank of 32 MiB SDRAM
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#
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CONFIG_SYS_TEXT_BASE = 0xc1f00000
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@ -1,136 +0,0 @@ |
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/* |
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* Memory Setup stuff - taken from blob memsetup.S |
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* |
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* 2004 (c) MontaVista Software, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include "config.h" |
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#include "version.h" |
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/*----------------------------------------------------------------------- |
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* Board defines: |
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*/ |
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#define MDCNFG 0x00 |
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#define MDCAS00 0x04 |
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#define MDCAS01 0x08 |
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#define MDCAS02 0x0C |
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#define MSC0 0x10 |
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#define MSC1 0x14 |
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#define MECR 0x18 |
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#define MDREFR 0x1C |
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#define MDCAS20 0x20 |
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#define MDCAS21 0x24 |
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#define MDCAS22 0x28 |
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#define MSC2 0x2C |
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#define SMCNFG 0x30 |
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#define ASSABET_BCR (0x12000000) |
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#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) |
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#define ASSABET_SCR_nNEPONSET (1 << 9) |
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#define NEPONSET_LEDS (0x10000010) |
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/*----------------------------------------------------------------------- |
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* Setup parameters for the board: |
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*/ |
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MEM_BASE: .long 0xa0000000 |
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MEM_START: .long 0xc0000000 |
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mdcnfg: .long 0x72547254 |
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mdcas00: .long 0xaaaaaa7f |
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mdcas01: .long 0xaaaaaaaa |
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mdcas02: .long 0xaaaaaaaa |
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msc0: .long 0x4b384370 |
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msc1: .long 0x22212419 |
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mecr: .long 0x994a994a |
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mdrefr: .long 0x04340327 |
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mdcas20: .long 0xaaaaaa7f |
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mdcas21: .long 0xaaaaaaaa |
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mdcas22: .long 0xaaaaaaaa |
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msc2: .long 0x42196669 |
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smcnfg: .long 0x00000000 |
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BCR: .long ASSABET_BCR |
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BCR_DB1110: .long ASSABET_BCR_DB1110 |
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LEDS: .long NEPONSET_LEDS |
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.globl lowlevel_init
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lowlevel_init: |
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/* Setting up the memory and stuff */ |
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ldr r0, MEM_BASE |
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ldr r1, mdcas00 |
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str r1, [r0, #MDCAS00] |
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ldr r1, mdcas01 |
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str r1, [r0, #MDCAS01] |
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ldr r1, mdcas02 |
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str r1, [r0, #MDCAS02] |
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ldr r1, mdcas20 |
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str r1, [r0, #MDCAS20] |
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ldr r1, mdcas21 |
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str r1, [r0, #MDCAS21] |
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ldr r1, mdcas22 |
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str r1, [r0, #MDCAS22] |
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ldr r1, mdrefr |
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str r1, [r0, #MDREFR] |
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ldr r1, mecr |
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str r1, [r0, #MECR] |
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ldr r1, msc0 |
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str r1, [r0, #MSC0] |
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ldr r1, msc1 |
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str r1, [r0, #MSC1] |
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ldr r1, msc2 |
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str r1, [r0, #MSC2] |
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ldr r1, smcnfg |
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str r1, [r0, #SMCNFG] |
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ldr r1, mdcnfg |
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str r1, [r0, #MDCNFG] |
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/* Load something to activate bank */ |
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ldr r2, MEM_START |
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.rept 8
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ldr r3, [r2] |
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.endr |
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/* Enable SDRAM */ |
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orr r1, r1, #0x00000001 |
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str r1, [r0, #MDCNFG] |
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ldr r1, BCR |
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ldr r2, BCR_DB1110 |
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str r2, [r1] |
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ldr r1, LEDS |
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mov r0, #0x3 |
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str r0, [r1] |
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/* All done... */ |
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mov pc, lr |
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@ -1,173 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* 2004 (c) MontaVista Software, Inc. |
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* |
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* Configuation settings for the Intel Assabet board. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ |
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#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ |
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#undef CONFIG_USE_IRQ |
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/* we will never enable dcache, because we have to setup MMU first */ |
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#define CONFIG_SYS_DCACHE_OFF |
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS 1 |
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#define CONFIG_INITRD_TAG 1 |
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/*
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
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/*
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* Hardware drivers |
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*/ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */ |
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#define CONFIG_LAN91C96_BASE 0x18000000 |
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/*
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* select serial console configuration |
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*/ |
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#define CONFIG_SA1100_SERIAL |
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ |
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/* allow to overwrite serial and ethaddr */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_BAUDRATE 115200 |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" |
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#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" |
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#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
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#endif |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ |
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#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ |
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#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
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#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */ |
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/* valid baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*-----------------------------------------------------------------------
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* Stack sizes |
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* |
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* The stack sizes are set up in start.S using the settings below |
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*/ |
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
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#ifdef CONFIG_USE_IRQ |
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
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#endif |
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/*-----------------------------------------------------------------------
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* Physical Memory Map |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ |
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#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ |
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ |
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#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ |
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ |
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#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_RAMSTART |
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#endif |
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/*-----------------------------------------------------------------------
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* FLASH and environment organization |
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*/ |
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
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#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE |
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#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ |
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#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ |
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#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ |
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#undef CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#if defined(CONFIG_ENV_IS_IN_FLASH) |
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#define CONFIG_ENV_IN_OWN_SECTOR 1 |
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) |
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#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE |
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#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE |
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#endif |
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#endif /* __CONFIG_H */ |
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