Tom Rini
12 years ago
commit
ca85eb8c42
@ -0,0 +1,473 @@ |
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/*
|
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* Faraday 10/100Mbps Ethernet Controller |
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* |
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* (C) Copyright 2010 Faraday Technology |
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* Dante Su <dantesu@faraday-tech.com> |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <asm/errno.h> |
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#include <asm/io.h> |
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#include <asm/dma-mapping.h> |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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#include <miiphy.h> |
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#endif |
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#include "ftmac110.h" |
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#define CFG_RXDES_NUM 8 |
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#define CFG_TXDES_NUM 2 |
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#define CFG_XBUF_SIZE 1536 |
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#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ |
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#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ |
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#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */ |
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/*
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* FTMAC110 DMA design issue |
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* |
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* Its DMA engine has a weird restriction that its Rx DMA engine |
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* accepts only 16-bits aligned address, 32-bits aligned is not |
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* acceptable. However this restriction does not apply to Tx DMA. |
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* |
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* Conclusion: |
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* (1) Tx DMA Buffer Address: |
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* 1 bytes aligned: Invalid |
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* 2 bytes aligned: O.K |
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* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible) |
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* (2) Rx DMA Buffer Address: |
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* 1 bytes aligned: Invalid |
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* 2 bytes aligned: O.K |
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* 4 bytes aligned: Invalid |
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*/ |
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struct ftmac110_chip { |
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void __iomem *regs; |
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uint32_t imr; |
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uint32_t maccr; |
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uint32_t lnkup; |
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uint32_t phy_addr; |
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struct ftmac110_rxd *rxd; |
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ulong rxd_dma; |
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uint32_t rxd_idx; |
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struct ftmac110_txd *txd; |
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ulong txd_dma; |
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uint32_t txd_idx; |
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}; |
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static int ftmac110_reset(struct eth_device *dev); |
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static uint16_t mdio_read(struct eth_device *dev, |
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uint8_t phyaddr, uint8_t phyreg) |
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{ |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_regs __iomem *regs = chip->regs; |
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uint32_t tmp, ts; |
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uint16_t ret = 0xffff; |
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tmp = PHYCR_READ |
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| (phyaddr << PHYCR_ADDR_SHIFT) |
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| (phyreg << PHYCR_REG_SHIFT); |
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writel(tmp, ®s->phycr); |
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for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) { |
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tmp = readl(®s->phycr); |
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if (tmp & PHYCR_READ) |
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continue; |
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break; |
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} |
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if (tmp & PHYCR_READ) |
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printf("ftmac110: mdio read timeout\n"); |
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else |
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ret = (uint16_t)(tmp & 0xffff); |
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return ret; |
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} |
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static void mdio_write(struct eth_device *dev, |
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uint8_t phyaddr, uint8_t phyreg, uint16_t phydata) |
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{ |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_regs __iomem *regs = chip->regs; |
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uint32_t tmp, ts; |
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tmp = PHYCR_WRITE |
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| (phyaddr << PHYCR_ADDR_SHIFT) |
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| (phyreg << PHYCR_REG_SHIFT); |
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writel(phydata, ®s->phydr); |
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writel(tmp, ®s->phycr); |
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for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) { |
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if (readl(®s->phycr) & PHYCR_WRITE) |
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continue; |
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break; |
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} |
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if (readl(®s->phycr) & PHYCR_WRITE) |
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printf("ftmac110: mdio write timeout\n"); |
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} |
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static uint32_t ftmac110_phyqry(struct eth_device *dev) |
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{ |
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ulong ts; |
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uint32_t maccr; |
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uint16_t pa, tmp, bmsr, bmcr; |
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struct ftmac110_chip *chip = dev->priv; |
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/* Default = 100Mbps Full */ |
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maccr = MACCR_100M | MACCR_FD; |
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/* 1. find the phy device */ |
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for (pa = 0; pa < 32; ++pa) { |
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tmp = mdio_read(dev, pa, MII_PHYSID1); |
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if (tmp == 0xFFFF || tmp == 0x0000) |
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continue; |
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chip->phy_addr = pa; |
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break; |
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} |
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if (pa >= 32) { |
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puts("ftmac110: phy device not found!\n"); |
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goto exit; |
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} |
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/* 2. wait until link-up & auto-negotiation complete */ |
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chip->lnkup = 0; |
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bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR); |
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ts = get_timer(0); |
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do { |
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bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR); |
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chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0; |
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if (!chip->lnkup) |
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continue; |
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if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE)) |
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break; |
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} while (get_timer(ts) < CFG_LINKUP_TIMEOUT); |
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if (!chip->lnkup) { |
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puts("ftmac110: link down\n"); |
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goto exit; |
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} |
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if (!(bmcr & BMCR_ANENABLE)) |
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puts("ftmac110: auto negotiation disabled\n"); |
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else if (!(bmsr & BMSR_ANEGCOMPLETE)) |
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puts("ftmac110: auto negotiation timeout\n"); |
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/* 3. derive MACCR */ |
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if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) { |
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tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE); |
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tmp &= mdio_read(dev, chip->phy_addr, MII_LPA); |
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if (tmp & LPA_100FULL) /* 100Mbps full-duplex */ |
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maccr = MACCR_100M | MACCR_FD; |
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else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */ |
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maccr = MACCR_100M; |
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else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */ |
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maccr = MACCR_FD; |
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else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */ |
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maccr = 0; |
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} else { |
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if (bmcr & BMCR_SPEED100) |
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maccr = MACCR_100M; |
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else |
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maccr = 0; |
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if (bmcr & BMCR_FULLDPLX) |
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maccr |= MACCR_FD; |
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} |
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exit: |
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printf("ftmac110: %d Mbps, %s\n", |
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(maccr & MACCR_100M) ? 100 : 10, |
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(maccr & MACCR_FD) ? "Full" : "half"); |
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return maccr; |
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} |
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static int ftmac110_reset(struct eth_device *dev) |
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{ |
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uint8_t *a; |
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uint32_t i, maccr; |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_regs __iomem *regs = chip->regs; |
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/* 1. MAC reset */ |
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writel(MACCR_RESET, ®s->maccr); |
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for (i = get_timer(0); get_timer(i) < 1000; ) { |
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if (readl(®s->maccr) & MACCR_RESET) |
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continue; |
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break; |
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} |
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if (readl(®s->maccr) & MACCR_RESET) { |
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printf("ftmac110: reset failed\n"); |
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return -ENXIO; |
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} |
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/* 1-1. Init tx ring */ |
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for (i = 0; i < CFG_TXDES_NUM; ++i) { |
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/* owned by SW */ |
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chip->txd[i].ct[0] = 0; |
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} |
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chip->txd_idx = 0; |
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/* 1-2. Init rx ring */ |
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for (i = 0; i < CFG_RXDES_NUM; ++i) { |
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/* owned by HW */ |
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chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); |
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} |
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chip->rxd_idx = 0; |
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/* 2. PHY status query */ |
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maccr = ftmac110_phyqry(dev); |
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/* 3. Fix up the MACCR value */ |
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chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT |
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| MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN; |
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/* 4. MAC address setup */ |
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a = dev->enetaddr; |
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writel(a[1] | (a[0] << 8), ®s->mac[0]); |
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writel(a[5] | (a[4] << 8) | (a[3] << 16) |
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| (a[2] << 24), ®s->mac[1]); |
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/* 5. MAC registers setup */ |
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writel(chip->rxd_dma, ®s->rxba); |
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writel(chip->txd_dma, ®s->txba); |
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/* interrupt at each tx/rx */ |
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writel(ITC_DEFAULT, ®s->itc); |
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/* no tx pool, rx poll = 1 normal cycle */ |
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writel(APTC_DEFAULT, ®s->aptc); |
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/* rx threshold = [6/8 fifo, 2/8 fifo] */ |
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writel(DBLAC_DEFAULT, ®s->dblac); |
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/* disable & clear all interrupt status */ |
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chip->imr = 0; |
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writel(ISR_ALL, ®s->isr); |
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writel(chip->imr, ®s->imr); |
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/* enable mac */ |
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writel(chip->maccr, ®s->maccr); |
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return 0; |
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} |
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static int ftmac110_probe(struct eth_device *dev, bd_t *bis) |
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{ |
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debug("ftmac110: probe\n"); |
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if (ftmac110_reset(dev)) |
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return -1; |
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return 0; |
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} |
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static void ftmac110_halt(struct eth_device *dev) |
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{ |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_regs __iomem *regs = chip->regs; |
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writel(0, ®s->imr); |
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writel(0, ®s->maccr); |
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debug("ftmac110: halt\n"); |
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} |
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static int ftmac110_send(struct eth_device *dev, void *pkt, int len) |
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{ |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_regs __iomem *regs = chip->regs; |
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struct ftmac110_txd *des; |
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if (!chip->lnkup) |
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return 0; |
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if (len <= 0 || len > CFG_XBUF_SIZE) { |
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printf("ftmac110: bad tx pkt len(%d)\n", len); |
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return 0; |
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} |
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len = max(60, len); |
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des = &chip->txd[chip->txd_idx]; |
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if (le32_to_cpu(des->ct[0]) & FTMAC110_TXCT0_OWNER) { |
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/* kick-off Tx DMA */ |
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writel(0xffffffff, ®s->txpd); |
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printf("ftmac110: out of txd\n"); |
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return 0; |
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} |
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memcpy(des->vbuf, (void *)pkt, len); |
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dma_map_single(des->vbuf, len, DMA_TO_DEVICE); |
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/* update len, fts and lts */ |
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des->ct[1] &= cpu_to_le32(FTMAC110_TXCT1_END); |
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des->ct[1] |= cpu_to_le32(FTMAC110_TXCT1_LEN(len) |
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| FTMAC110_TXCT1_FTS | FTMAC110_TXCT1_LTS); |
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/* set owner bit and clear others */ |
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des->ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER); |
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/* kick-off Tx DMA */ |
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writel(0xffffffff, ®s->txpd); |
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chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM; |
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return len; |
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} |
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static int ftmac110_recv(struct eth_device *dev) |
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{ |
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struct ftmac110_chip *chip = dev->priv; |
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struct ftmac110_rxd *des; |
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uint32_t ct0, len, rlen = 0; |
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uint8_t *buf; |
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if (!chip->lnkup) |
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return 0; |
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do { |
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des = &chip->rxd[chip->rxd_idx]; |
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ct0 = le32_to_cpu(des->ct[0]); |
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if (ct0 & FTMAC110_RXCT0_OWNER) |
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break; |
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len = FTMAC110_RXCT0_LEN(ct0); |
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buf = des->vbuf; |
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if (ct0 & FTMAC110_RXCT0_ERRMASK) { |
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printf("ftmac110: rx error\n"); |
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} else { |
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dma_map_single(buf, len, DMA_FROM_DEVICE); |
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NetReceive(buf, len); |
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rlen += len; |
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} |
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/* owned by hardware */ |
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des->ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); |
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chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM; |
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} while (0); |
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return rlen; |
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} |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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static int ftmac110_mdio_read( |
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const char *devname, uint8_t addr, uint8_t reg, uint16_t *value) |
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{ |
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int ret = 0; |
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struct eth_device *dev; |
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dev = eth_get_dev_by_name(devname); |
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if (dev == NULL) { |
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printf("%s: no such device\n", devname); |
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ret = -1; |
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} else { |
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*value = mdio_read(dev, addr, reg); |
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} |
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return ret; |
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} |
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static int ftmac110_mdio_write( |
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const char *devname, uint8_t addr, uint8_t reg, uint16_t value) |
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{ |
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int ret = 0; |
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struct eth_device *dev; |
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dev = eth_get_dev_by_name(devname); |
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if (dev == NULL) { |
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printf("%s: no such device\n", devname); |
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ret = -1; |
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} else { |
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mdio_write(dev, addr, reg, value); |
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} |
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return ret; |
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} |
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#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */ |
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int ftmac110_initialize(bd_t *bis) |
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{ |
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int i, card_nr = 0; |
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struct eth_device *dev; |
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struct ftmac110_chip *chip; |
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dev = malloc(sizeof(*dev) + sizeof(*chip)); |
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if (dev == NULL) { |
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panic("ftmac110: out of memory 1\n"); |
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return -1; |
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} |
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chip = (struct ftmac110_chip *)(dev + 1); |
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memset(dev, 0, sizeof(*dev) + sizeof(*chip)); |
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sprintf(dev->name, "FTMAC110#%d", card_nr); |
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dev->iobase = CONFIG_FTMAC110_BASE; |
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chip->regs = (void __iomem *)dev->iobase; |
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dev->priv = chip; |
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dev->init = ftmac110_probe; |
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dev->halt = ftmac110_halt; |
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dev->send = ftmac110_send; |
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dev->recv = ftmac110_recv; |
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if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) |
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eth_random_enetaddr(dev->enetaddr); |
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/* allocate tx descriptors (it must be 16 bytes aligned) */ |
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chip->txd = dma_alloc_coherent( |
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sizeof(struct ftmac110_txd) * CFG_TXDES_NUM, &chip->txd_dma); |
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if (!chip->txd) |
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panic("ftmac110: out of memory 3\n"); |
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memset(chip->txd, 0, |
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sizeof(struct ftmac110_txd) * CFG_TXDES_NUM); |
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for (i = 0; i < CFG_TXDES_NUM; ++i) { |
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void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); |
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if (!va) |
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panic("ftmac110: out of memory 4\n"); |
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chip->txd[i].vbuf = va; |
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chip->txd[i].buf = cpu_to_le32(virt_to_phys(va)); |
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chip->txd[i].ct[1] = 0; |
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chip->txd[i].ct[0] = 0; /* owned by SW */ |
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} |
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chip->txd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_TXCT1_END); |
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chip->txd_idx = 0; |
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|
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/* allocate rx descriptors (it must be 16 bytes aligned) */ |
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chip->rxd = dma_alloc_coherent( |
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sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM, &chip->rxd_dma); |
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if (!chip->rxd) |
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panic("ftmac110: out of memory 4\n"); |
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memset((void *)chip->rxd, 0, |
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sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM); |
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for (i = 0; i < CFG_RXDES_NUM; ++i) { |
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void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2); |
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if (!va) |
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panic("ftmac110: out of memory 5\n"); |
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/* it needs to be exactly 2 bytes aligned */ |
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va = ((uint8_t *)va + 2); |
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chip->rxd[i].vbuf = va; |
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chip->rxd[i].buf = cpu_to_le32(virt_to_phys(va)); |
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chip->rxd[i].ct[1] = cpu_to_le32(CFG_XBUF_SIZE); |
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chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER); |
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} |
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chip->rxd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_RXCT1_END); |
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chip->rxd_idx = 0; |
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eth_register(dev); |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write); |
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#endif |
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card_nr++; |
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return card_nr; |
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} |
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@ -0,0 +1,177 @@ |
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/*
|
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* Faraday 10/100Mbps Ethernet Controller |
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* |
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* (C) Copyright 2010 Faraday Technology |
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* Dante Su <dantesu@faraday-tech.com> |
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* |
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* This file is released under the terms of GPL v2 and any later version. |
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* See the file COPYING in the root directory of the source tree for details. |
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*/ |
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|
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#ifndef _FTMAC110_H |
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#define _FTMAC110_H |
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|
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struct ftmac110_regs { |
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uint32_t isr; /* 0x00: Interrups Status Register */ |
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uint32_t imr; /* 0x04: Interrupt Mask Register */ |
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uint32_t mac[2]; /* 0x08: MAC Address */ |
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uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */ |
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uint32_t txpd; /* 0x18: Tx Poll Demand Register */ |
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uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */ |
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uint32_t txba; /* 0x20: Tx Ring Base Address Register */ |
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uint32_t rxba; /* 0x24: Rx Ring Base Address Register */ |
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uint32_t itc; /* 0x28: Interrupt Timer Control Register */ |
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uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */ |
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uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */ |
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uint32_t revr; /* 0x34: Revision Register */ |
||||
uint32_t fear; /* 0x38: Feature Register */ |
||||
uint32_t rsvd[19]; |
||||
uint32_t maccr; /* 0x88: MAC Control Register */ |
||||
uint32_t macsr; /* 0x8C: MAC Status Register */ |
||||
uint32_t phycr; /* 0x90: PHY Control Register */ |
||||
uint32_t phydr; /* 0x94: PHY Data Register */ |
||||
uint32_t fcr; /* 0x98: Flow Control Register */ |
||||
uint32_t bpr; /* 0x9C: Back Pressure Register */ |
||||
}; |
||||
|
||||
/*
|
||||
* Interrupt status/mask register(ISR/IMR) bits |
||||
*/ |
||||
#define ISR_ALL 0x3ff |
||||
#define ISR_PHYSTCHG (1 << 9) /* phy status change */ |
||||
#define ISR_AHBERR (1 << 8) /* bus error */ |
||||
#define ISR_RXLOST (1 << 7) /* rx lost */ |
||||
#define ISR_RXFIFO (1 << 6) /* rx to fifo */ |
||||
#define ISR_TXLOST (1 << 5) /* tx lost */ |
||||
#define ISR_TXOK (1 << 4) /* tx to ethernet */ |
||||
#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */ |
||||
#define ISR_TXFIFO (1 << 2) /* tx to fifo */ |
||||
#define ISR_NORXBUF (1 << 1) /* out of rx buffer */ |
||||
#define ISR_RXOK (1 << 0) /* rx to buffer */ |
||||
|
||||
/*
|
||||
* MACCR control bits |
||||
*/ |
||||
#define MACCR_100M (1 << 18) /* 100Mbps mode */ |
||||
#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */ |
||||
#define MACCR_RXMCST (1 << 16) /* rx multicast packet */ |
||||
#define MACCR_FD (1 << 15) /* full duplex */ |
||||
#define MACCR_CRCAPD (1 << 14) /* tx crc append */ |
||||
#define MACCR_RXALL (1 << 12) /* rx all packets */ |
||||
#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */ |
||||
#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */ |
||||
#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */ |
||||
#define MACCR_RXEN (1 << 8) /* rx enable */ |
||||
#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */ |
||||
#define MACCR_TXEN (1 << 5) /* tx enable */ |
||||
#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */ |
||||
#define MACCR_LOOPBACK (1 << 3) /* loop-back */ |
||||
#define MACCR_RESET (1 << 2) /* reset */ |
||||
#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */ |
||||
#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */ |
||||
|
||||
/*
|
||||
* PHYCR control bits |
||||
*/ |
||||
#define PHYCR_READ (1 << 26) |
||||
#define PHYCR_WRITE (1 << 27) |
||||
#define PHYCR_REG_SHIFT 21 |
||||
#define PHYCR_ADDR_SHIFT 16 |
||||
|
||||
/*
|
||||
* ITC control bits |
||||
*/ |
||||
|
||||
/* Tx Cycle Length */ |
||||
#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */ |
||||
#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */ |
||||
/* Tx Threshold: Aggregate n interrupts as 1 interrupt */ |
||||
#define ITC_TX_THR(n) (((n) & 0x7) << 12) |
||||
/* Tx Interrupt Timeout = n * Tx Cycle */ |
||||
#define ITC_TX_ITMO(n) (((n) & 0xf) << 8) |
||||
/* Rx Cycle Length */ |
||||
#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */ |
||||
#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */ |
||||
/* Rx Threshold: Aggregate n interrupts as 1 interrupt */ |
||||
#define ITC_RX_THR(n) (((n) & 0x7) << 4) |
||||
/* Rx Interrupt Timeout = n * Rx Cycle */ |
||||
#define ITC_RX_ITMO(n) (((n) & 0xf) << 0) |
||||
|
||||
#define ITC_DEFAULT \ |
||||
(ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0)) |
||||
|
||||
/*
|
||||
* APTC contrl bits |
||||
*/ |
||||
|
||||
/* Tx Cycle Length */ |
||||
#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */ |
||||
#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */ |
||||
/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */ |
||||
#define APTC_TX_PTMO(n) (((n) & 0xf) << 8) |
||||
/* Rx Cycle Length */ |
||||
#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */ |
||||
#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */ |
||||
/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */ |
||||
#define APTC_RX_PTMO(n) (((n) & 0xf) << 0) |
||||
|
||||
#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1)) |
||||
|
||||
/*
|
||||
* DBLAC contrl bits |
||||
*/ |
||||
#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */ |
||||
#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */ |
||||
#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */ |
||||
#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */ |
||||
#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */ |
||||
#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */ |
||||
#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */ |
||||
#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */ |
||||
#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */ |
||||
|
||||
#define DBLAC_DEFAULT \ |
||||
(DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2)) |
||||
|
||||
/*
|
||||
* descriptor structure |
||||
*/ |
||||
struct ftmac110_rxd { |
||||
uint32_t ct[2]; |
||||
uint32_t buf; |
||||
void *vbuf; /* reserved */ |
||||
}; |
||||
|
||||
#define FTMAC110_RXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ |
||||
#define FTMAC110_RXCT0_FRS BIT_MASK(29) /* first pkt desc */ |
||||
#define FTMAC110_RXCT0_LRS BIT_MASK(28) /* last pkt desc */ |
||||
#define FTMAC110_RXCT0_ODDNB BIT_MASK(22) /* odd nibble */ |
||||
#define FTMAC110_RXCT0_RUNT BIT_MASK(21) /* runt pkt */ |
||||
#define FTMAC110_RXCT0_FTL BIT_MASK(20) /* frame too long */ |
||||
#define FTMAC110_RXCT0_CRC BIT_MASK(19) /* pkt crc error */ |
||||
#define FTMAC110_RXCT0_ERR BIT_MASK(18) /* bus error */ |
||||
#define FTMAC110_RXCT0_ERRMASK (0x1f << 18) /* all errors */ |
||||
#define FTMAC110_RXCT0_BCST BIT_MASK(17) /* Bcst pkt */ |
||||
#define FTMAC110_RXCT0_MCST BIT_MASK(16) /* Mcst pkt */ |
||||
#define FTMAC110_RXCT0_LEN(x) ((x) & 0x7ff) |
||||
|
||||
#define FTMAC110_RXCT1_END BIT_MASK(31) |
||||
#define FTMAC110_RXCT1_BUFSZ(x) ((x) & 0x7ff) |
||||
|
||||
struct ftmac110_txd { |
||||
uint32_t ct[2]; |
||||
uint32_t buf; |
||||
void *vbuf; /* reserved */ |
||||
}; |
||||
|
||||
#define FTMAC110_TXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ |
||||
#define FTMAC110_TXCT0_COL 0x00000003 /* collision */ |
||||
|
||||
#define FTMAC110_TXCT1_END BIT_MASK(31) /* end of ring */ |
||||
#define FTMAC110_TXCT1_TXIC BIT_MASK(30) /* tx done interrupt */ |
||||
#define FTMAC110_TXCT1_TX2FIC BIT_MASK(29) /* tx fifo interrupt */ |
||||
#define FTMAC110_TXCT1_FTS BIT_MASK(28) /* first pkt desc */ |
||||
#define FTMAC110_TXCT1_LTS BIT_MASK(27) /* last pkt desc */ |
||||
#define FTMAC110_TXCT1_LEN(x) ((x) & 0x7ff) |
||||
|
||||
#endif /* FTMAC110_H */ |
||||
@ -0,0 +1,645 @@ |
||||
/*
|
||||
* Micrel KS8851_MLL 16bit Network driver |
||||
* Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <malloc.h> |
||||
#include <net.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "ks8851_mll.h" |
||||
|
||||
#define DRIVERNAME "ks8851_mll" |
||||
|
||||
#define MAX_RECV_FRAMES 32 |
||||
#define MAX_BUF_SIZE 2048 |
||||
#define TX_BUF_SIZE 2000 |
||||
#define RX_BUF_SIZE 2000 |
||||
|
||||
static const struct chip_id chip_ids[] = { |
||||
{CIDER_ID, "KSZ8851"}, |
||||
{0, NULL}, |
||||
}; |
||||
|
||||
/*
|
||||
* union ks_tx_hdr - tx header data |
||||
* @txb: The header as bytes |
||||
* @txw: The header as 16bit, little-endian words |
||||
* |
||||
* A dual representation of the tx header data to allow |
||||
* access to individual bytes, and to allow 16bit accesses |
||||
* with 16bit alignment. |
||||
*/ |
||||
union ks_tx_hdr { |
||||
u8 txb[4]; |
||||
__le16 txw[2]; |
||||
}; |
||||
|
||||
/*
|
||||
* struct ks_net - KS8851 driver private data |
||||
* @net_device : The network device we're bound to |
||||
* @txh : temporaly buffer to save status/length. |
||||
* @frame_head_info : frame header information for multi-pkt rx. |
||||
* @statelock : Lock on this structure for tx list. |
||||
* @msg_enable : The message flags controlling driver output (see ethtool). |
||||
* @frame_cnt : number of frames received. |
||||
* @bus_width : i/o bus width. |
||||
* @irq : irq number assigned to this device. |
||||
* @rc_rxqcr : Cached copy of KS_RXQCR. |
||||
* @rc_txcr : Cached copy of KS_TXCR. |
||||
* @rc_ier : Cached copy of KS_IER. |
||||
* @sharedbus : Multipex(addr and data bus) mode indicator. |
||||
* @cmd_reg_cache : command register cached. |
||||
* @cmd_reg_cache_int : command register cached. Used in the irq handler. |
||||
* @promiscuous : promiscuous mode indicator. |
||||
* @all_mcast : mutlicast indicator. |
||||
* @mcast_lst_size : size of multicast list. |
||||
* @mcast_lst : multicast list. |
||||
* @mcast_bits : multicast enabed. |
||||
* @mac_addr : MAC address assigned to this device. |
||||
* @fid : frame id. |
||||
* @extra_byte : number of extra byte prepended rx pkt. |
||||
* @enabled : indicator this device works. |
||||
*/ |
||||
|
||||
/* Receive multiplex framer header info */ |
||||
struct type_frame_head { |
||||
u16 sts; /* Frame status */ |
||||
u16 len; /* Byte count */ |
||||
} fr_h_i[MAX_RECV_FRAMES]; |
||||
|
||||
struct ks_net { |
||||
struct net_device *netdev; |
||||
union ks_tx_hdr txh; |
||||
struct type_frame_head *frame_head_info; |
||||
u32 msg_enable; |
||||
u32 frame_cnt; |
||||
int bus_width; |
||||
int irq; |
||||
u16 rc_rxqcr; |
||||
u16 rc_txcr; |
||||
u16 rc_ier; |
||||
u16 sharedbus; |
||||
u16 cmd_reg_cache; |
||||
u16 cmd_reg_cache_int; |
||||
u16 promiscuous; |
||||
u16 all_mcast; |
||||
u16 mcast_lst_size; |
||||
u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN]; |
||||
u8 mcast_bits[HW_MCAST_SIZE]; |
||||
u8 mac_addr[6]; |
||||
u8 fid; |
||||
u8 extra_byte; |
||||
u8 enabled; |
||||
} ks_str, *ks; |
||||
|
||||
#define BE3 0x8000 /* Byte Enable 3 */ |
||||
#define BE2 0x4000 /* Byte Enable 2 */ |
||||
#define BE1 0x2000 /* Byte Enable 1 */ |
||||
#define BE0 0x1000 /* Byte Enable 0 */ |
||||
|
||||
static u8 ks_rdreg8(struct eth_device *dev, u16 offset) |
||||
{ |
||||
u8 shift_bit = offset & 0x03; |
||||
u8 shift_data = (offset & 1) << 3; |
||||
|
||||
writew(offset | (BE0 << shift_bit), dev->iobase + 2); |
||||
|
||||
return (u8)(readw(dev->iobase) >> shift_data); |
||||
} |
||||
|
||||
static u16 ks_rdreg16(struct eth_device *dev, u16 offset) |
||||
{ |
||||
writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); |
||||
|
||||
return readw(dev->iobase); |
||||
} |
||||
|
||||
static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val) |
||||
{ |
||||
u8 shift_bit = (offset & 0x03); |
||||
u16 value_write = (u16)(val << ((offset & 1) << 3)); |
||||
|
||||
writew(offset | (BE0 << shift_bit), dev->iobase + 2); |
||||
writew(value_write, dev->iobase); |
||||
} |
||||
|
||||
static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val) |
||||
{ |
||||
writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); |
||||
writew(val, dev->iobase); |
||||
} |
||||
|
||||
/*
|
||||
* ks_inblk - read a block of data from QMU. This is called after sudo DMA mode |
||||
* enabled. |
||||
* @ks: The chip state |
||||
* @wptr: buffer address to save data |
||||
* @len: length in byte to read |
||||
*/ |
||||
static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len) |
||||
{ |
||||
len >>= 1; |
||||
|
||||
while (len--) |
||||
*wptr++ = readw(dev->iobase); |
||||
} |
||||
|
||||
/*
|
||||
* ks_outblk - write data to QMU. This is called after sudo DMA mode enabled. |
||||
* @ks: The chip information |
||||
* @wptr: buffer address |
||||
* @len: length in byte to write |
||||
*/ |
||||
static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len) |
||||
{ |
||||
len >>= 1; |
||||
|
||||
while (len--) |
||||
writew(*wptr++, dev->iobase); |
||||
} |
||||
|
||||
static void ks_enable_int(struct eth_device *dev) |
||||
{ |
||||
ks_wrreg16(dev, KS_IER, ks->rc_ier); |
||||
} |
||||
|
||||
static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode) |
||||
{ |
||||
unsigned pmecr; |
||||
|
||||
ks_rdreg16(dev, KS_GRR); |
||||
pmecr = ks_rdreg16(dev, KS_PMECR); |
||||
pmecr &= ~PMECR_PM_MASK; |
||||
pmecr |= pwrmode; |
||||
|
||||
ks_wrreg16(dev, KS_PMECR, pmecr); |
||||
} |
||||
|
||||
/*
|
||||
* ks_read_config - read chip configuration of bus width. |
||||
* @ks: The chip information |
||||
*/ |
||||
static void ks_read_config(struct eth_device *dev) |
||||
{ |
||||
u16 reg_data = 0; |
||||
|
||||
/* Regardless of bus width, 8 bit read should always work. */ |
||||
reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; |
||||
reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; |
||||
|
||||
/* addr/data bus are multiplexed */ |
||||
ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; |
||||
|
||||
/*
|
||||
* There are garbage data when reading data from QMU, |
||||
* depending on bus-width. |
||||
*/ |
||||
if (reg_data & CCR_8BIT) { |
||||
ks->bus_width = ENUM_BUS_8BIT; |
||||
ks->extra_byte = 1; |
||||
} else if (reg_data & CCR_16BIT) { |
||||
ks->bus_width = ENUM_BUS_16BIT; |
||||
ks->extra_byte = 2; |
||||
} else { |
||||
ks->bus_width = ENUM_BUS_32BIT; |
||||
ks->extra_byte = 4; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* ks_soft_reset - issue one of the soft reset to the device |
||||
* @ks: The device state. |
||||
* @op: The bit(s) to set in the GRR |
||||
* |
||||
* Issue the relevant soft-reset command to the device's GRR register |
||||
* specified by @op. |
||||
* |
||||
* Note, the delays are in there as a caution to ensure that the reset |
||||
* has time to take effect and then complete. Since the datasheet does |
||||
* not currently specify the exact sequence, we have chosen something |
||||
* that seems to work with our device. |
||||
*/ |
||||
static void ks_soft_reset(struct eth_device *dev, unsigned op) |
||||
{ |
||||
/* Disable interrupt first */ |
||||
ks_wrreg16(dev, KS_IER, 0x0000); |
||||
ks_wrreg16(dev, KS_GRR, op); |
||||
mdelay(10); /* wait a short time to effect reset */ |
||||
ks_wrreg16(dev, KS_GRR, 0); |
||||
mdelay(1); /* wait for condition to clear */ |
||||
} |
||||
|
||||
void ks_enable_qmu(struct eth_device *dev) |
||||
{ |
||||
u16 w; |
||||
|
||||
w = ks_rdreg16(dev, KS_TXCR); |
||||
|
||||
/* Enables QMU Transmit (TXCR). */ |
||||
ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE); |
||||
|
||||
/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */ |
||||
w = ks_rdreg16(dev, KS_RXQCR); |
||||
ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE); |
||||
|
||||
/* Enables QMU Receive (RXCR1). */ |
||||
w = ks_rdreg16(dev, KS_RXCR1); |
||||
ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE); |
||||
} |
||||
|
||||
static void ks_disable_qmu(struct eth_device *dev) |
||||
{ |
||||
u16 w; |
||||
|
||||
w = ks_rdreg16(dev, KS_TXCR); |
||||
|
||||
/* Disables QMU Transmit (TXCR). */ |
||||
w &= ~TXCR_TXE; |
||||
ks_wrreg16(dev, KS_TXCR, w); |
||||
|
||||
/* Disables QMU Receive (RXCR1). */ |
||||
w = ks_rdreg16(dev, KS_RXCR1); |
||||
w &= ~RXCR1_RXE; |
||||
ks_wrreg16(dev, KS_RXCR1, w); |
||||
} |
||||
|
||||
static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len) |
||||
{ |
||||
u32 r = ks->extra_byte & 0x1; |
||||
u32 w = ks->extra_byte - r; |
||||
|
||||
/* 1. set sudo DMA mode */ |
||||
ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); |
||||
|
||||
/*
|
||||
* 2. read prepend data |
||||
* |
||||
* read 4 + extra bytes and discard them. |
||||
* extra bytes for dummy, 2 for status, 2 for len |
||||
*/ |
||||
|
||||
if (r) |
||||
ks_rdreg8(dev, 0); |
||||
|
||||
ks_inblk(dev, buf, w + 2 + 2); |
||||
|
||||
/* 3. read pkt data */ |
||||
ks_inblk(dev, buf, ALIGN(len, 4)); |
||||
|
||||
/* 4. reset sudo DMA Mode */ |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); |
||||
} |
||||
|
||||
static void ks_rcv(struct eth_device *dev, uchar **pv_data) |
||||
{ |
||||
struct type_frame_head *frame_hdr = ks->frame_head_info; |
||||
int i; |
||||
|
||||
ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8; |
||||
|
||||
/* read all header information */ |
||||
for (i = 0; i < ks->frame_cnt; i++) { |
||||
/* Checking Received packet status */ |
||||
frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR); |
||||
/* Get packet len from hardware */ |
||||
frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR); |
||||
frame_hdr++; |
||||
} |
||||
|
||||
frame_hdr = ks->frame_head_info; |
||||
while (ks->frame_cnt--) { |
||||
if ((frame_hdr->sts & RXFSHR_RXFV) && |
||||
(frame_hdr->len < RX_BUF_SIZE) && |
||||
frame_hdr->len) { |
||||
/* read data block including CRC 4 bytes */ |
||||
ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len); |
||||
|
||||
/* NetRxPackets buffer size is ok (*pv_data pointer) */ |
||||
NetReceive(*pv_data, frame_hdr->len); |
||||
pv_data++; |
||||
} else { |
||||
ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF)); |
||||
printf(DRIVERNAME ": bad packet\n"); |
||||
} |
||||
frame_hdr++; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* ks_read_selftest - read the selftest memory info. |
||||
* @ks: The device state |
||||
* |
||||
* Read and check the TX/RX memory selftest information. |
||||
*/ |
||||
static int ks_read_selftest(struct eth_device *dev) |
||||
{ |
||||
u16 both_done = MBIR_TXMBF | MBIR_RXMBF; |
||||
u16 mbir; |
||||
int ret = 0; |
||||
|
||||
mbir = ks_rdreg16(dev, KS_MBIR); |
||||
|
||||
if ((mbir & both_done) != both_done) { |
||||
printf(DRIVERNAME ": Memory selftest not finished\n"); |
||||
return 0; |
||||
} |
||||
|
||||
if (mbir & MBIR_TXMBFA) { |
||||
printf(DRIVERNAME ": TX memory selftest fails\n"); |
||||
ret |= 1; |
||||
} |
||||
|
||||
if (mbir & MBIR_RXMBFA) { |
||||
printf(DRIVERNAME ": RX memory selftest fails\n"); |
||||
ret |= 2; |
||||
} |
||||
|
||||
debug(DRIVERNAME ": the selftest passes\n"); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void ks_setup(struct eth_device *dev) |
||||
{ |
||||
u16 w; |
||||
|
||||
/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */ |
||||
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); |
||||
|
||||
/* Setup Receive Frame Data Pointer Auto-Increment */ |
||||
ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); |
||||
|
||||
/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */ |
||||
ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK); |
||||
|
||||
/* Setup RxQ Command Control (RXQCR) */ |
||||
ks->rc_rxqcr = RXQCR_CMD_CNTL; |
||||
ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr); |
||||
|
||||
/*
|
||||
* set the force mode to half duplex, default is full duplex |
||||
* because if the auto-negotiation fails, most switch uses |
||||
* half-duplex. |
||||
*/ |
||||
w = ks_rdreg16(dev, KS_P1MBCR); |
||||
w &= ~P1MBCR_FORCE_FDX; |
||||
ks_wrreg16(dev, KS_P1MBCR, w); |
||||
|
||||
w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP; |
||||
ks_wrreg16(dev, KS_TXCR, w); |
||||
|
||||
w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC; |
||||
|
||||
/* Normal mode */ |
||||
w |= RXCR1_RXPAFMA; |
||||
|
||||
ks_wrreg16(dev, KS_RXCR1, w); |
||||
} |
||||
|
||||
static void ks_setup_int(struct eth_device *dev) |
||||
{ |
||||
ks->rc_ier = 0x00; |
||||
|
||||
/* Clear the interrupts status of the hardware. */ |
||||
ks_wrreg16(dev, KS_ISR, 0xffff); |
||||
|
||||
/* Enables the interrupts of the hardware. */ |
||||
ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI); |
||||
} |
||||
|
||||
static int ks8851_mll_detect_chip(struct eth_device *dev) |
||||
{ |
||||
unsigned short val, i; |
||||
|
||||
ks_read_config(dev); |
||||
|
||||
val = ks_rdreg16(dev, KS_CIDER); |
||||
|
||||
if (val == 0xffff) { |
||||
/* Special case -- no chip present */ |
||||
printf(DRIVERNAME ": is chip mounted ?\n"); |
||||
return -1; |
||||
} else if ((val & 0xfff0) != CIDER_ID) { |
||||
printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val); |
||||
return -1; |
||||
} |
||||
|
||||
debug("Read back KS8851 id 0x%x\n", val); |
||||
|
||||
/* only one entry in the table */ |
||||
val &= 0xfff0; |
||||
for (i = 0; chip_ids[i].id != 0; i++) { |
||||
if (chip_ids[i].id == val) |
||||
break; |
||||
} |
||||
if (!chip_ids[i].id) { |
||||
printf(DRIVERNAME ": Unknown chip ID %04x\n", val); |
||||
return -1; |
||||
} |
||||
|
||||
dev->priv = (void *)&chip_ids[i]; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void ks8851_mll_reset(struct eth_device *dev) |
||||
{ |
||||
/* wake up powermode to normal mode */ |
||||
ks_set_powermode(dev, PMECR_PM_NORMAL); |
||||
mdelay(1); /* wait for normal mode to take effect */ |
||||
|
||||
/* Disable interrupt and reset */ |
||||
ks_soft_reset(dev, GRR_GSR); |
||||
|
||||
/* turn off the IRQs and ack any outstanding */ |
||||
ks_wrreg16(dev, KS_IER, 0x0000); |
||||
ks_wrreg16(dev, KS_ISR, 0xffff); |
||||
|
||||
/* shutdown RX/TX QMU */ |
||||
ks_disable_qmu(dev); |
||||
} |
||||
|
||||
static void ks8851_mll_phy_configure(struct eth_device *dev) |
||||
{ |
||||
u16 data; |
||||
|
||||
ks_setup(dev); |
||||
ks_setup_int(dev); |
||||
|
||||
/* Probing the phy */ |
||||
data = ks_rdreg16(dev, KS_OBCR); |
||||
ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA); |
||||
|
||||
debug(DRIVERNAME ": phy initialized\n"); |
||||
} |
||||
|
||||
static void ks8851_mll_enable(struct eth_device *dev) |
||||
{ |
||||
ks_wrreg16(dev, KS_ISR, 0xffff); |
||||
ks_enable_int(dev); |
||||
ks_enable_qmu(dev); |
||||
} |
||||
|
||||
static int ks8851_mll_init(struct eth_device *dev, bd_t *bd) |
||||
{ |
||||
struct chip_id *id = dev->priv; |
||||
|
||||
debug(DRIVERNAME ": detected %s controller\n", id->name); |
||||
|
||||
if (ks_read_selftest(dev)) { |
||||
printf(DRIVERNAME ": Selftest failed\n"); |
||||
return -1; |
||||
} |
||||
|
||||
ks8851_mll_reset(dev); |
||||
|
||||
/* Configure the PHY, initialize the link state */ |
||||
ks8851_mll_phy_configure(dev); |
||||
|
||||
/* static allocation of private informations */ |
||||
ks->frame_head_info = fr_h_i; |
||||
|
||||
/* Turn on Tx + Rx */ |
||||
ks8851_mll_enable(dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len) |
||||
{ |
||||
/* start header at txb[0] to align txw entries */ |
||||
ks->txh.txw[0] = 0; |
||||
ks->txh.txw[1] = cpu_to_le16(len); |
||||
|
||||
/* 1. set sudo-DMA mode */ |
||||
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); |
||||
/* 2. write status/lenth info */ |
||||
ks_outblk(dev, ks->txh.txw, 4); |
||||
/* 3. write pkt data */ |
||||
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4)); |
||||
/* 4. reset sudo-DMA mode */ |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); |
||||
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */ |
||||
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE); |
||||
/* 6. wait until TXQCR_METFE is auto-cleared */ |
||||
do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE); |
||||
} |
||||
|
||||
static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) |
||||
{ |
||||
u8 *data = (u8 *)packet; |
||||
u16 tmplen = (u16)length; |
||||
u16 retv; |
||||
|
||||
/*
|
||||
* Extra space are required: |
||||
* 4 byte for alignment, 4 for status/length, 4 for CRC |
||||
*/ |
||||
retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff; |
||||
if (retv >= tmplen + 12) { |
||||
ks_write_qmu(dev, data, tmplen); |
||||
return 0; |
||||
} else { |
||||
printf(DRIVERNAME ": failed to send packet: No buffer\n"); |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
static void ks8851_mll_halt(struct eth_device *dev) |
||||
{ |
||||
ks8851_mll_reset(dev); |
||||
} |
||||
|
||||
/*
|
||||
* Maximum receive ring size; that is, the number of packets |
||||
* we can buffer before overflow happens. Basically, this just |
||||
* needs to be enough to prevent a packet being discarded while |
||||
* we are processing the previous one. |
||||
*/ |
||||
static int ks8851_mll_recv(struct eth_device *dev) |
||||
{ |
||||
u16 status; |
||||
|
||||
status = ks_rdreg16(dev, KS_ISR); |
||||
|
||||
ks_wrreg16(dev, KS_ISR, status); |
||||
|
||||
if ((status & IRQ_RXI)) |
||||
ks_rcv(dev, (uchar **)NetRxPackets); |
||||
|
||||
if ((status & IRQ_LDI)) { |
||||
u16 pmecr = ks_rdreg16(dev, KS_PMECR); |
||||
pmecr &= ~PMECR_WKEVT_MASK; |
||||
ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ks8851_mll_write_hwaddr(struct eth_device *dev) |
||||
{ |
||||
u16 addrl, addrm, addrh; |
||||
|
||||
addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1]; |
||||
addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3]; |
||||
addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5]; |
||||
|
||||
ks_wrreg16(dev, KS_MARH, addrh); |
||||
ks_wrreg16(dev, KS_MARM, addrm); |
||||
ks_wrreg16(dev, KS_MARL, addrl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ks8851_mll_initialize(u8 dev_num, int base_addr) |
||||
{ |
||||
struct eth_device *dev; |
||||
|
||||
dev = malloc(sizeof(*dev)); |
||||
if (!dev) { |
||||
printf("Error: Failed to allocate memory\n"); |
||||
return -1; |
||||
} |
||||
memset(dev, 0, sizeof(*dev)); |
||||
|
||||
dev->iobase = base_addr; |
||||
|
||||
ks = &ks_str; |
||||
|
||||
/* Try to detect chip. Will fail if not present. */ |
||||
if (ks8851_mll_detect_chip(dev)) { |
||||
free(dev); |
||||
return -1; |
||||
} |
||||
|
||||
dev->init = ks8851_mll_init; |
||||
dev->halt = ks8851_mll_halt; |
||||
dev->send = ks8851_mll_send; |
||||
dev->recv = ks8851_mll_recv; |
||||
dev->write_hwaddr = ks8851_mll_write_hwaddr; |
||||
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); |
||||
|
||||
eth_register(dev); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,357 @@ |
||||
/*
|
||||
* drivers/net/ks8851_mll.c |
||||
* |
||||
* Supports: |
||||
* KS8851 16bit MLL chip from Micrel Inc. |
||||
* |
||||
* Copyright (c) 2009 Micrel Inc. |
||||
* |
||||
* modified by |
||||
* (c) 2011 Bticino s.p.a, Roberto Cerati <roberto.cerati@bticino.it> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
#ifndef _KS8851_MLL_H_ |
||||
#define _KS8851_MLL_H_ |
||||
|
||||
#include <linux/types.h> |
||||
|
||||
#define KS_CCR 0x08 |
||||
#define CCR_EEPROM (1 << 9) |
||||
#define CCR_SPI (1 << 8) |
||||
#define CCR_8BIT (1 << 7) |
||||
#define CCR_16BIT (1 << 6) |
||||
#define CCR_32BIT (1 << 5) |
||||
#define CCR_SHARED (1 << 4) |
||||
#define CCR_32PIN (1 << 0) |
||||
|
||||
/* MAC address registers */ |
||||
#define KS_MARL 0x10 |
||||
#define KS_MARM 0x12 |
||||
#define KS_MARH 0x14 |
||||
|
||||
#define KS_OBCR 0x20 |
||||
#define OBCR_ODS_16MA (1 << 6) |
||||
|
||||
#define KS_EEPCR 0x22 |
||||
#define EEPCR_EESA (1 << 4) |
||||
#define EEPCR_EESB (1 << 3) |
||||
#define EEPCR_EEDO (1 << 2) |
||||
#define EEPCR_EESCK (1 << 1) |
||||
#define EEPCR_EECS (1 << 0) |
||||
|
||||
#define KS_MBIR 0x24 |
||||
#define MBIR_TXMBF (1 << 12) |
||||
#define MBIR_TXMBFA (1 << 11) |
||||
#define MBIR_RXMBF (1 << 4) |
||||
#define MBIR_RXMBFA (1 << 3) |
||||
|
||||
#define KS_GRR 0x26 |
||||
#define GRR_QMU (1 << 1) |
||||
#define GRR_GSR (1 << 0) |
||||
|
||||
#define KS_WFCR 0x2A |
||||
#define WFCR_MPRXE (1 << 7) |
||||
#define WFCR_WF3E (1 << 3) |
||||
#define WFCR_WF2E (1 << 2) |
||||
#define WFCR_WF1E (1 << 1) |
||||
#define WFCR_WF0E (1 << 0) |
||||
|
||||
#define KS_WF0CRC0 0x30 |
||||
#define KS_WF0CRC1 0x32 |
||||
#define KS_WF0BM0 0x34 |
||||
#define KS_WF0BM1 0x36 |
||||
#define KS_WF0BM2 0x38 |
||||
#define KS_WF0BM3 0x3A |
||||
|
||||
#define KS_WF1CRC0 0x40 |
||||
#define KS_WF1CRC1 0x42 |
||||
#define KS_WF1BM0 0x44 |
||||
#define KS_WF1BM1 0x46 |
||||
#define KS_WF1BM2 0x48 |
||||
#define KS_WF1BM3 0x4A |
||||
|
||||
#define KS_WF2CRC0 0x50 |
||||
#define KS_WF2CRC1 0x52 |
||||
#define KS_WF2BM0 0x54 |
||||
#define KS_WF2BM1 0x56 |
||||
#define KS_WF2BM2 0x58 |
||||
#define KS_WF2BM3 0x5A |
||||
|
||||
#define KS_WF3CRC0 0x60 |
||||
#define KS_WF3CRC1 0x62 |
||||
#define KS_WF3BM0 0x64 |
||||
#define KS_WF3BM1 0x66 |
||||
#define KS_WF3BM2 0x68 |
||||
#define KS_WF3BM3 0x6A |
||||
|
||||
#define KS_TXCR 0x70 |
||||
#define TXCR_TCGICMP (1 << 8) |
||||
#define TXCR_TCGUDP (1 << 7) |
||||
#define TXCR_TCGTCP (1 << 6) |
||||
#define TXCR_TCGIP (1 << 5) |
||||
#define TXCR_FTXQ (1 << 4) |
||||
#define TXCR_TXFCE (1 << 3) |
||||
#define TXCR_TXPE (1 << 2) |
||||
#define TXCR_TXCRC (1 << 1) |
||||
#define TXCR_TXE (1 << 0) |
||||
|
||||
#define KS_TXSR 0x72 |
||||
#define TXSR_TXLC (1 << 13) |
||||
#define TXSR_TXMC (1 << 12) |
||||
#define TXSR_TXFID_MASK (0x3f << 0) |
||||
#define TXSR_TXFID_SHIFT (0) |
||||
#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) |
||||
|
||||
|
||||
#define KS_RXCR1 0x74 |
||||
#define RXCR1_FRXQ (1 << 15) |
||||
#define RXCR1_RXUDPFCC (1 << 14) |
||||
#define RXCR1_RXTCPFCC (1 << 13) |
||||
#define RXCR1_RXIPFCC (1 << 12) |
||||
#define RXCR1_RXPAFMA (1 << 11) |
||||
#define RXCR1_RXFCE (1 << 10) |
||||
#define RXCR1_RXEFE (1 << 9) |
||||
#define RXCR1_RXMAFMA (1 << 8) |
||||
#define RXCR1_RXBE (1 << 7) |
||||
#define RXCR1_RXME (1 << 6) |
||||
#define RXCR1_RXUE (1 << 5) |
||||
#define RXCR1_RXAE (1 << 4) |
||||
#define RXCR1_RXINVF (1 << 1) |
||||
#define RXCR1_RXE (1 << 0) |
||||
#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ |
||||
RXCR1_RXMAFMA | RXCR1_RXPAFMA) |
||||
|
||||
#define KS_RXCR2 0x76 |
||||
#define RXCR2_SRDBL_MASK (0x7 << 5) |
||||
#define RXCR2_SRDBL_SHIFT (5) |
||||
#define RXCR2_SRDBL_4B (0x0 << 5) |
||||
#define RXCR2_SRDBL_8B (0x1 << 5) |
||||
#define RXCR2_SRDBL_16B (0x2 << 5) |
||||
#define RXCR2_SRDBL_32B (0x3 << 5) |
||||
/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ |
||||
#define RXCR2_IUFFP (1 << 4) |
||||
#define RXCR2_RXIUFCEZ (1 << 3) |
||||
#define RXCR2_UDPLFE (1 << 2) |
||||
#define RXCR2_RXICMPFCC (1 << 1) |
||||
#define RXCR2_RXSAF (1 << 0) |
||||
|
||||
#define KS_TXMIR 0x78 |
||||
|
||||
#define KS_RXFHSR 0x7C |
||||
#define RXFSHR_RXFV (1 << 15) |
||||
#define RXFSHR_RXICMPFCS (1 << 13) |
||||
#define RXFSHR_RXIPFCS (1 << 12) |
||||
#define RXFSHR_RXTCPFCS (1 << 11) |
||||
#define RXFSHR_RXUDPFCS (1 << 10) |
||||
#define RXFSHR_RXBF (1 << 7) |
||||
#define RXFSHR_RXMF (1 << 6) |
||||
#define RXFSHR_RXUF (1 << 5) |
||||
#define RXFSHR_RXMR (1 << 4) |
||||
#define RXFSHR_RXFT (1 << 3) |
||||
#define RXFSHR_RXFTL (1 << 2) |
||||
#define RXFSHR_RXRF (1 << 1) |
||||
#define RXFSHR_RXCE (1 << 0) |
||||
#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ |
||||
RXFSHR_RXFTL | RXFSHR_RXMR |\
|
||||
RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
|
||||
RXFSHR_RXTCPFCS) |
||||
#define KS_RXFHBCR 0x7E |
||||
#define RXFHBCR_CNT_MASK 0x0FFF |
||||
|
||||
#define KS_TXQCR 0x80 |
||||
#define TXQCR_AETFE (1 << 2) |
||||
#define TXQCR_TXQMAM (1 << 1) |
||||
#define TXQCR_METFE (1 << 0) |
||||
|
||||
#define KS_RXQCR 0x82 |
||||
#define RXQCR_RXDTTS (1 << 12) |
||||
#define RXQCR_RXDBCTS (1 << 11) |
||||
#define RXQCR_RXFCTS (1 << 10) |
||||
#define RXQCR_RXIPHTOE (1 << 9) |
||||
#define RXQCR_RXDTTE (1 << 7) |
||||
#define RXQCR_RXDBCTE (1 << 6) |
||||
#define RXQCR_RXFCTE (1 << 5) |
||||
#define RXQCR_ADRFE (1 << 4) |
||||
#define RXQCR_SDA (1 << 3) |
||||
#define RXQCR_RRXEF (1 << 0) |
||||
#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) |
||||
|
||||
#define KS_TXFDPR 0x84 |
||||
#define TXFDPR_TXFPAI (1 << 14) |
||||
#define TXFDPR_TXFP_MASK (0x7ff << 0) |
||||
#define TXFDPR_TXFP_SHIFT (0) |
||||
|
||||
#define KS_RXFDPR 0x86 |
||||
#define RXFDPR_RXFPAI (1 << 14) |
||||
|
||||
#define KS_RXDTTR 0x8C |
||||
#define KS_RXDBCTR 0x8E |
||||
|
||||
#define KS_IER 0x90 |
||||
#define KS_ISR 0x92 |
||||
#define IRQ_LCI (1 << 15) |
||||
#define IRQ_TXI (1 << 14) |
||||
#define IRQ_RXI (1 << 13) |
||||
#define IRQ_RXOI (1 << 11) |
||||
#define IRQ_TXPSI (1 << 9) |
||||
#define IRQ_RXPSI (1 << 8) |
||||
#define IRQ_TXSAI (1 << 6) |
||||
#define IRQ_RXWFDI (1 << 5) |
||||
#define IRQ_RXMPDI (1 << 4) |
||||
#define IRQ_LDI (1 << 3) |
||||
#define IRQ_EDI (1 << 2) |
||||
#define IRQ_SPIBEI (1 << 1) |
||||
#define IRQ_DEDI (1 << 0) |
||||
|
||||
#define KS_RXFCTR 0x9C |
||||
#define RXFCTR_THRESHOLD_MASK 0x00FF |
||||
|
||||
#define KS_RXFC 0x9D |
||||
#define RXFCTR_RXFC_MASK (0xff << 8) |
||||
#define RXFCTR_RXFC_SHIFT (8) |
||||
#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff) |
||||
#define RXFCTR_RXFCT_MASK (0xff << 0) |
||||
#define RXFCTR_RXFCT_SHIFT (0) |
||||
|
||||
#define KS_TXNTFSR 0x9E |
||||
|
||||
#define KS_MAHTR0 0xA0 |
||||
#define KS_MAHTR1 0xA2 |
||||
#define KS_MAHTR2 0xA4 |
||||
#define KS_MAHTR3 0xA6 |
||||
|
||||
#define KS_FCLWR 0xB0 |
||||
#define KS_FCHWR 0xB2 |
||||
#define KS_FCOWR 0xB4 |
||||
|
||||
#define KS_CIDER 0xC0 |
||||
#define CIDER_ID 0x8870 |
||||
#define CIDER_REV_MASK (0x7 << 1) |
||||
#define CIDER_REV_SHIFT (1) |
||||
#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7) |
||||
|
||||
#define KS_CGCR 0xC6 |
||||
#define KS_IACR 0xC8 |
||||
#define IACR_RDEN (1 << 12) |
||||
#define IACR_TSEL_MASK (0x3 << 10) |
||||
#define IACR_TSEL_SHIFT (10) |
||||
#define IACR_TSEL_MIB (0x3 << 10) |
||||
#define IACR_ADDR_MASK (0x1f << 0) |
||||
#define IACR_ADDR_SHIFT (0) |
||||
|
||||
#define KS_IADLR 0xD0 |
||||
#define KS_IAHDR 0xD2 |
||||
|
||||
#define KS_PMECR 0xD4 |
||||
#define PMECR_PME_DELAY (1 << 14) |
||||
#define PMECR_PME_POL (1 << 12) |
||||
#define PMECR_WOL_WAKEUP (1 << 11) |
||||
#define PMECR_WOL_MAGICPKT (1 << 10) |
||||
#define PMECR_WOL_LINKUP (1 << 9) |
||||
#define PMECR_WOL_ENERGY (1 << 8) |
||||
#define PMECR_AUTO_WAKE_EN (1 << 7) |
||||
#define PMECR_WAKEUP_NORMAL (1 << 6) |
||||
#define PMECR_WKEVT_MASK (0xf << 2) |
||||
#define PMECR_WKEVT_SHIFT (2) |
||||
#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) |
||||
#define PMECR_WKEVT_ENERGY (0x1 << 2) |
||||
#define PMECR_WKEVT_LINK (0x2 << 2) |
||||
#define PMECR_WKEVT_MAGICPKT (0x4 << 2) |
||||
#define PMECR_WKEVT_FRAME (0x8 << 2) |
||||
#define PMECR_PM_MASK (0x3 << 0) |
||||
#define PMECR_PM_SHIFT (0) |
||||
#define PMECR_PM_NORMAL (0x0 << 0) |
||||
#define PMECR_PM_ENERGY (0x1 << 0) |
||||
#define PMECR_PM_SOFTDOWN (0x2 << 0) |
||||
#define PMECR_PM_POWERSAVE (0x3 << 0) |
||||
|
||||
/* Standard MII PHY data */ |
||||
#define KS_P1MBCR 0xE4 |
||||
#define P1MBCR_FORCE_FDX (1 << 8) |
||||
|
||||
#define KS_P1MBSR 0xE6 |
||||
#define P1MBSR_AN_COMPLETE (1 << 5) |
||||
#define P1MBSR_AN_CAPABLE (1 << 3) |
||||
#define P1MBSR_LINK_UP (1 << 2) |
||||
|
||||
#define KS_PHY1ILR 0xE8 |
||||
#define KS_PHY1IHR 0xEA |
||||
#define KS_P1ANAR 0xEC |
||||
#define KS_P1ANLPR 0xEE |
||||
|
||||
#define KS_P1SCLMD 0xF4 |
||||
#define P1SCLMD_LEDOFF (1 << 15) |
||||
#define P1SCLMD_TXIDS (1 << 14) |
||||
#define P1SCLMD_RESTARTAN (1 << 13) |
||||
#define P1SCLMD_DISAUTOMDIX (1 << 10) |
||||
#define P1SCLMD_FORCEMDIX (1 << 9) |
||||
#define P1SCLMD_AUTONEGEN (1 << 7) |
||||
#define P1SCLMD_FORCE100 (1 << 6) |
||||
#define P1SCLMD_FORCEFDX (1 << 5) |
||||
#define P1SCLMD_ADV_FLOW (1 << 4) |
||||
#define P1SCLMD_ADV_100BT_FDX (1 << 3) |
||||
#define P1SCLMD_ADV_100BT_HDX (1 << 2) |
||||
#define P1SCLMD_ADV_10BT_FDX (1 << 1) |
||||
#define P1SCLMD_ADV_10BT_HDX (1 << 0) |
||||
|
||||
#define KS_P1CR 0xF6 |
||||
#define P1CR_HP_MDIX (1 << 15) |
||||
#define P1CR_REV_POL (1 << 13) |
||||
#define P1CR_OP_100M (1 << 10) |
||||
#define P1CR_OP_FDX (1 << 9) |
||||
#define P1CR_OP_MDI (1 << 7) |
||||
#define P1CR_AN_DONE (1 << 6) |
||||
#define P1CR_LINK_GOOD (1 << 5) |
||||
#define P1CR_PNTR_FLOW (1 << 4) |
||||
#define P1CR_PNTR_100BT_FDX (1 << 3) |
||||
#define P1CR_PNTR_100BT_HDX (1 << 2) |
||||
#define P1CR_PNTR_10BT_FDX (1 << 1) |
||||
#define P1CR_PNTR_10BT_HDX (1 << 0) |
||||
|
||||
/* TX Frame control */ |
||||
#define TXFR_TXIC (1 << 15) |
||||
#define TXFR_TXFID_MASK (0x3f << 0) |
||||
#define TXFR_TXFID_SHIFT (0) |
||||
|
||||
#define KS_P1SR 0xF8 |
||||
#define P1SR_HP_MDIX (1 << 15) |
||||
#define P1SR_REV_POL (1 << 13) |
||||
#define P1SR_OP_100M (1 << 10) |
||||
#define P1SR_OP_FDX (1 << 9) |
||||
#define P1SR_OP_MDI (1 << 7) |
||||
#define P1SR_AN_DONE (1 << 6) |
||||
#define P1SR_LINK_GOOD (1 << 5) |
||||
#define P1SR_PNTR_FLOW (1 << 4) |
||||
#define P1SR_PNTR_100BT_FDX (1 << 3) |
||||
#define P1SR_PNTR_100BT_HDX (1 << 2) |
||||
#define P1SR_PNTR_10BT_FDX (1 << 1) |
||||
#define P1SR_PNTR_10BT_HDX (1 << 0) |
||||
|
||||
#define ENUM_BUS_NONE 0 |
||||
#define ENUM_BUS_8BIT 1 |
||||
#define ENUM_BUS_16BIT 2 |
||||
#define ENUM_BUS_32BIT 3 |
||||
|
||||
#define MAX_MCAST_LST 32 |
||||
#define HW_MCAST_SIZE 8 |
||||
#define MAC_ADDR_LEN 6 |
||||
|
||||
/* Chip ID values */ |
||||
struct chip_id { |
||||
u16 id; |
||||
char *name; |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,94 @@ |
||||
/*
|
||||
* ICPlus PHY drivers |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc. |
||||
* |
||||
*/ |
||||
#include <phy.h> |
||||
|
||||
/* IP101A/G - IP1001 */ |
||||
#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ |
||||
#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ |
||||
#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ |
||||
#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ |
||||
#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ |
||||
#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ |
||||
#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ |
||||
#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED |
||||
|
||||
static int ip1001_config(struct phy_device *phydev) |
||||
{ |
||||
int c; |
||||
|
||||
/* Enable Auto Power Saving mode */ |
||||
c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2); |
||||
if (c < 0) |
||||
return c; |
||||
c |= IP1001_APS_ON; |
||||
c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c); |
||||
if (c < 0) |
||||
return c; |
||||
|
||||
/* INTR pin used: speed/link/duplex will cause an interrupt */ |
||||
c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS, |
||||
IP101A_G_IRQ_DEFAULT); |
||||
if (c < 0) |
||||
return c; |
||||
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { |
||||
/*
|
||||
* Additional delay (2ns) used to adjust RX clock phase |
||||
* at RGMII interface |
||||
*/ |
||||
c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS); |
||||
if (c < 0) |
||||
return c; |
||||
|
||||
c |= IP1001_PHASE_SEL_MASK; |
||||
c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS, |
||||
c); |
||||
if (c < 0) |
||||
return c; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ip1001_startup(struct phy_device *phydev) |
||||
{ |
||||
genphy_update_link(phydev); |
||||
genphy_parse_link(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
static struct phy_driver IP1001_driver = { |
||||
.name = "ICPlus IP1001", |
||||
.uid = 0x02430d90, |
||||
.mask = 0x0ffffff0, |
||||
.features = PHY_GBIT_FEATURES, |
||||
.config = &ip1001_config, |
||||
.startup = &ip1001_startup, |
||||
.shutdown = &genphy_shutdown, |
||||
}; |
||||
|
||||
int phy_icplus_init(void) |
||||
{ |
||||
phy_register(&IP1001_driver); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,533 @@ |
||||
/*
|
||||
* sunxi_wemac.c -- Allwinner A10 ethernet driver |
||||
* |
||||
* (C) Copyright 2012, Stefan Roese <sr@denx.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <net.h> |
||||
#include <miiphy.h> |
||||
#include <linux/err.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/gpio.h> |
||||
|
||||
/* EMAC register */ |
||||
struct wemac_regs { |
||||
u32 ctl; /* 0x00 */ |
||||
u32 tx_mode; /* 0x04 */ |
||||
u32 tx_flow; /* 0x08 */ |
||||
u32 tx_ctl0; /* 0x0c */ |
||||
u32 tx_ctl1; /* 0x10 */ |
||||
u32 tx_ins; /* 0x14 */ |
||||
u32 tx_pl0; /* 0x18 */ |
||||
u32 tx_pl1; /* 0x1c */ |
||||
u32 tx_sta; /* 0x20 */ |
||||
u32 tx_io_data; /* 0x24 */ |
||||
u32 tx_io_data1; /* 0x28 */ |
||||
u32 tx_tsvl0; /* 0x2c */ |
||||
u32 tx_tsvh0; /* 0x30 */ |
||||
u32 tx_tsvl1; /* 0x34 */ |
||||
u32 tx_tsvh1; /* 0x38 */ |
||||
u32 rx_ctl; /* 0x3c */ |
||||
u32 rx_hash0; /* 0x40 */ |
||||
u32 rx_hash1; /* 0x44 */ |
||||
u32 rx_sta; /* 0x48 */ |
||||
u32 rx_io_data; /* 0x4c */ |
||||
u32 rx_fbc; /* 0x50 */ |
||||
u32 int_ctl; /* 0x54 */ |
||||
u32 int_sta; /* 0x58 */ |
||||
u32 mac_ctl0; /* 0x5c */ |
||||
u32 mac_ctl1; /* 0x60 */ |
||||
u32 mac_ipgt; /* 0x64 */ |
||||
u32 mac_ipgr; /* 0x68 */ |
||||
u32 mac_clrt; /* 0x6c */ |
||||
u32 mac_maxf; /* 0x70 */ |
||||
u32 mac_supp; /* 0x74 */ |
||||
u32 mac_test; /* 0x78 */ |
||||
u32 mac_mcfg; /* 0x7c */ |
||||
u32 mac_mcmd; /* 0x80 */ |
||||
u32 mac_madr; /* 0x84 */ |
||||
u32 mac_mwtd; /* 0x88 */ |
||||
u32 mac_mrdd; /* 0x8c */ |
||||
u32 mac_mind; /* 0x90 */ |
||||
u32 mac_ssrr; /* 0x94 */ |
||||
u32 mac_a0; /* 0x98 */ |
||||
u32 mac_a1; /* 0x9c */ |
||||
}; |
||||
|
||||
/* SRAMC register */ |
||||
struct sunxi_sramc_regs { |
||||
u32 ctrl0; |
||||
u32 ctrl1; |
||||
}; |
||||
|
||||
/* 0: Disable 1: Aborted frame enable(default) */ |
||||
#define EMAC_TX_AB_M (0x1 << 0) |
||||
/* 0: CPU 1: DMA(default) */ |
||||
#define EMAC_TX_TM (0x1 << 1) |
||||
|
||||
#define EMAC_TX_SETUP (0) |
||||
|
||||
/* 0: DRQ asserted 1: DRQ automatically(default) */ |
||||
#define EMAC_RX_DRQ_MODE (0x1 << 1) |
||||
/* 0: CPU 1: DMA(default) */ |
||||
#define EMAC_RX_TM (0x1 << 2) |
||||
/* 0: Normal(default) 1: Pass all Frames */ |
||||
#define EMAC_RX_PA (0x1 << 4) |
||||
/* 0: Normal(default) 1: Pass Control Frames */ |
||||
#define EMAC_RX_PCF (0x1 << 5) |
||||
/* 0: Normal(default) 1: Pass Frames with CRC Error */ |
||||
#define EMAC_RX_PCRCE (0x1 << 6) |
||||
/* 0: Normal(default) 1: Pass Frames with Length Error */ |
||||
#define EMAC_RX_PLE (0x1 << 7) |
||||
/* 0: Normal 1: Pass Frames length out of range(default) */ |
||||
#define EMAC_RX_POR (0x1 << 8) |
||||
/* 0: Not accept 1: Accept unicast Packets(default) */ |
||||
#define EMAC_RX_UCAD (0x1 << 16) |
||||
/* 0: Normal(default) 1: DA Filtering */ |
||||
#define EMAC_RX_DAF (0x1 << 17) |
||||
/* 0: Not accept 1: Accept multicast Packets(default) */ |
||||
#define EMAC_RX_MCO (0x1 << 20) |
||||
/* 0: Disable(default) 1: Enable Hash filter */ |
||||
#define EMAC_RX_MHF (0x1 << 21) |
||||
/* 0: Not accept 1: Accept Broadcast Packets(default) */ |
||||
#define EMAC_RX_BCO (0x1 << 22) |
||||
/* 0: Disable(default) 1: Enable SA Filtering */ |
||||
#define EMAC_RX_SAF (0x1 << 24) |
||||
/* 0: Normal(default) 1: Inverse Filtering */ |
||||
#define EMAC_RX_SAIF (0x1 << 25) |
||||
|
||||
#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ |
||||
EMAC_RX_MCO | EMAC_RX_BCO) |
||||
|
||||
/* 0: Disable 1: Enable Receive Flow Control(default) */ |
||||
#define EMAC_MAC_CTL0_RFC (0x1 << 2) |
||||
/* 0: Disable 1: Enable Transmit Flow Control(default) */ |
||||
#define EMAC_MAC_CTL0_TFC (0x1 << 3) |
||||
|
||||
#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) |
||||
|
||||
/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ |
||||
#define EMAC_MAC_CTL1_FLC (0x1 << 1) |
||||
/* 0: Disable(default) 1: Enable Huge Frame */ |
||||
#define EMAC_MAC_CTL1_HF (0x1 << 2) |
||||
/* 0: Disable(default) 1: Enable MAC Delayed CRC */ |
||||
#define EMAC_MAC_CTL1_DCRC (0x1 << 3) |
||||
/* 0: Disable 1: Enable MAC CRC(default) */ |
||||
#define EMAC_MAC_CTL1_CRC (0x1 << 4) |
||||
/* 0: Disable 1: Enable MAC PAD Short frames(default) */ |
||||
#define EMAC_MAC_CTL1_PC (0x1 << 5) |
||||
/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ |
||||
#define EMAC_MAC_CTL1_VC (0x1 << 6) |
||||
/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ |
||||
#define EMAC_MAC_CTL1_ADP (0x1 << 7) |
||||
/* 0: Disable(default) 1: Enable */ |
||||
#define EMAC_MAC_CTL1_PRE (0x1 << 8) |
||||
/* 0: Disable(default) 1: Enable */ |
||||
#define EMAC_MAC_CTL1_LPE (0x1 << 9) |
||||
/* 0: Disable(default) 1: Enable no back off */ |
||||
#define EMAC_MAC_CTL1_NB (0x1 << 12) |
||||
/* 0: Disable(default) 1: Enable */ |
||||
#define EMAC_MAC_CTL1_BNB (0x1 << 13) |
||||
/* 0: Disable(default) 1: Enable */ |
||||
#define EMAC_MAC_CTL1_ED (0x1 << 14) |
||||
|
||||
#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ |
||||
EMAC_MAC_CTL1_PC) |
||||
|
||||
#define EMAC_MAC_IPGT 0x15 |
||||
|
||||
#define EMAC_MAC_NBTB_IPG1 0xC |
||||
#define EMAC_MAC_NBTB_IPG2 0x12 |
||||
|
||||
#define EMAC_MAC_CW 0x37 |
||||
#define EMAC_MAC_RM 0xF |
||||
|
||||
#define EMAC_MAC_MFL 0x0600 |
||||
|
||||
/* Receive status */ |
||||
#define EMAC_CRCERR (1 << 4) |
||||
#define EMAC_LENERR (3 << 5) |
||||
|
||||
#define DMA_CPU_TRRESHOLD 2000 |
||||
|
||||
struct wemac_eth_dev { |
||||
u32 speed; |
||||
u32 duplex; |
||||
u32 phy_configured; |
||||
int link_printed; |
||||
}; |
||||
|
||||
struct wemac_rxhdr { |
||||
s16 rx_len; |
||||
u16 rx_status; |
||||
}; |
||||
|
||||
static void wemac_inblk_32bit(void *reg, void *data, int count) |
||||
{ |
||||
int cnt = (count + 3) >> 2; |
||||
|
||||
if (cnt) { |
||||
u32 *buf = data; |
||||
|
||||
do { |
||||
u32 x = readl(reg); |
||||
*buf++ = x; |
||||
} while (--cnt); |
||||
} |
||||
} |
||||
|
||||
static void wemac_outblk_32bit(void *reg, void *data, int count) |
||||
{ |
||||
int cnt = (count + 3) >> 2; |
||||
|
||||
if (cnt) { |
||||
const u32 *buf = data; |
||||
|
||||
do { |
||||
writel(*buf++, reg); |
||||
} while (--cnt); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Read a word from phyxcer |
||||
*/ |
||||
static int wemac_phy_read(const char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short *value) |
||||
{ |
||||
struct eth_device *dev = eth_get_dev_by_name(devname); |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
|
||||
/* issue the phy address and reg */ |
||||
writel(addr << 8 | reg, ®s->mac_madr); |
||||
|
||||
/* pull up the phy io line */ |
||||
writel(0x1, ®s->mac_mcmd); |
||||
|
||||
/* Wait read complete */ |
||||
mdelay(1); |
||||
|
||||
/* push down the phy io line */ |
||||
writel(0x0, ®s->mac_mcmd); |
||||
|
||||
/* and write data */ |
||||
*value = readl(®s->mac_mrdd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Write a word to phyxcer |
||||
*/ |
||||
static int wemac_phy_write(const char *devname, unsigned char addr, |
||||
unsigned char reg, unsigned short value) |
||||
{ |
||||
struct eth_device *dev = eth_get_dev_by_name(devname); |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
|
||||
/* issue the phy address and reg */ |
||||
writel(addr << 8 | reg, ®s->mac_madr); |
||||
|
||||
/* pull up the phy io line */ |
||||
writel(0x1, ®s->mac_mcmd); |
||||
|
||||
/* Wait write complete */ |
||||
mdelay(1); |
||||
|
||||
/* push down the phy io line */ |
||||
writel(0x0, ®s->mac_mcmd); |
||||
|
||||
/* and write data */ |
||||
writel(value, ®s->mac_mwtd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void emac_setup(struct eth_device *dev) |
||||
{ |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
u32 reg_val; |
||||
u16 phy_val; |
||||
u32 duplex_flag; |
||||
|
||||
/* Set up TX */ |
||||
writel(EMAC_TX_SETUP, ®s->tx_mode); |
||||
|
||||
/* Set up RX */ |
||||
writel(EMAC_RX_SETUP, ®s->rx_ctl); |
||||
|
||||
/* Set MAC */ |
||||
/* Set MAC CTL0 */ |
||||
writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); |
||||
|
||||
/* Set MAC CTL1 */ |
||||
wemac_phy_read(dev->name, 1, 0, &phy_val); |
||||
debug("PHY SETUP, reg 0 value: %x\n", phy_val); |
||||
duplex_flag = !!(phy_val & (1 << 8)); |
||||
|
||||
reg_val = 0; |
||||
if (duplex_flag) |
||||
reg_val = (0x1 << 0); |
||||
writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); |
||||
|
||||
/* Set up IPGT */ |
||||
writel(EMAC_MAC_IPGT, ®s->mac_ipgt); |
||||
|
||||
/* Set up IPGR */ |
||||
writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); |
||||
|
||||
/* Set up Collison window */ |
||||
writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); |
||||
|
||||
/* Set up Max Frame Length */ |
||||
writel(EMAC_MAC_MFL, ®s->mac_maxf); |
||||
} |
||||
|
||||
static void wemac_reset(struct eth_device *dev) |
||||
{ |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
|
||||
debug("resetting device\n"); |
||||
|
||||
/* RESET device */ |
||||
writel(0, ®s->ctl); |
||||
udelay(200); |
||||
|
||||
writel(1, ®s->ctl); |
||||
udelay(200); |
||||
} |
||||
|
||||
static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd) |
||||
{ |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
struct wemac_eth_dev *priv = dev->priv; |
||||
u16 phy_reg; |
||||
|
||||
/* Init EMAC */ |
||||
|
||||
/* Flush RX FIFO */ |
||||
setbits_le32(®s->rx_ctl, 0x8); |
||||
udelay(1); |
||||
|
||||
/* Init MAC */ |
||||
|
||||
/* Soft reset MAC */ |
||||
clrbits_le32(®s->mac_ctl0, 1 << 15); |
||||
|
||||
/* Set MII clock */ |
||||
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); |
||||
|
||||
/* Clear RX counter */ |
||||
writel(0x0, ®s->rx_fbc); |
||||
udelay(1); |
||||
|
||||
/* Set up EMAC */ |
||||
emac_setup(dev); |
||||
|
||||
writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 | |
||||
dev->enetaddr[2], ®s->mac_a1); |
||||
writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 | |
||||
dev->enetaddr[5], ®s->mac_a0); |
||||
|
||||
mdelay(1); |
||||
|
||||
wemac_reset(dev); |
||||
|
||||
/* PHY POWER UP */ |
||||
wemac_phy_read(dev->name, 1, 0, &phy_reg); |
||||
wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11))); |
||||
mdelay(1); |
||||
|
||||
wemac_phy_read(dev->name, 1, 0, &phy_reg); |
||||
|
||||
priv->speed = miiphy_speed(dev->name, 0); |
||||
priv->duplex = miiphy_duplex(dev->name, 0); |
||||
|
||||
/* Print link status only once */ |
||||
if (!priv->link_printed) { |
||||
printf("ENET Speed is %d Mbps - %s duplex connection\n", |
||||
priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); |
||||
priv->link_printed = 1; |
||||
} |
||||
|
||||
/* Set EMAC SPEED depend on PHY */ |
||||
clrsetbits_le32(®s->mac_supp, 1 << 8, |
||||
((phy_reg & (1 << 13)) >> 13) << 8); |
||||
|
||||
/* Set duplex depend on phy */ |
||||
clrsetbits_le32(®s->mac_ctl1, 1 << 0, |
||||
((phy_reg & (1 << 8)) >> 8) << 0); |
||||
|
||||
/* Enable RX/TX */ |
||||
setbits_le32(®s->ctl, 0x7); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void sunxi_wemac_eth_halt(struct eth_device *dev) |
||||
{ |
||||
/* Nothing to do here */ |
||||
} |
||||
|
||||
static int sunxi_wemac_eth_recv(struct eth_device *dev) |
||||
{ |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
struct wemac_rxhdr rxhdr; |
||||
u32 rxcount; |
||||
u32 reg_val; |
||||
int rx_len; |
||||
int rx_status; |
||||
int good_packet; |
||||
|
||||
/* Check packet ready or not */ |
||||
|
||||
/*
|
||||
* Race warning: The first packet might arrive with |
||||
* the interrupts disabled, but the second will fix |
||||
*/ |
||||
rxcount = readl(®s->rx_fbc); |
||||
if (!rxcount) { |
||||
/* Had one stuck? */ |
||||
rxcount = readl(®s->rx_fbc); |
||||
if (!rxcount) |
||||
return 0; |
||||
} |
||||
|
||||
reg_val = readl(®s->rx_io_data); |
||||
if (reg_val != 0x0143414d) { |
||||
/* Disable RX */ |
||||
clrbits_le32(®s->ctl, 1 << 2); |
||||
|
||||
/* Flush RX FIFO */ |
||||
setbits_le32(®s->rx_ctl, 1 << 3); |
||||
while (readl(®s->rx_ctl) & (1 << 3)) |
||||
; |
||||
|
||||
/* Enable RX */ |
||||
setbits_le32(®s->ctl, 1 << 2); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* A packet ready now |
||||
* Get status/length |
||||
*/ |
||||
good_packet = 1; |
||||
|
||||
wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); |
||||
|
||||
rx_len = rxhdr.rx_len; |
||||
rx_status = rxhdr.rx_status; |
||||
|
||||
/* Packet Status check */ |
||||
if (rx_len < 0x40) { |
||||
good_packet = 0; |
||||
debug("RX: Bad Packet (runt)\n"); |
||||
} |
||||
|
||||
/* rx_status is identical to RSR register. */ |
||||
if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { |
||||
good_packet = 0; |
||||
if (rx_status & EMAC_CRCERR) |
||||
printf("crc error\n"); |
||||
if (rx_status & EMAC_LENERR) |
||||
printf("length error\n"); |
||||
} |
||||
|
||||
/* Move data from WEMAC */ |
||||
if (good_packet) { |
||||
if (rx_len > DMA_CPU_TRRESHOLD) { |
||||
printf("Received packet is too big (len=%d)\n", rx_len); |
||||
} else { |
||||
wemac_inblk_32bit((void *)®s->rx_io_data, |
||||
NetRxPackets[0], rx_len); |
||||
|
||||
/* Pass to upper layer */ |
||||
NetReceive(NetRxPackets[0], rx_len); |
||||
return rx_len; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len) |
||||
{ |
||||
struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; |
||||
|
||||
/* Select channel 0 */ |
||||
writel(0, ®s->tx_ins); |
||||
|
||||
/* Write packet */ |
||||
wemac_outblk_32bit((void *)®s->tx_io_data, packet, len); |
||||
|
||||
/* Set TX len */ |
||||
writel(len, ®s->tx_pl0); |
||||
|
||||
/* Start translate from fifo to phy */ |
||||
setbits_le32(®s->tx_ctl0, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int sunxi_wemac_initialize(void) |
||||
{ |
||||
struct sunxi_ccm_reg *const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
struct sunxi_sramc_regs *sram = |
||||
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; |
||||
struct eth_device *dev; |
||||
struct wemac_eth_dev *priv; |
||||
int pin; |
||||
|
||||
dev = malloc(sizeof(*dev)); |
||||
if (dev == NULL) |
||||
return -ENOMEM; |
||||
|
||||
priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev)); |
||||
if (!priv) { |
||||
free(dev); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
memset(dev, 0, sizeof(*dev)); |
||||
memset(priv, 0, sizeof(struct wemac_eth_dev)); |
||||
|
||||
/* Map SRAM to EMAC */ |
||||
setbits_le32(&sram->ctrl1, 0x5 << 2); |
||||
|
||||
/* Configure pin mux settings for MII Ethernet */ |
||||
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) |
||||
sunxi_gpio_set_cfgpin(pin, 2); |
||||
|
||||
/* Set up clock gating */ |
||||
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC); |
||||
|
||||
dev->iobase = SUNXI_EMAC_BASE; |
||||
dev->priv = priv; |
||||
dev->init = sunxi_wemac_eth_init; |
||||
dev->halt = sunxi_wemac_eth_halt; |
||||
dev->send = sunxi_wemac_eth_send; |
||||
dev->recv = sunxi_wemac_eth_recv; |
||||
strcpy(dev->name, "wemac"); |
||||
|
||||
eth_register(dev); |
||||
|
||||
miiphy_register(dev->name, wemac_phy_read, wemac_phy_write); |
||||
|
||||
return 0; |
||||
} |
||||
Loading…
Reference in new issue