Wolfgang Denk
14 years ago
commit
cacc342d5a
@ -0,0 +1,95 @@ |
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/*
|
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* (C) Copyright 2010 |
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/mx31.h> |
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#include <asm/arch/mx31-regs.h> |
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#include <mxc_gpio.h> |
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#include <fpga.h> |
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#include <lattice.h> |
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#include "qong_fpga.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_FPGA) |
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static void qong_jtag_init(void) |
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{ |
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return; |
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} |
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static void qong_fpga_jtag_set_tdi(int value) |
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{ |
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mxc_gpio_set(QONG_FPGA_TDI_PIN, value); |
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} |
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static void qong_fpga_jtag_set_tms(int value) |
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{ |
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mxc_gpio_set(QONG_FPGA_TMS_PIN, value); |
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} |
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|
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static void qong_fpga_jtag_set_tck(int value) |
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{ |
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mxc_gpio_set(QONG_FPGA_TCK_PIN, value); |
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} |
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static int qong_fpga_jtag_get_tdo(void) |
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{ |
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return mxc_gpio_get(QONG_FPGA_TDO_PIN); |
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} |
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lattice_board_specific_func qong_fpga_fns = { |
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qong_jtag_init, |
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qong_fpga_jtag_set_tdi, |
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qong_fpga_jtag_set_tms, |
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qong_fpga_jtag_set_tck, |
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qong_fpga_jtag_get_tdo |
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}; |
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Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = { |
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{ |
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Lattice_XP2, |
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lattice_jtag_mode, |
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356519, |
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(void *) &qong_fpga_fns, |
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NULL, |
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0, |
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"lfxp2_5e_ftbga256" |
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}, |
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}; |
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int qong_fpga_init(void) |
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{ |
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int i; |
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fpga_init(); |
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) { |
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fpga_add(fpga_lattice, &qong_fpga[i]); |
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} |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,49 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := igep0020.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,33 @@ |
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#
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# (C) Copyright 2009
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# ISEE 2007 SL, <www.iseebcn.com>
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#
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# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1)
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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# For use with external or internal boots.
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TEXT_BASE = 0x80008000
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@ -0,0 +1,129 @@ |
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/*
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* (C) Copyright 2010 |
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* ISEE 2007 SL, <www.iseebcn.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <twl4030.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/mach-types.h> |
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#include "igep0020.h" |
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/* GPMC definitions for LAN9221 chips */ |
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static const u32 gpmc_lan_config[] = { |
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NET_LAN9221_GPMC_CONFIG1, |
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NET_LAN9221_GPMC_CONFIG2, |
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NET_LAN9221_GPMC_CONFIG3, |
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NET_LAN9221_GPMC_CONFIG4, |
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NET_LAN9221_GPMC_CONFIG5, |
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NET_LAN9221_GPMC_CONFIG6, |
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}; |
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/*
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* Routine: board_init |
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* Description: Early hardware init. |
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*/ |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
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/* board id for Linux */ |
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gd->bd->bi_arch_number = MACH_TYPE_IGEP0020; |
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/* boot param addr */ |
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
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return 0; |
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} |
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/*
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* Routine: setup_net_chip |
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* Description: Setting up the configuration GPMC registers specific to the |
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* Ethernet hardware. |
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*/ |
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#if defined(CONFIG_CMD_NET) |
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static void setup_net_chip(void) |
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{ |
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, |
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GPMC_SIZE_16M); |
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
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writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
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&ctrl_base->gpmc_nadv_ale); |
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/* Make GPIO 64 as output pin and send a magic pulse through it */ |
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if (!omap_request_gpio(64)) { |
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omap_set_gpio_direction(64, 0); |
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omap_set_gpio_dataout(64, 1); |
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udelay(1); |
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omap_set_gpio_dataout(64, 0); |
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udelay(1); |
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omap_set_gpio_dataout(64, 1); |
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} |
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} |
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#endif |
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/*
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* Routine: misc_init_r |
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* Description: Configure board specific parts |
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*/ |
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int misc_init_r(void) |
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{ |
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twl4030_power_init(); |
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#if defined(CONFIG_CMD_NET) |
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setup_net_chip(); |
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#endif |
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dieid_num_r(); |
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return 0; |
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} |
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/*
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* Routine: set_muxconf_regs |
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* Description: Setting up the configuration Mux registers specific to the |
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* hardware. Many pins need to be moved from protect to primary |
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* mode. |
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*/ |
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void set_muxconf_regs(void) |
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{ |
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MUX_DEFAULT(); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC911X |
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
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#endif |
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return rc; |
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} |
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@ -0,0 +1,156 @@ |
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/*
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* (C) Copyright 2010 |
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* ISEE 2007 SL, <www.iseebcn.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _IGEP0020_H_ |
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#define _IGEP0020_H_ |
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const omap3_sysinfo sysinfo = { |
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DDR_STACKED, |
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"IGEP v2 board", |
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"ONENAND", |
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}; |
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/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */ |
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#define NET_LAN9221_GPMC_CONFIG1 0x00001000 |
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#define NET_LAN9221_GPMC_CONFIG2 0x00080701 |
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#define NET_LAN9221_GPMC_CONFIG3 0x00020201 |
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#define NET_LAN9221_GPMC_CONFIG4 0x08030703 |
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#define NET_LAN9221_GPMC_CONFIG5 0x00060908 |
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#define NET_LAN9221_GPMC_CONFIG6 0x87030000 |
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#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c |
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static void setup_net_chip(void); |
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/*
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* IEN - Input Enable |
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* IDIS - Input Disable |
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* PTD - Pull type Down |
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* PTU - Pull type Up |
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* DIS - Pull type selection is inactive |
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* EN - Pull type selection is active |
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* M0 - Mode 0 |
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* The commented string gives the final mux configuration for that pin |
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*/ |
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#define MUX_DEFAULT()\ |
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
|
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
|
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
|
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
|
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
|
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
|
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
|
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
|
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
|
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
|
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MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
|
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MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
|
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MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
|
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MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
|
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MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
|
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MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
|
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MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
|
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MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
|
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
|
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
|
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
|
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
|
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ |
||||
#endif |
||||
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := igep0030.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,34 @@ |
||||
#
|
||||
# (C) Copyright 2009
|
||||
# ISEE 2007 SL, <www.iseebcn.com>
|
||||
#
|
||||
# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80008000
|
||||
|
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* ISEE 2007 SL, <www.iseebcn.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <twl4030.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mem.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/mach-types.h> |
||||
#include "igep0030.h" |
||||
|
||||
/*
|
||||
* Routine: board_init |
||||
* Description: Early hardware init. |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
||||
/* board id for Linux */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_IGEP0030; |
||||
/* boot param addr */ |
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: misc_init_r |
||||
* Description: Configure board specific parts |
||||
*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
twl4030_power_init(); |
||||
|
||||
dieid_num_r(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs |
||||
* Description: Setting up the configuration Mux registers specific to the |
||||
* hardware. Many pins need to be moved from protect to primary |
||||
* mode. |
||||
*/ |
||||
void set_muxconf_regs(void) |
||||
{ |
||||
MUX_DEFAULT(); |
||||
} |
||||
@ -0,0 +1,147 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* ISEE 2007 SL, <www.iseebcn.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _IGEP0030_H_ |
||||
#define _IGEP0030_H_ |
||||
|
||||
const omap3_sysinfo sysinfo = { |
||||
DDR_STACKED, |
||||
"OMAP3 IGEP module", |
||||
"ONENAND", |
||||
}; |
||||
|
||||
/*
|
||||
* IEN - Input Enable |
||||
* IDIS - Input Disable |
||||
* PTD - Pull type Down |
||||
* PTU - Pull type Up |
||||
* DIS - Pull type selection is inactive |
||||
* EN - Pull type selection is active |
||||
* M0 - Mode 0 |
||||
* The commented string gives the final mux configuration for that pin |
||||
*/ |
||||
|
||||
#define MUX_DEFAULT()\ |
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ |
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,399 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* |
||||
* ispVM functions adapted from Lattice's ispmVMEmbedded code: |
||||
* Copyright 2009 Lattice Semiconductor Corp. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <fpga.h> |
||||
#include <lattice.h> |
||||
|
||||
static lattice_board_specific_func *pfns; |
||||
static char *fpga_image; |
||||
static unsigned long read_bytes; |
||||
static unsigned long bufsize; |
||||
static unsigned short expectedCRC; |
||||
|
||||
/*
|
||||
* External variables and functions declared in ivm_core.c module. |
||||
*/ |
||||
extern unsigned short g_usCalculatedCRC; |
||||
extern unsigned short g_usDataType; |
||||
extern unsigned char *g_pucIntelBuffer; |
||||
extern unsigned char *g_pucHeapMemory; |
||||
extern unsigned short g_iHeapCounter; |
||||
extern unsigned short g_iHEAPSize; |
||||
extern unsigned short g_usIntelDataIndex; |
||||
extern unsigned short g_usIntelBufferSize; |
||||
extern char *const g_szSupportedVersions[]; |
||||
|
||||
|
||||
/*
|
||||
* ispVMDelay |
||||
* |
||||
* Users must implement a delay to observe a_usTimeDelay, where |
||||
* bit 15 of the a_usTimeDelay defines the unit. |
||||
* 1 = milliseconds |
||||
* 0 = microseconds |
||||
* Example: |
||||
* a_usTimeDelay = 0x0001 = 1 microsecond delay. |
||||
* a_usTimeDelay = 0x8001 = 1 millisecond delay. |
||||
* |
||||
* This subroutine is called upon to provide a delay from 1 millisecond to a few |
||||
* hundreds milliseconds each time. |
||||
* It is understood that due to a_usTimeDelay is defined as unsigned short, a 16 |
||||
* bits integer, this function is restricted to produce a delay to 64000 |
||||
* micro-seconds or 32000 milli-second maximum. The VME file will never pass on |
||||
* to this function a delay time > those maximum number. If it needs more than |
||||
* those maximum, the VME file will launch the delay function several times to |
||||
* realize a larger delay time cummulatively. |
||||
* It is perfectly alright to provide a longer delay than required. It is not |
||||
* acceptable if the delay is shorter. |
||||
*/ |
||||
void ispVMDelay(unsigned short delay) |
||||
{ |
||||
if (delay & 0x8000) |
||||
delay = (delay & ~0x8000) * 1000; |
||||
udelay(delay); |
||||
} |
||||
|
||||
void writePort(unsigned char a_ucPins, unsigned char a_ucValue) |
||||
{ |
||||
a_ucValue = a_ucValue ? 1 : 0; |
||||
|
||||
switch (a_ucPins) { |
||||
case g_ucPinTDI: |
||||
pfns->jtag_set_tdi(a_ucValue); |
||||
break; |
||||
case g_ucPinTCK: |
||||
pfns->jtag_set_tck(a_ucValue); |
||||
break; |
||||
case g_ucPinTMS: |
||||
pfns->jtag_set_tms(a_ucValue); |
||||
break; |
||||
default: |
||||
printf("%s: requested unknown pin\n", __func__); |
||||
} |
||||
} |
||||
|
||||
unsigned char readPort(void) |
||||
{ |
||||
return pfns->jtag_get_tdo(); |
||||
} |
||||
|
||||
void sclock(void) |
||||
{ |
||||
writePort(g_ucPinTCK, 0x01); |
||||
writePort(g_ucPinTCK, 0x00); |
||||
} |
||||
|
||||
void calibration(void) |
||||
{ |
||||
/* Apply 2 pulses to TCK. */ |
||||
writePort(g_ucPinTCK, 0x00); |
||||
writePort(g_ucPinTCK, 0x01); |
||||
writePort(g_ucPinTCK, 0x00); |
||||
writePort(g_ucPinTCK, 0x01); |
||||
writePort(g_ucPinTCK, 0x00); |
||||
|
||||
ispVMDelay(0x8001); |
||||
|
||||
/* Apply 2 pulses to TCK. */ |
||||
writePort(g_ucPinTCK, 0x01); |
||||
writePort(g_ucPinTCK, 0x00); |
||||
writePort(g_ucPinTCK, 0x01); |
||||
writePort(g_ucPinTCK, 0x00); |
||||
} |
||||
|
||||
/*
|
||||
* GetByte |
||||
* |
||||
* Returns a byte to the caller. The returned byte depends on the |
||||
* g_usDataType register. If the HEAP_IN bit is set, then the byte |
||||
* is returned from the HEAP. If the LHEAP_IN bit is set, then |
||||
* the byte is returned from the intelligent buffer. Otherwise, |
||||
* the byte is returned directly from the VME file. |
||||
*/ |
||||
unsigned char GetByte(void) |
||||
{ |
||||
unsigned char ucData; |
||||
unsigned int block_size = 4 * 1024; |
||||
|
||||
if (g_usDataType & HEAP_IN) { |
||||
|
||||
/*
|
||||
* Get data from repeat buffer. |
||||
*/ |
||||
|
||||
if (g_iHeapCounter > g_iHEAPSize) { |
||||
|
||||
/*
|
||||
* Data over-run. |
||||
*/ |
||||
|
||||
return 0xFF; |
||||
} |
||||
|
||||
ucData = g_pucHeapMemory[g_iHeapCounter++]; |
||||
} else if (g_usDataType & LHEAP_IN) { |
||||
|
||||
/*
|
||||
* Get data from intel buffer. |
||||
*/ |
||||
|
||||
if (g_usIntelDataIndex >= g_usIntelBufferSize) { |
||||
return 0xFF; |
||||
} |
||||
|
||||
ucData = g_pucIntelBuffer[g_usIntelDataIndex++]; |
||||
} else { |
||||
if (read_bytes == bufsize) { |
||||
return 0xFF; |
||||
} |
||||
ucData = *fpga_image++; |
||||
read_bytes++; |
||||
|
||||
if (!(read_bytes % block_size)) { |
||||
printf("Downloading FPGA %ld/%ld completed\r", |
||||
read_bytes, |
||||
bufsize); |
||||
} |
||||
|
||||
if (expectedCRC != 0) { |
||||
ispVMCalculateCRC32(ucData); |
||||
} |
||||
} |
||||
|
||||
return ucData; |
||||
} |
||||
|
||||
signed char ispVM(void) |
||||
{ |
||||
char szFileVersion[9] = { 0 }; |
||||
signed char cRetCode = 0; |
||||
signed char cIndex = 0; |
||||
signed char cVersionIndex = 0; |
||||
unsigned char ucReadByte = 0; |
||||
unsigned short crc; |
||||
|
||||
g_pucHeapMemory = NULL; |
||||
g_iHeapCounter = 0; |
||||
g_iHEAPSize = 0; |
||||
g_usIntelDataIndex = 0; |
||||
g_usIntelBufferSize = 0; |
||||
g_usCalculatedCRC = 0; |
||||
expectedCRC = 0; |
||||
ucReadByte = GetByte(); |
||||
switch (ucReadByte) { |
||||
case FILE_CRC: |
||||
crc = (unsigned char)GetByte(); |
||||
crc <<= 8; |
||||
crc |= GetByte(); |
||||
expectedCRC = crc; |
||||
|
||||
for (cIndex = 0; cIndex < 8; cIndex++) |
||||
szFileVersion[cIndex] = GetByte(); |
||||
|
||||
break; |
||||
default: |
||||
szFileVersion[0] = (signed char) ucReadByte; |
||||
for (cIndex = 1; cIndex < 8; cIndex++) |
||||
szFileVersion[cIndex] = GetByte(); |
||||
|
||||
break; |
||||
} |
||||
|
||||
/*
|
||||
* |
||||
* Compare the VME file version against the supported version. |
||||
* |
||||
*/ |
||||
|
||||
for (cVersionIndex = 0; g_szSupportedVersions[cVersionIndex] != 0; |
||||
cVersionIndex++) { |
||||
for (cIndex = 0; cIndex < 8; cIndex++) { |
||||
if (szFileVersion[cIndex] != |
||||
g_szSupportedVersions[cVersionIndex][cIndex]) { |
||||
cRetCode = VME_VERSION_FAILURE; |
||||
break; |
||||
} |
||||
cRetCode = 0; |
||||
} |
||||
|
||||
if (cRetCode == 0) { |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (cRetCode < 0) { |
||||
return VME_VERSION_FAILURE; |
||||
} |
||||
|
||||
printf("VME file checked: starting downloading to FPGA\n"); |
||||
|
||||
ispVMStart(); |
||||
|
||||
cRetCode = ispVMCode(); |
||||
|
||||
ispVMEnd(); |
||||
ispVMFreeMem(); |
||||
puts("\n"); |
||||
|
||||
if (cRetCode == 0 && expectedCRC != 0 && |
||||
(expectedCRC != g_usCalculatedCRC)) { |
||||
printf("Expected CRC: 0x%.4X\n", expectedCRC); |
||||
printf("Calculated CRC: 0x%.4X\n", g_usCalculatedCRC); |
||||
return VME_CRC_FAILURE; |
||||
} |
||||
return cRetCode; |
||||
} |
||||
|
||||
static int lattice_validate(Lattice_desc *desc, const char *fn) |
||||
{ |
||||
int ret_val = FALSE; |
||||
|
||||
if (desc) { |
||||
if ((desc->family > min_lattice_type) && |
||||
(desc->family < max_lattice_type)) { |
||||
if ((desc->iface > min_lattice_iface_type) && |
||||
(desc->iface < max_lattice_iface_type)) { |
||||
if (desc->size) { |
||||
ret_val = TRUE; |
||||
} else { |
||||
printf("%s: NULL part size\n", fn); |
||||
} |
||||
} else { |
||||
printf("%s: Invalid Interface type, %d\n", |
||||
fn, desc->iface); |
||||
} |
||||
} else { |
||||
printf("%s: Invalid family type, %d\n", |
||||
fn, desc->family); |
||||
} |
||||
} else { |
||||
printf("%s: NULL descriptor!\n", fn); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int lattice_load(Lattice_desc *desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
if (!lattice_validate(desc, (char *)__func__)) { |
||||
printf("%s: Invalid device descriptor\n", __func__); |
||||
} else { |
||||
pfns = desc->iface_fns; |
||||
|
||||
switch (desc->family) { |
||||
case Lattice_XP2: |
||||
fpga_image = buf; |
||||
read_bytes = 0; |
||||
bufsize = bsize; |
||||
debug("%s: Launching the Lattice ISPVME Loader:" |
||||
" addr 0x%x size 0x%x...\n", |
||||
__func__, fpga_image, bufsize); |
||||
ret_val = ispVM(); |
||||
if (ret_val) |
||||
printf("%s: error %d downloading FPGA image\n", |
||||
__func__, ret_val); |
||||
else |
||||
puts("FPGA downloaded successfully\n"); |
||||
break; |
||||
default: |
||||
printf("%s: Unsupported family type, %d\n", |
||||
__func__, desc->family); |
||||
} |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize) |
||||
{ |
||||
puts("Dump not supported for Lattice FPGA\n"); |
||||
|
||||
return FPGA_FAIL; |
||||
|
||||
} |
||||
|
||||
int lattice_info(Lattice_desc *desc) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
if (lattice_validate(desc, (char *)__func__)) { |
||||
printf("Family: \t"); |
||||
switch (desc->family) { |
||||
case Lattice_XP2: |
||||
puts("XP2\n"); |
||||
break; |
||||
/* Add new family types here */ |
||||
default: |
||||
printf("Unknown family type, %d\n", desc->family); |
||||
} |
||||
|
||||
puts("Interface type:\t"); |
||||
switch (desc->iface) { |
||||
case lattice_jtag_mode: |
||||
puts("JTAG Mode\n"); |
||||
break; |
||||
/* Add new interface types here */ |
||||
default: |
||||
printf("Unsupported interface type, %d\n", desc->iface); |
||||
} |
||||
|
||||
printf("Device Size: \t%d bytes\n", |
||||
desc->size); |
||||
|
||||
if (desc->iface_fns) { |
||||
printf("Device Function Table @ 0x%p\n", |
||||
desc->iface_fns); |
||||
switch (desc->family) { |
||||
case Lattice_XP2: |
||||
break; |
||||
/* Add new family types here */ |
||||
default: |
||||
break; |
||||
} |
||||
} else { |
||||
puts("No Device Function Table.\n"); |
||||
} |
||||
|
||||
if (desc->desc) |
||||
printf("Model: \t%s\n", desc->desc); |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
} else { |
||||
printf("%s: Invalid device descriptor\n", __func__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
@ -0,0 +1,415 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Sukumar Ghorai <s-ghorai@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation's version 2 of |
||||
* the License. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <mmc.h> |
||||
#include <part.h> |
||||
#include <i2c.h> |
||||
#include <twl4030.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mmc_host_def.h> |
||||
|
||||
static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); |
||||
static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); |
||||
static struct mmc hsmmc_dev[2]; |
||||
unsigned char mmc_board_init(hsmmc_t *mmc_base) |
||||
{ |
||||
#if defined(CONFIG_TWL4030_POWER) |
||||
twl4030_power_mmc_init(); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_OMAP34XX) |
||||
t2_t *t2_base = (t2_t *)T2_BASE; |
||||
struct prcm *prcm_base = (struct prcm *)PRCM_BASE; |
||||
|
||||
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | |
||||
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
||||
&t2_base->pbias_lite); |
||||
|
||||
writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
||||
&t2_base->devconf0); |
||||
|
||||
writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, |
||||
&t2_base->devconf1); |
||||
|
||||
writel(readl(&prcm_base->fclken1_core) | |
||||
EN_MMC1 | EN_MMC2 | EN_MMC3, |
||||
&prcm_base->fclken1_core); |
||||
|
||||
writel(readl(&prcm_base->iclken1_core) | |
||||
EN_MMC1 | EN_MMC2 | EN_MMC3, |
||||
&prcm_base->iclken1_core); |
||||
#endif |
||||
|
||||
/* TODO add appropriate OMAP4 init - none currently necessary */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void mmc_init_stream(hsmmc_t *mmc_base) |
||||
{ |
||||
|
||||
writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); |
||||
|
||||
writel(MMC_CMD0, &mmc_base->cmd); |
||||
while (!(readl(&mmc_base->stat) & CC_MASK)) |
||||
; |
||||
writel(CC_MASK, &mmc_base->stat) |
||||
; |
||||
writel(MMC_CMD0, &mmc_base->cmd) |
||||
; |
||||
while (!(readl(&mmc_base->stat) & CC_MASK)) |
||||
; |
||||
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
||||
} |
||||
|
||||
|
||||
static int mmc_init_setup(struct mmc *mmc) |
||||
{ |
||||
hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; |
||||
unsigned int reg_val; |
||||
unsigned int dsor; |
||||
|
||||
mmc_board_init(mmc_base); |
||||
|
||||
writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, |
||||
&mmc_base->sysconfig); |
||||
while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) |
||||
; |
||||
writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
||||
while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) |
||||
; |
||||
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
||||
writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, |
||||
&mmc_base->capa); |
||||
|
||||
reg_val = readl(&mmc_base->con) & RESERVED_MASK; |
||||
|
||||
writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | |
||||
MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | |
||||
HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); |
||||
|
||||
dsor = 240; |
||||
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), |
||||
(ICE_STOP | DTO_15THDTO | CEN_DISABLE)); |
||||
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, |
||||
(dsor << CLKD_OFFSET) | ICE_OSCILLATE); |
||||
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) |
||||
; |
||||
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
||||
|
||||
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); |
||||
|
||||
writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | |
||||
IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, |
||||
&mmc_base->ie); |
||||
|
||||
mmc_init_stream(mmc_base); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
||||
struct mmc_data *data) |
||||
{ |
||||
hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; |
||||
unsigned int flags, mmc_stat; |
||||
unsigned int retry = 0x100000; |
||||
|
||||
|
||||
while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) |
||||
; |
||||
writel(0xFFFFFFFF, &mmc_base->stat); |
||||
while (readl(&mmc_base->stat)) |
||||
; |
||||
/*
|
||||
* CMDREG |
||||
* CMDIDX[13:8] : Command index |
||||
* DATAPRNT[5] : Data Present Select |
||||
* ENCMDIDX[4] : Command Index Check Enable |
||||
* ENCMDCRC[3] : Command CRC Check Enable |
||||
* RSPTYP[1:0] |
||||
* 00 = No Response |
||||
* 01 = Length 136 |
||||
* 10 = Length 48 |
||||
* 11 = Length 48 Check busy after response |
||||
*/ |
||||
/* Delay added before checking the status of frq change
|
||||
* retry not supported by mmc.c(core file) |
||||
*/ |
||||
if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) |
||||
udelay(50000); /* wait 50 ms */ |
||||
|
||||
if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
||||
flags = 0; |
||||
else if (cmd->resp_type & MMC_RSP_136) |
||||
flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; |
||||
else if (cmd->resp_type & MMC_RSP_BUSY) |
||||
flags = RSP_TYPE_LGHT48B; |
||||
else |
||||
flags = RSP_TYPE_LGHT48; |
||||
|
||||
/* enable default flags */ |
||||
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | |
||||
MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); |
||||
|
||||
if (cmd->resp_type & MMC_RSP_CRC) |
||||
flags |= CCCE_CHECK; |
||||
if (cmd->resp_type & MMC_RSP_OPCODE) |
||||
flags |= CICE_CHECK; |
||||
|
||||
if (data) { |
||||
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || |
||||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { |
||||
flags |= (MSBS_MULTIBLK | BCE_ENABLE); |
||||
data->blocksize = 512; |
||||
writel(data->blocksize | (data->blocks << 16), |
||||
&mmc_base->blk); |
||||
} else |
||||
writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); |
||||
|
||||
if (data->flags & MMC_DATA_READ) |
||||
flags |= (DP_DATA | DDIR_READ); |
||||
else |
||||
flags |= (DP_DATA | DDIR_WRITE); |
||||
} |
||||
|
||||
writel(cmd->cmdarg, &mmc_base->arg); |
||||
writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
||||
|
||||
do { |
||||
mmc_stat = readl(&mmc_base->stat); |
||||
retry--; |
||||
} while ((mmc_stat == 0) && (retry > 0)); |
||||
|
||||
if (retry == 0) { |
||||
printf("%s : timeout: No status update\n", __func__); |
||||
return TIMEOUT; |
||||
} |
||||
|
||||
if ((mmc_stat & IE_CTO) != 0) |
||||
return TIMEOUT; |
||||
else if ((mmc_stat & ERRI_MASK) != 0) |
||||
return -1; |
||||
|
||||
if (mmc_stat & CC_MASK) { |
||||
writel(CC_MASK, &mmc_base->stat); |
||||
if (cmd->resp_type & MMC_RSP_PRESENT) { |
||||
if (cmd->resp_type & MMC_RSP_136) { |
||||
/* response type 2 */ |
||||
cmd->response[3] = readl(&mmc_base->rsp10); |
||||
cmd->response[2] = readl(&mmc_base->rsp32); |
||||
cmd->response[1] = readl(&mmc_base->rsp54); |
||||
cmd->response[0] = readl(&mmc_base->rsp76); |
||||
} else |
||||
/* response types 1, 1b, 3, 4, 5, 6 */ |
||||
cmd->response[0] = readl(&mmc_base->rsp10); |
||||
} |
||||
} |
||||
|
||||
if (data && (data->flags & MMC_DATA_READ)) { |
||||
mmc_read_data(mmc_base, data->dest, |
||||
data->blocksize * data->blocks); |
||||
} else if (data && (data->flags & MMC_DATA_WRITE)) { |
||||
mmc_write_data(mmc_base, data->src, |
||||
data->blocksize * data->blocks); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size) |
||||
{ |
||||
unsigned int *output_buf = (unsigned int *)buf; |
||||
unsigned int mmc_stat; |
||||
unsigned int count; |
||||
|
||||
/*
|
||||
* Start Polled Read |
||||
*/ |
||||
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; |
||||
count /= 4; |
||||
|
||||
while (size) { |
||||
do { |
||||
mmc_stat = readl(&mmc_base->stat); |
||||
} while (mmc_stat == 0); |
||||
|
||||
if ((mmc_stat & ERRI_MASK) != 0) |
||||
return 1; |
||||
|
||||
if (mmc_stat & BRR_MASK) { |
||||
unsigned int k; |
||||
|
||||
writel(readl(&mmc_base->stat) | BRR_MASK, |
||||
&mmc_base->stat); |
||||
for (k = 0; k < count; k++) { |
||||
*output_buf = readl(&mmc_base->data); |
||||
output_buf++; |
||||
} |
||||
size -= (count*4); |
||||
} |
||||
|
||||
if (mmc_stat & BWR_MASK) |
||||
writel(readl(&mmc_base->stat) | BWR_MASK, |
||||
&mmc_base->stat); |
||||
|
||||
if (mmc_stat & TC_MASK) { |
||||
writel(readl(&mmc_base->stat) | TC_MASK, |
||||
&mmc_base->stat); |
||||
break; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size) |
||||
{ |
||||
unsigned int *input_buf = (unsigned int *)buf; |
||||
unsigned int mmc_stat; |
||||
unsigned int count; |
||||
|
||||
/*
|
||||
* Start Polled Read |
||||
*/ |
||||
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; |
||||
count /= 4; |
||||
|
||||
while (size) { |
||||
do { |
||||
mmc_stat = readl(&mmc_base->stat); |
||||
} while (mmc_stat == 0); |
||||
|
||||
if ((mmc_stat & ERRI_MASK) != 0) |
||||
return 1; |
||||
|
||||
if (mmc_stat & BWR_MASK) { |
||||
unsigned int k; |
||||
|
||||
writel(readl(&mmc_base->stat) | BWR_MASK, |
||||
&mmc_base->stat); |
||||
for (k = 0; k < count; k++) { |
||||
writel(*input_buf, &mmc_base->data); |
||||
input_buf++; |
||||
} |
||||
size -= (count*4); |
||||
} |
||||
|
||||
if (mmc_stat & BRR_MASK) |
||||
writel(readl(&mmc_base->stat) | BRR_MASK, |
||||
&mmc_base->stat); |
||||
|
||||
if (mmc_stat & TC_MASK) { |
||||
writel(readl(&mmc_base->stat) | TC_MASK, |
||||
&mmc_base->stat); |
||||
break; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static void mmc_set_ios(struct mmc *mmc) |
||||
{ |
||||
hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv; |
||||
unsigned int dsor = 0; |
||||
|
||||
/* configue bus width */ |
||||
switch (mmc->bus_width) { |
||||
case 8: |
||||
writel(readl(&mmc_base->con) | DTW_8_BITMODE, |
||||
&mmc_base->con); |
||||
break; |
||||
|
||||
case 4: |
||||
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, |
||||
&mmc_base->con); |
||||
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, |
||||
&mmc_base->hctl); |
||||
break; |
||||
|
||||
case 1: |
||||
default: |
||||
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, |
||||
&mmc_base->con); |
||||
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, |
||||
&mmc_base->hctl); |
||||
break; |
||||
} |
||||
|
||||
/* configure clock with 96Mhz system clock.
|
||||
*/ |
||||
if (mmc->clock != 0) { |
||||
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); |
||||
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) |
||||
dsor++; |
||||
} |
||||
|
||||
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), |
||||
(ICE_STOP | DTO_15THDTO | CEN_DISABLE)); |
||||
|
||||
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, |
||||
(dsor << CLKD_OFFSET) | ICE_OSCILLATE); |
||||
|
||||
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) |
||||
; |
||||
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
||||
} |
||||
|
||||
int omap_mmc_init(int dev_index) |
||||
{ |
||||
struct mmc *mmc; |
||||
|
||||
mmc = &hsmmc_dev[dev_index]; |
||||
|
||||
sprintf(mmc->name, "OMAP SD/MMC"); |
||||
mmc->send_cmd = mmc_send_cmd; |
||||
mmc->set_ios = mmc_set_ios; |
||||
mmc->init = mmc_init_setup; |
||||
|
||||
switch (dev_index) { |
||||
case 0: |
||||
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; |
||||
break; |
||||
case 1: |
||||
mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE; |
||||
break; |
||||
case 2: |
||||
mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE; |
||||
break; |
||||
default: |
||||
mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE; |
||||
return 1; |
||||
} |
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
||||
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
||||
|
||||
mmc->f_min = 400000; |
||||
mmc->f_max = 52000000; |
||||
|
||||
mmc_register(mmc); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, but |
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
||||
* for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software Foundation, |
||||
* Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <usb.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mx31-regs.h> |
||||
#include <usb/ehci-fsl.h> |
||||
#include <errno.h> |
||||
|
||||
#include "ehci.h" |
||||
#include "ehci-core.h" |
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600 |
||||
|
||||
#define MX31_OTG_SIC_SHIFT 29 |
||||
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) |
||||
#define MX31_OTG_PM_BIT (1 << 24) |
||||
|
||||
#define MX31_H2_SIC_SHIFT 21 |
||||
#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) |
||||
#define MX31_H2_PM_BIT (1 << 16) |
||||
#define MX31_H2_DT_BIT (1 << 5) |
||||
|
||||
#define MX31_H1_SIC_SHIFT 13 |
||||
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) |
||||
#define MX31_H1_PM_BIT (1 << 8) |
||||
#define MX31_H1_DT_BIT (1 << 4) |
||||
|
||||
static int mxc_set_usbcontrol(int port, unsigned int flags) |
||||
{ |
||||
unsigned int v; |
||||
#ifdef CONFIG_MX31 |
||||
v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET); |
||||
|
||||
switch (port) { |
||||
case 0: /* OTG port */ |
||||
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); |
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) |
||||
<< MX31_OTG_SIC_SHIFT; |
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
||||
v |= MX31_OTG_PM_BIT; |
||||
|
||||
break; |
||||
case 1: /* H1 port */ |
||||
v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | |
||||
MX31_H1_DT_BIT); |
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) |
||||
<< MX31_H1_SIC_SHIFT; |
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
||||
v |= MX31_H1_PM_BIT; |
||||
|
||||
if (!(flags & MXC_EHCI_TTL_ENABLED)) |
||||
v |= MX31_H1_DT_BIT; |
||||
|
||||
break; |
||||
case 2: /* H2 port */ |
||||
v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | |
||||
MX31_H2_DT_BIT); |
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) |
||||
<< MX31_H2_SIC_SHIFT; |
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
||||
v |= MX31_H2_PM_BIT; |
||||
|
||||
if (!(flags & MXC_EHCI_TTL_ENABLED)) |
||||
v |= MX31_H2_DT_BIT; |
||||
|
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
writel(v, MX31_OTG_BASE_ADDR + |
||||
USBCTRL_OTGBASE_OFFSET); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int ehci_hcd_init(void) |
||||
{ |
||||
u32 tmp; |
||||
struct usb_ehci *ehci; |
||||
struct clock_control_regs *sc_regs = |
||||
(struct clock_control_regs *)CCM_BASE; |
||||
|
||||
tmp = __raw_readl(&sc_regs->ccmr); |
||||
__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; |
||||
|
||||
udelay(80); |
||||
|
||||
/* Take USB2 */ |
||||
ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + |
||||
(0x200 * CONFIG_MXC_USB_PORT)); |
||||
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); |
||||
hcor = (struct ehci_hcor *)((uint32_t) hccr + |
||||
HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
||||
setbits_le32(&ehci->usbmode, CM_HOST); |
||||
setbits_le32(&ehci->control, USB_EN); |
||||
|
||||
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); |
||||
|
||||
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Destroy the appropriate control structures corresponding |
||||
* the the EHCI host controller. |
||||
*/ |
||||
int ehci_hcd_stop(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,228 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* ISEE 2007 SL, <www.iseebcn.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */ |
||||
#define CONFIG_OMAP3430 1 /* which is in a 3430 */ |
||||
#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */ |
||||
|
||||
#define CONFIG_SDRC /* The chip has SDRC controller */ |
||||
|
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/*
|
||||
* Display CPU and Board information |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO 1 |
||||
#define CONFIG_DISPLAY_BOARDINFO 1 |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_REVISION_TAG 1 |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/* select serial console configuration */ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
||||
#define CONFIG_MMC 1 |
||||
#define CONFIG_OMAP3_MMC 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/* DDR */ |
||||
#define CONFIG_OMAP3_NUMONYX_DDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_MUSB_UDC 1 |
||||
#define CONFIG_USB_OMAP3 1 |
||||
#define CONFIG_TWL4030_USB 1 |
||||
|
||||
/* USB device configuration */ |
||||
#define CONFIG_USB_DEVICE 1 |
||||
#define CONFIG_USB_TTY 1 |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
/* Change these to suit your needs */ |
||||
#define CONFIG_USBD_VENDORID 0x0451 |
||||
#define CONFIG_USBD_PRODUCTID 0x5678 |
||||
#define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
||||
#define CONFIG_USBD_PRODUCT_NAME "IGEP" |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_ONENAND /* ONENAND support */ |
||||
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_NFS /* NFS support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
||||
#define CONFIG_MTD_DEVICE |
||||
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_BUS 0 |
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 |
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1 |
||||
|
||||
/*
|
||||
* TWL4030 |
||||
*/ |
||||
#define CONFIG_TWL4030_POWER 1 |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"usbtty=cdc_acm\0" |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT "U-Boot # " |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ |
||||
/* works on */ |
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
||||
0x01F00000) /* 31MB */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
||||
/* load address */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock |
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
||||
* This rate is divided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
* |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ |
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
||||
|
||||
/* SDRAM Bank Allocation method */ |
||||
#define SDRC_R_B_C 1 |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ |
||||
|
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
||||
|
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_ONENAND 1 |
||||
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ |
||||
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */ |
||||
|
||||
/*
|
||||
* SMSC911x Ethernet |
||||
*/ |
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_SMC911X |
||||
#define CONFIG_SMC911X_32_BIT |
||||
#define CONFIG_SMC911X_BASE 0x2C000000 |
||||
#endif /* (CONFIG_CMD_NET) */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,215 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* ISEE 2007 SL, <www.iseebcn.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#include <asm/sizes.h> |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */ |
||||
#define CONFIG_OMAP3430 1 /* which is in a 3430 */ |
||||
#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */ |
||||
|
||||
#define CONFIG_SDRC /* The chip has SDRC controller */ |
||||
|
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/*
|
||||
* Display CPU and Board information |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO 1 |
||||
#define CONFIG_DISPLAY_BOARDINFO 1 |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_REVISION_TAG 1 |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/* select serial console configuration */ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
||||
#define CONFIG_MMC 1 |
||||
#define CONFIG_OMAP3_MMC 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/* DDR */ |
||||
#define CONFIG_OMAP3_NUMONYX_DDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_MUSB_UDC 1 |
||||
#define CONFIG_USB_OMAP3 1 |
||||
#define CONFIG_TWL4030_USB 1 |
||||
|
||||
/* USB device configuration */ |
||||
#define CONFIG_USB_DEVICE 1 |
||||
#define CONFIG_USB_TTY 1 |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
/* Change these to suit your needs */ |
||||
#define CONFIG_USBD_VENDORID 0x0451 |
||||
#define CONFIG_USBD_PRODUCTID 0x5678 |
||||
#define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
||||
#define CONFIG_USBD_PRODUCT_NAME "IGEP" |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_ONENAND /* ONENAND support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
||||
#define CONFIG_MTD_DEVICE |
||||
|
||||
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_BUS 0 |
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 |
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1 |
||||
|
||||
/*
|
||||
* TWL4030 |
||||
*/ |
||||
#define CONFIG_TWL4030_POWER 1 |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0" |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"usbtty=cdc_acm\0" |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT "U-Boot # " |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ |
||||
/* works on */ |
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
||||
0x01F00000) /* 31MB */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
||||
/* load address */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock |
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
||||
* This rate is divided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
* |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ |
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
||||
|
||||
/* SDRAM Bank Allocation method */ |
||||
#define SDRC_R_B_C 1 |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ |
||||
|
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
||||
|
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_ONENAND 1 |
||||
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ |
||||
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,319 @@ |
||||
/*
|
||||
* Porting to U-Boot: |
||||
* |
||||
* (C) Copyright 2010 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* Lattice's ispVME Embedded Tool to load Lattice's FPGA: |
||||
* |
||||
* Lattice Semiconductor Corp. Copyright 2009 |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _VME_OPCODE_H |
||||
#define _VME_OPCODE_H |
||||
|
||||
#define VME_VERSION_NUMBER "12.1" |
||||
|
||||
/* Maximum declarations. */ |
||||
|
||||
#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */ |
||||
#define SCANMAX 64000L /* The maximum SDR/SIR burst. */ |
||||
|
||||
/*
|
||||
* |
||||
* Supported JTAG state transitions. |
||||
* |
||||
*/ |
||||
|
||||
#define RESET 0x00 |
||||
#define IDLE 0x01 |
||||
#define IRPAUSE 0x02 |
||||
#define DRPAUSE 0x03 |
||||
#define SHIFTIR 0x04 |
||||
#define SHIFTDR 0x05 |
||||
/* 11/15/05 Nguyen changed to support DRCAPTURE*/ |
||||
#define DRCAPTURE 0x06 |
||||
|
||||
/*
|
||||
* Flow control register bit definitions. A set bit indicates |
||||
* that the register currently exhibits the corresponding mode. |
||||
*/ |
||||
|
||||
#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */ |
||||
#define CASCADE 0x0002 /* Currently splitting large SDR. */ |
||||
#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */ |
||||
#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */ |
||||
#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */ |
||||
#define VERIFYUES 0x0200 /* Continue if fail is in effect. */ |
||||
|
||||
/*
|
||||
* DataType register bit definitions. A set bit indicates |
||||
* that the register currently holds the corresponding type of data. |
||||
*/ |
||||
|
||||
#define EXPRESS 0x0001 /* Simultaneous program and verify. */ |
||||
#define SIR_DATA 0x0002 /* SIR is the active SVF command. */ |
||||
#define SDR_DATA 0x0004 /* SDR is the active SVF command. */ |
||||
#define COMPRESS 0x0008 /* Data is compressed. */ |
||||
#define TDI_DATA 0x0010 /* TDI data is present. */ |
||||
#define TDO_DATA 0x0020 /* TDO data is present. */ |
||||
#define MASK_DATA 0x0040 /* MASK data is present. */ |
||||
#define HEAP_IN 0x0080 /* Data is from the heap. */ |
||||
#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */ |
||||
#define VARIABLE 0x0400 /* Data is from a declared variable. */ |
||||
#define CRC_DATA 0x0800 /* CRC data is pressent. */ |
||||
#define CMASK_DATA 0x1000 /* CMASK data is pressent. */ |
||||
#define RMASK_DATA 0x2000 /* RMASK data is pressent. */ |
||||
#define READ_DATA 0x4000 /* READ data is pressent. */ |
||||
#define DMASK_DATA 0x8000 /* DMASK data is pressent. */ |
||||
|
||||
/*
|
||||
* |
||||
* Pin opcodes. |
||||
* |
||||
*/ |
||||
|
||||
#define signalENABLE 0x1C /* ispENABLE pin. */ |
||||
#define signalTMS 0x1D /* TMS pin. */ |
||||
#define signalTCK 0x1E /* TCK pin. */ |
||||
#define signalTDI 0x1F /* TDI pin. */ |
||||
#define signalTRST 0x20 /* TRST pin. */ |
||||
|
||||
/*
|
||||
* |
||||
* Supported vendors. |
||||
* |
||||
*/ |
||||
|
||||
#define VENDOR 0x56 |
||||
#define LATTICE 0x01 |
||||
#define ALTERA 0x02 |
||||
#define XILINX 0x03 |
||||
|
||||
/*
|
||||
* Opcode definitions. |
||||
* |
||||
* Note: opcodes must be unique. |
||||
*/ |
||||
|
||||
#define ENDDATA 0x00 /* The end of the current SDR data stream. */ |
||||
#define RUNTEST 0x01 /* The duration to stay at the stable state. */ |
||||
#define ENDDR 0x02 /* The stable state after SDR. */ |
||||
#define ENDIR 0x03 /* The stable state after SIR. */ |
||||
#define ENDSTATE 0x04 /* The stable state after RUNTEST. */ |
||||
#define TRST 0x05 /* Assert the TRST pin. */ |
||||
#define HIR 0x06 /* |
||||
* The sum of the IR bits of the |
||||
* leading devices. |
||||
*/ |
||||
#define TIR 0x07 /* |
||||
* The sum of the IR bits of the trailing |
||||
* devices. |
||||
*/ |
||||
#define HDR 0x08 /* The number of leading devices. */ |
||||
#define TDR 0x09 /* The number of trailing devices. */ |
||||
#define ispEN 0x0A /* Assert the ispEN pin. */ |
||||
#define FREQUENCY 0x0B /* |
||||
* The maximum clock rate to run the JTAG state |
||||
* machine. |
||||
*/ |
||||
#define STATE 0x10 /* Move to the next stable state. */ |
||||
#define SIR 0x11 /* The instruction stream follows. */ |
||||
#define SDR 0x12 /* The data stream follows. */ |
||||
#define TDI 0x13 /* The following data stream feeds into |
||||
the device. */ |
||||
#define TDO 0x14 /* |
||||
* The following data stream is compared against |
||||
* the device. |
||||
*/ |
||||
#define MASK 0x15 /* The following data stream is used as mask. */ |
||||
#define XSDR 0x16 /* |
||||
* The following data stream is for simultaneous |
||||
* program and verify. |
||||
*/ |
||||
#define XTDI 0x17 /* The following data stream is for shift in |
||||
* only. It must be stored for the next |
||||
* XSDR. |
||||
*/ |
||||
#define XTDO 0x18 /* |
||||
* There is not data stream. The data stream |
||||
* was stored from the previous XTDI. |
||||
*/ |
||||
#define MEM 0x19 /* |
||||
* The maximum memory needed to allocate in |
||||
* order hold one row of data. |
||||
*/ |
||||
#define WAIT 0x1A /* The duration of delay to observe. */ |
||||
#define TCK 0x1B /* The number of TCK pulses. */ |
||||
#define SHR 0x23 /* |
||||
* Set the flow control register for |
||||
* right shift |
||||
*/ |
||||
#define SHL 0x24 /* |
||||
* Set the flow control register for left shift. |
||||
*/ |
||||
#define HEAP 0x32 /* The memory size needed to hold one loop. */ |
||||
#define REPEAT 0x33 /* The beginning of the loop. */ |
||||
#define LEFTPAREN 0x35 /* The beginning of data following the loop. */ |
||||
#define VAR 0x55 /* Plac holder for loop data. */ |
||||
#define SEC 0x1C /* |
||||
* The delay time in seconds that must be |
||||
* observed. |
||||
*/ |
||||
#define SMASK 0x1D /* The mask for TDI data. */ |
||||
#define MAX_WAIT 0x1E /* The absolute maximum wait time. */ |
||||
#define ON 0x1F /* Assert the targeted pin. */ |
||||
#define OFF 0x20 /* Dis-assert the targeted pin. */ |
||||
#define SETFLOW 0x30 /* Change the flow control register. */ |
||||
#define RESETFLOW 0x31 /* Clear the flow control register. */ |
||||
|
||||
#define CRC 0x47 /* |
||||
* The following data stream is used for CRC |
||||
* calculation. |
||||
*/ |
||||
#define CMASK 0x48 /* |
||||
* The following data stream is used as mask |
||||
* for CRC calculation. |
||||
*/ |
||||
#define RMASK 0x49 /* |
||||
* The following data stream is used as mask |
||||
* for read and save. |
||||
*/ |
||||
#define READ 0x50 /* |
||||
* The following data stream is used for read |
||||
* and save. |
||||
*/ |
||||
#define ENDLOOP 0x59 /* The end of the repeat loop. */ |
||||
#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */ |
||||
#define VUES 0x61 /* Support continue if fail. */ |
||||
#define DMASK 0x62 /* |
||||
* The following data stream is used for dynamic |
||||
* I/O. |
||||
*/ |
||||
#define COMMENT 0x63 /* Support SVF comments in the VME file. */ |
||||
#define HEADER 0x64 /* Support header in VME file. */ |
||||
#define FILE_CRC 0x65 /* Support crc-protected VME file. */ |
||||
#define LCOUNT 0x66 /* Support intelligent programming. */ |
||||
#define LDELAY 0x67 /* Support intelligent programming. */ |
||||
#define LSDR 0x68 /* Support intelligent programming. */ |
||||
#define LHEAP 0x69 /* |
||||
* Memory needed to hold intelligent data |
||||
* buffer |
||||
*/ |
||||
#define CONTINUE 0x70 /* Allow continuation. */ |
||||
#define LVDS 0x71 /* Support LVDS. */ |
||||
#define ENDVME 0x7F /* End of the VME file. */ |
||||
#define ENDFILE 0xFF /* End of file. */ |
||||
|
||||
/*
|
||||
* |
||||
* ispVM Embedded Return Codes. |
||||
* |
||||
*/ |
||||
|
||||
#define VME_VERIFICATION_FAILURE -1 |
||||
#define VME_FILE_READ_FAILURE -2 |
||||
#define VME_VERSION_FAILURE -3 |
||||
#define VME_INVALID_FILE -4 |
||||
#define VME_ARGUMENT_FAILURE -5 |
||||
#define VME_CRC_FAILURE -6 |
||||
|
||||
#define g_ucPinTDI 0x01 |
||||
#define g_ucPinTCK 0x02 |
||||
#define g_ucPinTMS 0x04 |
||||
#define g_ucPinENABLE 0x08 |
||||
#define g_ucPinTRST 0x10 |
||||
|
||||
/*
|
||||
* |
||||
* Type definitions. |
||||
* |
||||
*/ |
||||
|
||||
/* Support LVDS */ |
||||
typedef struct { |
||||
unsigned short usPositiveIndex; |
||||
unsigned short usNegativeIndex; |
||||
unsigned char ucUpdate; |
||||
} LVDSPair; |
||||
|
||||
typedef enum { |
||||
min_lattice_iface_type, /* insert all new types after this */ |
||||
lattice_jtag_mode, /* jtag/tap */ |
||||
max_lattice_iface_type /* insert all new types before this */ |
||||
} Lattice_iface; |
||||
|
||||
typedef enum { |
||||
min_lattice_type, |
||||
Lattice_XP2, /* Lattice XP2 Family */ |
||||
max_lattice_type /* insert all new types before this */ |
||||
} Lattice_Family; |
||||
|
||||
typedef struct { |
||||
Lattice_Family family; /* part type */ |
||||
Lattice_iface iface; /* interface type */ |
||||
size_t size; /* bytes of data part can accept */ |
||||
void *iface_fns; /* interface function table */ |
||||
void *base; /* base interface address */ |
||||
int cookie; /* implementation specific cookie */ |
||||
char *desc; /* description string */ |
||||
} Lattice_desc; /* end, typedef Altera_desc */ |
||||
|
||||
/* Lattice Model Type */ |
||||
#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1) |
||||
|
||||
/* Board specific implementation specific function types */ |
||||
typedef void (*Lattice_jtag_init)(void); |
||||
typedef void (*Lattice_jtag_set_tdi)(int v); |
||||
typedef void (*Lattice_jtag_set_tms)(int v); |
||||
typedef void (*Lattice_jtag_set_tck)(int v); |
||||
typedef int (*Lattice_jtag_get_tdo)(void); |
||||
|
||||
typedef struct { |
||||
Lattice_jtag_init jtag_init; |
||||
Lattice_jtag_set_tdi jtag_set_tdi; |
||||
Lattice_jtag_set_tms jtag_set_tms; |
||||
Lattice_jtag_set_tck jtag_set_tck; |
||||
Lattice_jtag_get_tdo jtag_get_tdo; |
||||
} lattice_board_specific_func; |
||||
|
||||
void writePort(unsigned char pins, unsigned char value); |
||||
unsigned char readPort(void); |
||||
void sclock(void); |
||||
void ispVMDelay(unsigned short int a_usMicroSecondDelay); |
||||
void calibration(void); |
||||
|
||||
int lattice_load(Lattice_desc *desc, void *buf, size_t bsize); |
||||
int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize); |
||||
int lattice_info(Lattice_desc *desc); |
||||
|
||||
void ispVMStart(void); |
||||
void ispVMEnd(void); |
||||
signed char ispVMCode(void); |
||||
void ispVMDelay(unsigned short int a_usMicroSecondDelay); |
||||
void ispVMCalculateCRC32(unsigned char a_ucData); |
||||
unsigned char GetByte(void); |
||||
void writePort(unsigned char pins, unsigned char value); |
||||
unsigned char readPort(void); |
||||
void sclock(void); |
||||
#endif |
||||
|
||||
Loading…
Reference in new issue