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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

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master
Wolfgang Denk 16 years ago
parent 6c7bc91fb3 4c1883670a
commit cae26e2fdd
137 changed files with 2104 additions and 2415 deletions
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  1. 2
      MAINTAINERS
  2. 2
      MAKEALL
  3. 16
      Makefile
  4. 12
      board/amcc/acadia/acadia.c
  5. 18
      board/amcc/acadia/memory.c
  6. 52
      board/amcc/acadia/pll.c
  7. 104
      board/amcc/bamboo/bamboo.c
  8. 2
      board/amcc/bamboo/flash.c
  9. 4
      board/amcc/bubinga/bubinga.c
  10. 20
      board/amcc/bubinga/flash.c
  11. 4
      board/amcc/canyonlands/canyonlands.c
  12. 32
      board/amcc/ebony/ebony.c
  13. 6
      board/amcc/katmai/katmai.c
  14. 18
      board/amcc/luan/luan.c
  15. 48
      board/amcc/ocotea/ocotea.c
  16. 18
      board/amcc/redwood/redwood.c
  17. 60
      board/amcc/sequoia/sequoia.c
  18. 6
      board/amcc/taihu/taihu.c
  19. 70
      board/amcc/taishan/showinfo.c
  20. 44
      board/amcc/taishan/taishan.c
  21. 20
      board/amcc/walnut/flash.c
  22. 58
      board/amcc/yosemite/yosemite.c
  23. 2
      board/amcc/yucca/flash.c
  24. 20
      board/amcc/yucca/yucca.c
  25. 38
      board/cray/L1/L1.c
  26. 24
      board/cray/L1/init.S
  27. 18
      board/csb272/csb272.c
  28. 50
      board/csb272/init.S
  29. 18
      board/csb472/csb472.c
  30. 54
      board/csb472/init.S
  31. 6
      board/dave/PPChameleonEVB/PPChameleonEVB.c
  32. 8
      board/dave/PPChameleonEVB/flash.c
  33. 2
      board/eric/eric.c
  34. 20
      board/eric/flash.c
  35. 126
      board/eric/init.S
  36. 26
      board/esd/apc405/apc405.c
  37. 8
      board/esd/ar405/flash.c
  38. 2
      board/esd/ash405/ash405.c
  39. 8
      board/esd/ash405/flash.c
  40. 8
      board/esd/canbt/canbt.c
  41. 10
      board/esd/canbt/flash.c
  42. 2
      board/esd/cms700/cms700.c
  43. 8
      board/esd/cms700/flash.c
  44. 12
      board/esd/cpci2dp/cpci2dp.c
  45. 10
      board/esd/cpci2dp/flash.c
  46. 22
      board/esd/cpci405/cpci405.c
  47. 20
      board/esd/cpci405/flash.c
  48. 10
      board/esd/cpciiser4/flash.c
  49. 2
      board/esd/dp405/dp405.c
  50. 8
      board/esd/dp405/flash.c
  51. 8
      board/esd/du405/du405.c
  52. 20
      board/esd/du405/flash.c
  53. 56
      board/esd/du440/du440.c
  54. 8
      board/esd/hh405/flash.c
  55. 2
      board/esd/hh405/hh405.c
  56. 8
      board/esd/hub405/flash.c
  57. 2
      board/esd/hub405/hub405.c
  58. 20
      board/esd/ocrtc/flash.c
  59. 2
      board/esd/ocrtc/ocrtc.c
  60. 8
      board/esd/pci405/flash.c
  61. 28
      board/esd/pci405/pci405.c
  62. 8
      board/esd/plu405/flash.c
  63. 2
      board/esd/plu405/plu405.c
  64. 6
      board/esd/pmc405/pmc405.c
  65. 2
      board/esd/pmc405de/pmc405de.c
  66. 66
      board/esd/pmc440/pmc440.c
  67. 8
      board/esd/voh405/flash.c
  68. 2
      board/esd/voh405/voh405.c
  69. 8
      board/esd/vom405/flash.c
  70. 2
      board/esd/vom405/vom405.c
  71. 8
      board/esd/wuh405/flash.c
  72. 2
      board/esd/wuh405/wuh405.c
  73. 16
      board/exbitgen/exbitgen.c
  74. 104
      board/exbitgen/init.S
  75. 14
      board/g2000/g2000.c
  76. 2
      board/gdsys/dlvision/dlvision.c
  77. 52
      board/gdsys/gdppc440etx/gdppc440etx.c
  78. 0
      board/gdsys/intip/Makefile
  79. 0
      board/gdsys/intip/chip_config.c
  80. 0
      board/gdsys/intip/config.mk
  81. 0
      board/gdsys/intip/init.S
  82. 4
      board/gdsys/intip/intip.c
  83. 2
      board/gdsys/intip/u-boot.lds
  84. 2
      board/gdsys/neo/neo.c
  85. 14
      board/jse/init.S
  86. 8
      board/jse/jse.c
  87. 80
      board/jse/sdram.c
  88. 64
      board/korat/korat.c
  89. 52
      board/lwmon5/lwmon5.c
  90. 58
      board/mpl/common/flash.c
  91. 74
      board/mpl/mip405/init.S
  92. 132
      board/mpl/mip405/mip405.c
  93. 74
      board/mpl/pip405/init.S
  94. 82
      board/mpl/pip405/pip405.c
  95. 2
      board/netstal/hcu4/hcu4.c
  96. 30
      board/netstal/hcu5/hcu5.c
  97. 4
      board/netstal/hcu5/sdram.c
  98. 6
      board/netstal/mcu25/mcu25.c
  99. 58
      board/pcs440ep/pcs440ep.c
  100. 6
      board/prodrive/alpr/alpr.c
  101. Some files were not shown because too many files have changed in this diff Show More

2
MAINTAINERS
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@ -141,10 +141,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
Dirk Eibach <eibach@gdsys.de>
compactcenter PPC460EX
devconcenter PPC460EX
dlvision PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>

2
MAKEALL
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@ -185,7 +185,6 @@ LIST_4xx=" \
canyonlands \
canyonlands_nand \
CMS700 \
compactcenter \
CPCI2DP \
CPCI405 \
CPCI4052 \
@ -214,6 +213,7 @@ LIST_4xx=" \
hcu5 \
HH405 \
HUB405 \
intip \
JSE \
KAREF \
katmai \

16
Makefile
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@ -1308,14 +1308,6 @@ CATcenter_33_config: unconfig
CMS700_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
# Compact-Center & DevCon-Center use different U-Boot images
compactcenter_config \
devconcenter_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
@ -1400,6 +1392,14 @@ HH405_config: unconfig
HUB405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd
# Compact-Center(codename intip) & DevCon-Center use different U-Boot images
intip_config \
devconcenter_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a intip ppc ppc4xx intip gdsys
JSE_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx jse

12
board/amcc/acadia/acadia.c
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@ -57,7 +57,7 @@ int board_early_init_f(void)
#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
@ -65,18 +65,18 @@ int board_early_init_f(void)
acadia_gpio_init();
/* Configure 405EZ for NAND usage */
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(sdrultra0, reg);
mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(SDR0_ULTRA0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
SDR_ULTRA0_NDGPIOBP |
SDR_ULTRA0_EBCRDYEN |
SDR_ULTRA0_NFSRSTEN;
mtsdr(sdrultra0, reg);
mtsdr(SDR0_ULTRA0, reg);
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */

18
board/amcc/acadia/memory.c
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@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
@ -81,25 +81,25 @@ phys_size_t initdram(int board_type)
gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
mtebc(PB1AP, 0x078F1EC0);
mtebc(PB2AP, 0x078F1EC0);
mtebc(PB1CR, 0x000BC000);
mtebc(PB2CR, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
mtebc(PB1AP, 0x9C0201C0);
mtebc(PB2AP, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
mfsdr(SDR0_ULTRA0, val);
mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)

52
board/amcc/acadia/pll.c
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@ -51,11 +51,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033c);
mtcpr(cprplld, 0x0c010200);
mtcpr(cprprimad, 0x04060c0c);
mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033c);
mtcpr(CPR0_PLLD, 0x0c010200);
mtcpr(CPC0_PRIMAD, 0x04060c0c);
mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
@ -83,13 +83,13 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x20000238);
mtcpr(CPR0_PLLD, 0x03010400);
mtcpr(CPC0_PRIMAD, 0x03050a0a);
mtcpr(CPC0_PERC0, 0x00000000);
mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0x07323200);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_333_166_83)
@ -117,12 +117,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033C);
mtcpr(CPR0_PLLD, 0x0a010000);
mtcpr(CPC0_PRIMAD, 0x02040808);
mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xA6A60300);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_100_100_12)
@ -143,12 +143,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x000003BC);
mtcpr(CPR0_PLLD, 0x06060600);
mtcpr(CPC0_PRIMAD, 0x02020004);
mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xC8C81600);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
@ -167,12 +167,12 @@ unsigned long get_tbclk(void)
/*
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(cprprimad, cpr_primad);
mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency

104
board/amcc/bamboo/bamboo.c
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@ -487,35 +487,35 @@ int pci_pre_init(struct pci_controller *hose)
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
@ -695,8 +695,8 @@ void ext_bus_cntlr_init(void)
|
+-------------------------------------------------------------------------*/
/* NVRAM - FPGA */
mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
/*-------------------------------------------------------------------------+
|
@ -749,7 +749,7 @@ void ext_bus_cntlr_init(void)
case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
@ -822,7 +822,7 @@ void ext_bus_cntlr_init(void)
/* Default Strap Settings 5-7 */
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
@ -1013,8 +1013,8 @@ void ext_bus_cntlr_init(void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
EBC0_CFG_PTD_ENABLED |
EBC0_CFG_RTC_2048PERCLK |
EBC0_CFG_EMPL_LOW |
@ -1029,20 +1029,20 @@ void ext_bus_cntlr_init(void)
| Initialize EBC Bank 0-4
+-------------------------------------------------------------------------*/
/* EBC Bank0 */
mtebc(pb0ap, ebc0_cs0_bnap_value);
mtebc(pb0cr, ebc0_cs0_bncr_value);
mtebc(PB0AP, ebc0_cs0_bnap_value);
mtebc(PB0CR, ebc0_cs0_bncr_value);
/* EBC Bank1 */
mtebc(pb1ap, ebc0_cs1_bnap_value);
mtebc(pb1cr, ebc0_cs1_bncr_value);
mtebc(PB1AP, ebc0_cs1_bnap_value);
mtebc(PB1CR, ebc0_cs1_bncr_value);
/* EBC Bank2 */
mtebc(pb2ap, ebc0_cs2_bnap_value);
mtebc(pb2cr, ebc0_cs2_bncr_value);
mtebc(PB2AP, ebc0_cs2_bnap_value);
mtebc(PB2CR, ebc0_cs2_bncr_value);
/* EBC Bank3 */
mtebc(pb3ap, ebc0_cs3_bnap_value);
mtebc(pb3cr, ebc0_cs3_bncr_value);
mtebc(PB3AP, ebc0_cs3_bnap_value);
mtebc(PB3CR, ebc0_cs3_bncr_value);
/* EBC Bank4 */
mtebc(pb4ap, ebc0_cs4_bnap_value);
mtebc(pb4cr, ebc0_cs4_bncr_value);
mtebc(PB4AP, ebc0_cs4_bnap_value);
mtebc(PB4CR, ebc0_cs4_bncr_value);
return;
}
@ -1939,10 +1939,10 @@ void configure_ppc440ep_pins(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
usb2_device_selection_in_fpga();
}
@ -1950,19 +1950,19 @@ void configure_ppc440ep_pins(void)
/* USB1.1 Device Selection */
if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* USB1.1 Host Selection */
if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* NAND Flash Selection */
@ -1971,14 +1971,14 @@ void configure_ppc440ep_pins(void)
update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
#else
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
@ -1991,16 +1991,16 @@ void configure_ppc440ep_pins(void)
else
{
/* Set Mux on EMAC */
mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
}
/* MII Selection */
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
}
@ -2009,9 +2009,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
}
@ -2020,9 +2020,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
}
@ -2071,13 +2071,13 @@ void configure_ppc440ep_pins(void)
/* Packet Reject Function Enable */
if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
{
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
}
/* Perform effective access to hardware */
mtsdr(sdr_pfc1, sdr0_pfc1);
mtsdr(SDR0_PFC1, sdr0_pfc1);
set_chip_gpio_configuration(GPIO0, gpio_tab);
set_chip_gpio_configuration(GPIO1, gpio_tab);

2
board/amcc/bamboo/flash.c
Unescape View File

@ -94,7 +94,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA4
* Read Serial Device Strap Register1 in PPC440EP
*/
mfsdr(sdr_sdstp1, val);
mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;

4
board/amcc/bubinga/bubinga.c
Unescape View File

@ -41,9 +41,9 @@ int board_early_init_f(void)
* and enable the internal PCI arbiter if selected
*/
if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
else
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
return 0;
}

20
board/amcc/bubinga/flash.c
Unescape View File

@ -106,25 +106,25 @@ unsigned long flash_init(void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);

4
board/amcc/canyonlands/canyonlands.c
Unescape View File

@ -475,9 +475,9 @@ int board_early_init_r (void)
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */

32
board/amcc/ebony/ebony.c
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@ -41,30 +41,30 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(pb7ap, 0x01015280); /* FPGA registers */
mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(PB7AP, 0x01015280); /* FPGA registers */
mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose)
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
strap = mfdcr(CPC0_STRP1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;

6
board/amcc/katmai/katmai.c
Unescape View File

@ -220,9 +220,9 @@ int board_early_init_f (void)
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
@ -280,7 +280,7 @@ int pci_pre_init(struct pci_controller * hose )
* The katmai board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;

18
board/amcc/luan/luan.c
Unescape View File

@ -42,12 +42,12 @@ int board_early_init_f(void)
{
u32 mfr;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( pb2ap, 0x03800000 );
mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtebc( PB0AP, 0x03800000 ); /* set chip selects */
mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( PB1AP, 0x03800000 );
mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
@ -67,9 +67,9 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
return 0;
}
@ -147,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose )
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);

48
board/amcc/ocotea/ocotea.c
Unescape View File

@ -54,7 +54,7 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
@ -63,14 +63,14 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/* read FPGA base register FPGA_REG0 */
@ -95,53 +95,53 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| 4 MB FLASH. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
EBC_BXAP_BCE_DISABLE|
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
EBC_BXAP_BEM_WRITEONLY|
EBC_BXAP_PEN_DISABLED);
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------
@ -189,9 +189,9 @@ int board_early_init_f (void)
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mfsdr (sdr_mfr, mfr);
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(sdr_mfr, mfr); */
/* mtsdr(SDR0_MFR, mfr); */
fpga_init();
return 0;
@ -297,7 +297,7 @@ int pci_pre_init(struct pci_controller * hose )
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
@ -379,8 +379,8 @@ void fpga_init(void)
unsigned long sdr0_cust0;
unsigned long pvr;
mfsdr (sdr_pfc0, sdr0_pfc0);
mfsdr (sdr_pfc1, sdr0_pfc1);
mfsdr (SDR0_PFC0, sdr0_pfc0);
mfsdr (SDR0_PFC1, sdr0_pfc1);
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
pvr = get_pvr ();
@ -390,8 +390,8 @@ void fpga_init(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
} else {
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
switch (group)
@ -403,8 +403,8 @@ void fpga_init(void)
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
break;
case 3:
case 4:
@ -412,8 +412,8 @@ void fpga_init(void)
case 6:
/* CPU trace B - Over EBMI */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
mtsdr (sdr_pfc0, sdr0_pfc0);
mtsdr (sdr_pfc1, sdr0_pfc1);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_DISABLE);
break;
@ -421,8 +421,8 @@ void fpga_init(void)
}
/* Initialize the ethernet specific functions in the fpga */
mfsdr(sdr_pfc1, sdr0_pfc1);
mfsdr(sdr_cust0, sdr0_cust0);
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_CUST0, sdr0_cust0);
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))

18
board/amcc/redwood/redwood.c
Unescape View File

@ -220,7 +220,7 @@ static void early_init_EBC(void)
* default value :
* 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
@ -237,8 +237,8 @@ static void early_init_EBC(void)
* since some board registers values may be needed to determine the
* boot type
*/
mtebc(pb1ap, EBC_BXAP_FPGA);
mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
mtebc(PB1AP, EBC_BXAP_FPGA);
mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
}
@ -399,12 +399,12 @@ static void early_reinit_EBC(int computed_boot_device)
break;
}
mtebc(pb0ap, ebc0_cs0_bxap_value);
mtebc(pb0cr, ebc0_cs0_bxcr_value);
mtebc(pb1ap, ebc0_cs1_bxap_value);
mtebc(pb1cr, ebc0_cs1_bxcr_value);
mtebc(pb2ap, ebc0_cs2_bxap_value);
mtebc(pb2cr, ebc0_cs2_bxcr_value);
mtebc(PB0AP, ebc0_cs0_bxap_value);
mtebc(PB0CR, ebc0_cs0_bxcr_value);
mtebc(PB1AP, ebc0_cs1_bxap_value);
mtebc(PB1CR, ebc0_cs1_bxcr_value);
mtebc(PB2AP, ebc0_cs2_bxap_value);
mtebc(PB2CR, ebc0_cs2_bxcr_value);
}
static void early_init_UIC(void)

60
board/amcc/sequoia/sequoia.c
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@ -46,8 +46,8 @@ int board_early_init_f(void)
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the interrupt controller polarities, triggers, etc.
@ -107,8 +107,8 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg);
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
@ -144,19 +144,19 @@ int misc_init_r(void)
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
pbcr = mfdcr(ebccfgd);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
@ -309,8 +309,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
return 0;
}
@ -370,35 +370,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = sequoia_pci_fixup_irq;

6
board/amcc/taihu/taihu.c
Unescape View File

@ -48,14 +48,14 @@ int board_early_init_f(void)
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
/*
* Configure CPC0_PCI to enable PerWE as output
* and enable the internal PCI arbiter
*/
mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
return 0;
}

70
board/amcc/taishan/showinfo.c
Unescape View File

@ -33,60 +33,60 @@ void show_reset_reg(void)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfcpr(clk_pllc,reg);
mfcpr(CPR0_PLLC,reg);
printf("cpr_pllc = %#010lx\n",reg);
mfcpr(clk_plld,reg);
mfcpr(CPR0_PLLD,reg);
printf("cpr_plld = %#010lx\n",reg);
mfcpr(clk_primad,reg);
mfcpr(CPR0_PRIMAD,reg);
printf("cpr_primad = %#010lx\n",reg);
mfcpr(clk_primbd,reg);
mfcpr(CPR0_PRIMBD,reg);
printf("cpr_primbd = %#010lx\n",reg);
mfcpr(clk_opbd,reg);
mfcpr(CPR0_OPBD,reg);
printf("cpr_opbd = %#010lx\n",reg);
mfcpr(clk_perd,reg);
mfcpr(CPR0_PERD,reg);
printf("cpr_perd = %#010lx\n",reg);
mfcpr(clk_mald,reg);
mfcpr(CPR0_MALD,reg);
printf("cpr_mald = %#010lx\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
printf("sdr_ebc = %#010lx\n",reg);
mfsdr(SDR0_EBC,reg);
printf("SDR0_EBC = %#010lx\n",reg);
mfsdr(sdr_cp440,reg);
printf("sdr_cp440 = %#010lx\n",reg);
mfsdr(SDR0_CP440,reg);
printf("SDR0_CP440 = %#010lx\n",reg);
mfsdr(sdr_xcr,reg);
printf("sdr_xcr = %#010lx\n",reg);
mfsdr(SDR0_XCR,reg);
printf("SDR0_XCR = %#010lx\n",reg);
mfsdr(sdr_xpllc,reg);
printf("sdr_xpllc = %#010lx\n",reg);
mfsdr(SDR0_XPLLC,reg);
printf("SDR0_XPLLC = %#010lx\n",reg);
mfsdr(sdr_xplld,reg);
printf("sdr_xplld = %#010lx\n",reg);
mfsdr(SDR0_XPLLD,reg);
printf("SDR0_XPLLD = %#010lx\n",reg);
mfsdr(sdr_pfc0,reg);
printf("sdr_pfc0 = %#010lx\n",reg);
mfsdr(SDR0_PFC0,reg);
printf("SDR0_PFC0 = %#010lx\n",reg);
mfsdr(sdr_pfc1,reg);
printf("sdr_pfc1 = %#010lx\n",reg);
mfsdr(SDR0_PFC1,reg);
printf("SDR0_PFC1 = %#010lx\n",reg);
mfsdr(sdr_cust0,reg);
printf("sdr_cust0 = %#010lx\n",reg);
mfsdr(SDR0_CUST0,reg);
printf("SDR0_CUST0 = %#010lx\n",reg);
mfsdr(sdr_cust1,reg);
printf("sdr_cust1 = %#010lx\n",reg);
mfsdr(SDR0_CUST1,reg);
printf("SDR0_CUST1 = %#010lx\n",reg);
mfsdr(sdr_uart0,reg);
printf("sdr_uart0 = %#010lx\n",reg);
mfsdr(SDR0_UART0,reg);
printf("SDR0_UART0 = %#010lx\n",reg);
mfsdr(sdr_uart1,reg);
printf("sdr_uart1 = %#010lx\n",reg);
mfsdr(SDR0_UART1,reg);
printf("SDR0_UART1 = %#010lx\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
@ -96,14 +96,14 @@ void show_xbridge_info(void)
unsigned long reg;
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
printf("sdr_xcr = %#010lx\n", reg);
mfsdr(SDR0_XCR, reg);
printf("SDR0_XCR = %#010lx\n", reg);
mfsdr(sdr_xpllc, reg);
printf("sdr_xpllc = %#010lx\n", reg);
mfsdr(SDR0_XPLLC, reg);
printf("SDR0_XPLLC = %#010lx\n", reg);
mfsdr(sdr_xplld, reg);
printf("sdr_xplld = %#010lx\n", reg);
mfsdr(SDR0_XPLLD, reg);
printf("SDR0_XPLLD = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));

44
board/amcc/taishan/taishan.c
Unescape View File

@ -47,7 +47,7 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
@ -56,66 +56,66 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------+
| 64MB FLASH. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 1 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| LCM. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| TMP. Initialize bank 3 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| Connector 4~7. Initialize bank 3~ 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb4ap,0);
mtebc(pb4cr,0);
mtebc(pb5ap,0);
mtebc(pb5cr,0);
mtebc(pb6ap,0);
mtebc(pb6cr,0);
mtebc(pb7ap,0);
mtebc(pb7cr,0);
mtebc(PB4AP,0);
mtebc(PB4CR,0);
mtebc(PB5AP,0);
mtebc(PB5CR,0);
mtebc(PB6AP,0);
mtebc(PB6CR,0);
mtebc(PB7AP,0);
mtebc(PB7CR,0);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@ -164,13 +164,13 @@ int board_early_init_f (void)
mtdcr (uic0vr, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(sdr_pfc0,reg);
mfsdr(SDR0_PFC0,reg);
reg |= 0x00300000;
mtsdr(sdr_pfc0,reg);
mtsdr(SDR0_PFC0,reg);
mfsdr(sdr_pfc1,reg);
mfsdr(SDR0_PFC1,reg);
reg |= 0x00100000;
mtsdr(sdr_pfc1,reg);
mtsdr(SDR0_PFC1,reg);
/* Set GPIO 10 and 11 as output */
GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
@ -230,7 +230,7 @@ int pci_pre_init(struct pci_controller * hose )
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;

20
board/amcc/walnut/flash.c
Unescape View File

@ -102,27 +102,27 @@ unsigned long flash_init(void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr =
(pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr =
(pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);

58
board/amcc/yosemite/yosemite.c
Unescape View File

@ -40,9 +40,9 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
* Setup the GPIO pins
@ -101,10 +101,10 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
@ -129,8 +129,8 @@ int misc_init_r (void)
int size_val = 0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
@ -158,8 +158,8 @@ int misc_init_r (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -353,35 +353,35 @@ int pci_pre_init(struct pci_controller *hose)
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}

2
board/amcc/yucca/flash.c
Unescape View File

@ -982,7 +982,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA0
* Read Serial Device Strap Register1 in PPC440SPe
*/
mfsdr(sdr_sdstp1, val);
mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;

20
board/amcc/yucca/yucca.c
Unescape View File

@ -167,7 +167,7 @@ int board_early_init_f (void)
| 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
|
+-------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
@ -188,8 +188,8 @@ int board_early_init_f (void)
| boot type
|
+-------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_FPGA);
mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
mtebc(PB1AP, EBC_BXAP_FPGA);
mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
/*-------------------------------------------------------------------+
|
@ -334,10 +334,10 @@ int board_early_init_f (void)
break;
}
mtebc(pb0ap, ebc0_cs0_bxap_value);
mtebc(pb0cr, ebc0_cs0_bxcr_value);
mtebc(pb2ap, ebc0_cs2_bxap_value);
mtebc(pb2cr, ebc0_cs2_bxcr_value);
mtebc(PB0AP, ebc0_cs0_bxap_value);
mtebc(PB0CR, ebc0_cs0_bxcr_value);
mtebc(PB2AP, ebc0_cs2_bxap_value);
mtebc(PB2CR, ebc0_cs2_bxcr_value);
/*--------------------------------------------------------------------+
| Interrupt controller setup for the AMCC 440SPe Evaluation board.
@ -530,9 +530,9 @@ int board_early_init_f (void)
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
fpga_init();
@ -608,7 +608,7 @@ int pci_pre_init(struct pci_controller * hose )
* The yucca board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;

38
board/cray/L1/L1.c
Unescape View File

@ -198,8 +198,8 @@ static void init_sdram (void)
unsigned long tmp;
/* write SDRAM bank 0 register */
mtdcr (memcfga, mem_mb0cf);
mtdcr (memcfgd, 0x00062001);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
/* To set the appropriate timings, we need to know the SDRAM speed. */
@ -212,26 +212,26 @@ static void init_sdram (void)
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100MHz. */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, 0x0086400D);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
mtdcr (memcfgd, 0x05F00000);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200);
/* sdram controller.*/
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, 0x90800000);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200);
/* initially, disable ECC on all banks */
udelay (200);
mtdcr (memcfga, mem_ecccf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff;
mtdcr (memcfga, mem_ecccf);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGDATA, tmp);
return;
}
@ -282,18 +282,18 @@ int testdram (void)
}
printf ("Enable ECC..");
mtdcr (memcfga, mem_mcopt1);
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
;
udelay (400);
mtdcr (memcfga, mem_ecccf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000;
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
printf ("enabled.\n");
return (0);

24
board/cray/L1/init.S
Unescape View File

@ -87,17 +87,17 @@ ext_bus_cntlr_init:
/* Peripheral Bank 0 (Flash) initialization */
/*---------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
blr
@ -125,16 +125,16 @@ ext_bus_cntlr_init:
/* all reserved bits=0 */
/*---------------------------------------------------------------------- */
/*---------------------------------------------------------------------- */
addi r4,0,pb1ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0185 /* hiword */
ori r4,r4,0x4380 /* loword */
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb1cr
mtdcr ebccfga,r4
addi r4,0,PB1CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
blr

18
board/csb272/csb272.c
Unescape View File

@ -95,7 +95,7 @@ int board_early_init_f(void)
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtebc (epcr, 0xa8400000); /* EBC always driven */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
return 0; /* success */
}
@ -135,29 +135,29 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb1cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb2cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb3cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;

50
board/csb272/init.S
Unescape View File

@ -38,17 +38,17 @@
#define WDCR_EBC(reg,val) \
addi r4,0,reg;\
mtdcr ebccfga,r4;\
mtdcr EBC0_CFGADDR,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
#define WDCR_SDRAM(reg,val) \
addi r4,0,reg;\
mtdcr memcfga,r4;\
mtdcr SDRAM0_CFGADDR,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/******************************************************************************
* Function: ext_bus_cntlr_init
@ -106,51 +106,51 @@ ext_bus_cntlr_init:
* SETUP CPC0_CR0
*******************************************************************/
LI32(r4, 0x007000c0)
mtdcr cntrl0, r4
mtdcr CPC0_CR0, r4
/********************************************************************
* Setup CPC0_CR1: Change PCIINT signal to PerWE
*******************************************************************/
mfdcr r4, cntrl1
mfdcr r4, CPC0_CR1
ori r4, r4, 0x4000
mtdcr cntrl1, r4
mtdcr CPC0_CR1, r4
/********************************************************************
* Setup External Bus Controller (EBC).
*******************************************************************/
WDCR_EBC(epcr, 0xd84c0000)
WDCR_EBC(EBC0_CFG, 0xd84c0000)
/********************************************************************
* Memory Bank 0 (Intel 28F128J3 Flash) initialization
*******************************************************************/
/*WDCR_EBC(pb0ap, 0x02869200)*/
WDCR_EBC(pb0ap, 0x07869200)
WDCR_EBC(pb0cr, 0xfe0bc000)
/*WDCR_EBC(PB1AP, 0x02869200)*/
WDCR_EBC(PB1AP, 0x07869200)
WDCR_EBC(PB0CR, 0xfe0bc000)
/********************************************************************
* Memory Bank 1 (Holtek HT6542B PS/2) initialization
*******************************************************************/
WDCR_EBC(pb1ap, 0x1f869200)
WDCR_EBC(pb1cr, 0xf0818000)
WDCR_EBC(PB1AP, 0x1f869200)
WDCR_EBC(PB1CR, 0xf0818000)
/********************************************************************
* Memory Bank 2 (Epson S1D13506) initialization
*******************************************************************/
WDCR_EBC(pb2ap, 0x05860300)
WDCR_EBC(pb2cr, 0xf045a000)
WDCR_EBC(PB2AP, 0x05860300)
WDCR_EBC(PB2CR, 0xf045a000)
/********************************************************************
* Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
*******************************************************************/
WDCR_EBC(pb3ap, 0x0387d200)
WDCR_EBC(pb3cr, 0xf021c000)
WDCR_EBC(PB3AP, 0x0387d200)
WDCR_EBC(PB3CR, 0xf021c000)
/********************************************************************
* Memory Bank 4-7 (Unused) initialization
*******************************************************************/
WDCR_EBC(pb4ap, 0)
WDCR_EBC(pb4cr, 0)
WDCR_EBC(pb5ap, 0)
WDCR_EBC(pb5cr, 0)
WDCR_EBC(pb6ap, 0)
WDCR_EBC(pb6cr, 0)
WDCR_EBC(pb7ap, 0)
WDCR_EBC(pb7cr, 0)
WDCR_EBC(PB4AP, 0)
WDCR_EBC(PB4CR, 0)
WDCR_EBC(PB5AP, 0)
WDCR_EBC(PB5CR, 0)
WDCR_EBC(PB6AP, 0)
WDCR_EBC(PB6CR, 0)
WDCR_EBC(PB7AP, 0)
WDCR_EBC(PB7CR, 0)
/* We are all done */
mtlr r0 /* Restore link register */

18
board/csb472/csb472.c
Unescape View File

@ -63,7 +63,7 @@ int board_early_init_f(void)
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtebc (epcr, 0xa8400000); /* EBC always driven */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
return 0; /* success */
}
@ -103,29 +103,29 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb1cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb2cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb3cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;

54
board/csb472/init.S
Unescape View File

@ -38,17 +38,17 @@
#define WDCR_EBC(reg,val) \
addi r4,0,reg;\
mtdcr ebccfga,r4;\
mtdcr EBC0_CFGADDR,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
#define WDCR_SDRAM(reg,val) \
addi r4,0,reg;\
mtdcr memcfga,r4;\
mtdcr SDRAM0_CFGADDR,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/******************************************************************************
* Function: ext_bus_cntlr_init
@ -106,47 +106,47 @@ ext_bus_cntlr_init:
* SETUP CPC0_CR0
*******************************************************************/
LI32(r4, 0x00c01030)
mtdcr cntrl0, r4
mtdcr CPC0_CR0, r4
/********************************************************************
* Setup CPC0_CR1: Change PCIINT signal to PerWE
*******************************************************************/
mfdcr r4, cntrl1
mfdcr r4, CPC0_CR1
ori r4, r4, 0x4000
mtdcr cntrl1, r4
mtdcr CPC0_CR1, r4
/********************************************************************
* Setup External Bus Controller (EBC).
*******************************************************************/
WDCR_EBC(epcr, 0xd84c0000)
WDCR_EBC(EBC0_CFG, 0xd84c0000)
/********************************************************************
* Memory Bank 0 (Intel 28F640J3 Flash) initialization
*******************************************************************/
/*WDCR_EBC(pb0ap, 0x03055200)*/
/*WDCR_EBC(pb0ap, 0x04055200)*/
WDCR_EBC(pb0ap, 0x08055200)
WDCR_EBC(pb0cr, 0xff87a000)
/*WDCR_EBC(PB1AP, 0x03055200)*/
/*WDCR_EBC(PB1AP, 0x04055200)*/
WDCR_EBC(PB1AP, 0x08055200)
WDCR_EBC(PB0CR, 0xff87a000)
/********************************************************************
* Memory Bank 3 (Xilinx XC95144 CPLD) initialization
*******************************************************************/
/*WDCR_EBC(pb3ap, 0x07869200)*/
WDCR_EBC(pb3ap, 0x04055200)
WDCR_EBC(pb3cr, 0xf081c000)
/*WDCR_EBC(PB3AP, 0x07869200)*/
WDCR_EBC(PB3AP, 0x04055200)
WDCR_EBC(PB3CR, 0xf081c000)
/********************************************************************
* Memory Bank 1,2,4-7 (Unused) initialization
*******************************************************************/
WDCR_EBC(pb1ap, 0)
WDCR_EBC(pb1cr, 0)
WDCR_EBC(pb2ap, 0)
WDCR_EBC(pb2cr, 0)
WDCR_EBC(pb4ap, 0)
WDCR_EBC(pb4cr, 0)
WDCR_EBC(pb5ap, 0)
WDCR_EBC(pb5cr, 0)
WDCR_EBC(pb6ap, 0)
WDCR_EBC(pb6cr, 0)
WDCR_EBC(pb7ap, 0)
WDCR_EBC(pb7cr, 0)
WDCR_EBC(PB1AP, 0)
WDCR_EBC(PB1CR, 0)
WDCR_EBC(PB2AP, 0)
WDCR_EBC(PB2CR, 0)
WDCR_EBC(PB4AP, 0)
WDCR_EBC(PB4CR, 0)
WDCR_EBC(PB5AP, 0)
WDCR_EBC(PB5CR, 0)
WDCR_EBC(PB6AP, 0)
WDCR_EBC(PB6CR, 0)
WDCR_EBC(PB7AP, 0)
WDCR_EBC(PB7CR, 0)
/* We are all done */
mtlr r0 /* Restore link register */

6
board/dave/PPChameleonEVB/PPChameleonEVB.c
Unescape View File

@ -65,9 +65,9 @@ int board_early_init_f (void)
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
#if 1 /* test-only */
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
#else
mtebc (epcr, 0x28400000); /* ebc in high-z */
mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
#endif
return 0;
}
@ -101,7 +101,7 @@ int misc_init_r (void)
int status;
int index;
int i;
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {

8
board/dave/PPChameleonEVB/flash.c
Unescape View File

@ -75,9 +75,9 @@ unsigned long flash_init (void)
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base = -size;
switch (size) {
case 1 << 20:
@ -97,7 +97,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
/* Monitor protection ON by default */

2
board/eric/eric.c
Unescape View File

@ -70,7 +70,7 @@ int board_early_init_f (void)
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
out32 (PPC405GP_GPIO0_TCR, 0x7E400000);

20
board/eric/flash.c
Unescape View File

@ -105,24 +105,24 @@ unsigned long flash_init (void)
if (size_b1)
{
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0)
{
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);

126
board/eric/init.S
Unescape View File

@ -76,129 +76,129 @@ ext_bus_cntlr_init:
/* Memory Bank 0 (Flash) initialization (from openbios) */
/*----------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS0_AP@h
ori r4,r4,CS0_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS0_CR@h
ori r4,r4,CS0_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 1 (NVRAM/RTC) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb1ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS1_AP@h
ori r4,r4,CS1_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb1cr
mtdcr ebccfga,r4
addi r4,0,PB1CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS1_CR@h
ori r4,r4,CS1_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 2 (A/D converter) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb2ap
mtdcr ebccfga,r4
addi r4,0,PB2AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS2_AP@h
ori r4,r4,CS2_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb2cr
mtdcr ebccfga,r4
addi r4,0,PB2CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS2_CR@h
ori r4,r4,CS2_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 3 (Ethernet PHY Reset) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb3ap
mtdcr ebccfga,r4
addi r4,0,PB3AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS3_AP@h
ori r4,r4,CS3_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb3cr
mtdcr ebccfga,r4
addi r4,0,PB3CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS3_CR@h
ori r4,r4,CS3_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb4ap
mtdcr ebccfga,r4
addi r4,0,PB4AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS4_AP@h
ori r4,r4,CS4_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb4cr
mtdcr ebccfga,r4
addi r4,0,PB4CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS4_CR@h
ori r4,r4,CS4_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb5ap
mtdcr ebccfga,r4
addi r4,0,PB5AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS5_AP@h
ori r4,r4,CS5_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb5cr
mtdcr ebccfga,r4
addi r4,0,PB5CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS5_CR@h
ori r4,r4,CS5_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 6 (CPU LED0) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb6ap
mtdcr ebccfga,r4
addi r4,0,PB6AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS6_AP@h
ori r4,r4,CS6_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb6cr
mtdcr ebccfga,r4
addi r4,0,PB6CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS6_CR@h
ori r4,r4,CS5_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 7 (CPU LED1) initialization */
/*----------------------------------------------------------------------- */
addi r4,0,pb7ap
mtdcr ebccfga,r4
addi r4,0,PB7AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS7_AP@h
ori r4,r4,CS7_AP@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb7cr
mtdcr ebccfga,r4
addi r4,0,PB7CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,CS7_CR@h
ori r4,r4,CS7_CR@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/* addis r4,r0,FPGA_BRDC@h */
/* ori r4,r4,FPGA_BRDC@l */
@ -229,40 +229,40 @@ sdram_init:
/*------------------------------------------------------------------- */
addi r4,0,mem_mb0cf
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB0CF@h
ori r4,r4,MB0CF@l
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb1cf
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB1CF@h
ori r4,r4,MB1CF@l
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB2CF for bank 2. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb2cf
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB2CF@h
ori r4,r4,MB2CF@l
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB3CF for bank 3. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb3cf
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB3CF@h
ori r4,r4,MB3CF@l
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
@ -276,7 +276,7 @@ sdram_init:
/* maybe 133Mhz. */
/*------------------------------------------------------------------- */
mfdcr r5,strap /* determine FBK divider */
mfdcr r5,CPC0_PSR /* determine FBK divider */
/* via STRAP reg to calc PLB speed. */
/* SDRAM speed is the same as the PLB */
/* speed. */
@ -306,15 +306,15 @@ sdram_init:
/* Set SDTR1 */
/*------------------------------------------------------------------- */
addi r4,0,mem_sdtr1
mtdcr memcfga,r4
mtdcr memcfgd,r6
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r6
/*------------------------------------------------------------------- */
/* Set RTR */
/*------------------------------------------------------------------- */
addi r4,0,mem_rtr
mtdcr memcfga,r4
mtdcr memcfgd,r7
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
/*------------------------------------------------------------------- */
/* Delay to ensure 200usec have elapsed since reset. Assume worst */
@ -333,10 +333,10 @@ sdram_init:
/* read/prefetch. */
/*------------------------------------------------------------------- */
addi r4,0,mem_mcopt1
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x8080 /* set DC_EN=1 */
ori r4,r4,0x0000
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Delay to ensure 10msec have elapsed since reset. This is */

26
board/esd/apc405/apc405.c
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@ -92,7 +92,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
int board_revision(void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
unsigned long value;
/*
@ -100,8 +100,8 @@ int board_revision(void)
*/
/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03800000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
@ -113,7 +113,7 @@ int board_revision(void)
/*
* Restore GPIO settings
*/
mtdcr(cntrl0, cntrl0Reg);
mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x001c0000:
@ -166,7 +166,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* New boards have a single 32MB flash connected to CS0
@ -174,12 +174,12 @@ int board_early_init_f (void)
*/
if (board_revision() >= 8) {
/* disable CS1 */
mtebc(pb1ap, 0);
mtebc(pb1cr, 0);
mtebc(PB1AP, 0);
mtebc(PB1CR, 0);
/* resize CS0 to 32MB */
mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
}
return 0;
@ -209,7 +209,7 @@ int misc_init_r(void)
int status;
int index;
int i;
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
@ -219,8 +219,8 @@ int misc_init_r(void)
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
@ -265,7 +265,7 @@ int misc_init_r(void)
}
/* restore gpio/cs settings */
mtdcr(cntrl0, cntrl0Reg);
mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");

8
board/esd/ar405/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/ash405/ash405.c
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@ -77,7 +77,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

8
board/esd/ash405/flash.c
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@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

8
board/esd/canbt/canbt.c
Unescape View File

@ -52,16 +52,16 @@ const unsigned char fpgadata[] = {
int board_early_init_f (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
int index, len, i;
int status;
/*
* Setup GPIO pins
*/
cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff;
cntrl0Reg |= 0x0070f000;
mtdcr (cntrl0, cntrl0Reg);
CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
CPC0_CR0Reg |= 0x0070f000;
mtdcr (CPC0_CR0, CPC0_CR0Reg);
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */

10
board/esd/canbt/flash.c
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@ -64,13 +64,13 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/cms700/cms700.c
Unescape View File

@ -56,7 +56,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* Reset CPLD via GPIO12 (CS3) pin

8
board/esd/cms700/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

12
board/esd/cpci2dp/cpci2dp.c
Unescape View File

@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
/*
* Setup GPIO pins
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg |
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg |
((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
@ -72,7 +72,7 @@ int board_early_init_f (void)
int misc_init_r (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -81,8 +81,8 @@ int misc_init_r (void)
/*
* Select cts (and not dsr) on uart1
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00001000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return (0);
}

10
board/esd/cpci2dp/flash.c
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@ -64,13 +64,13 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

22
board/esd/cpci405/cpci405.c
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@ -214,7 +214,7 @@ int ctermm2(void)
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
return -1; /* yes, board is cpci405 host */
else
return 0; /* no, board is cpci405 adapter */
@ -222,14 +222,14 @@ int cpci405_host(void)
int cpci405_version(void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
unsigned long value;
/*
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
@ -238,7 +238,7 @@ int cpci405_version(void)
/*
* Restore GPIO settings
*/
mtdcr(cntrl0, cntrl0Reg);
mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x00180000:
@ -261,7 +261,7 @@ int cpci405_version(void)
int misc_init_r (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -283,8 +283,8 @@ int misc_init_r (void)
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
@ -330,7 +330,7 @@ int misc_init_r (void)
}
/* restore gpio/cs settings */
mtdcr(cntrl0, cntrl0Reg);
mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
@ -400,8 +400,8 @@ int misc_init_r (void)
/*
* Select cts (and not dsr) on uart1
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00001000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return 0;
}

20
board/esd/cpci405/flash.c
Unescape View File

@ -91,13 +91,13 @@ unsigned long flash_init (void)
size_b1 = 1 << 20;
}
base_b1 = -size_b1;
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
mtdcr (ebccfgd, pbcr);
mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
printf("size_b1=%x base_b1=%x pb1cr = %x\n",
printf("size_b1=%x base_b1=%x PB1CR = %x\n",
size_b1, base_b1, pbcr); /* test-only */
#endif
}
@ -108,13 +108,13 @@ unsigned long flash_init (void)
size_b0 = 1 << 20;
}
base_b0 = base_b1 - size_b0;
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
mtdcr (ebccfgd, pbcr);
mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
printf("size_b0=%x base_b0=%x pb0cr = %x\n",
printf("size_b0=%x base_b0=%x PB0CR = %x\n",
size_b0, base_b0, pbcr); /* test-only */
#endif
}

10
board/esd/cpciiser4/flash.c
Unescape View File

@ -64,13 +64,13 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/dp405/dp405.c
Unescape View File

@ -54,7 +54,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* Reset CPLD via GPIO13 (CS4) pin

8
board/esd/dp405/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

8
board/esd/du405/du405.c
Unescape View File

@ -135,7 +135,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 100 us
*/
mtebc (epcr, 0xb8400000);
mtebc (EBC0_CFG, 0xb8400000);
return 0;
}
@ -143,13 +143,13 @@ int board_early_init_f (void)
int misc_init_r (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
/*
* Setup UART1 handshaking: use CTS instead of DSR
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00001000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return (0);
}

20
board/esd/du405/flash.c
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@ -67,25 +67,25 @@ unsigned long flash_init (void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

56
board/esd/du440/du440.c
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@ -45,8 +45,8 @@ int board_early_init_f(void)
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the GPIO pins
@ -145,8 +145,8 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg);
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
@ -176,12 +176,12 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
@ -265,8 +265,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
/*
* release IO-RST#
@ -380,35 +380,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}

8
board/esd/hh405/flash.c
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@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/hh405/hh405.c
Unescape View File

@ -374,7 +374,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

8
board/esd/hub405/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/hub405/hub405.c
Unescape View File

@ -97,7 +97,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

20
board/esd/ocrtc/flash.c
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@ -68,9 +68,9 @@ unsigned long flash_init (void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
switch (size_b1) {
case 1 << 20:
@ -90,14 +90,14 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
switch (size_b1) {
case 1 << 20:
@ -117,8 +117,8 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

2
board/esd/ocrtc/ocrtc.c
Unescape View File

@ -57,7 +57,7 @@ int board_early_init_f (void)
* EBC Configuration Register: clear EBTC -> high-Z ebc signals between
* transfers, set device-paced timeout to 256 cycles
*/
mtebc (epcr, 0x20400000);
mtebc (EBC0_CFG, 0x20400000);
return 0;
}

8
board/esd/pci405/flash.c
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@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

28
board/esd/pci405/pci405.c
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@ -67,7 +67,7 @@ const unsigned char fpgadata[] =
int board_revision(void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
unsigned long value;
/*
@ -77,8 +77,8 @@ int board_revision(void)
/*
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
udelay(1000); /* wait some time before reading input */
@ -87,7 +87,7 @@ int board_revision(void)
/*
* Restore GPIO settings
*/
mtdcr(cntrl0, cntrl0Reg);
mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x00100200:
@ -133,7 +133,7 @@ unsigned long fpga_init_state(void)
int board_early_init_f (void)
{
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
@ -166,18 +166,18 @@ int board_early_init_f (void)
/*
* Setup GPIO pins (IRQ4/GPIO21 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00008000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
@ -282,11 +282,11 @@ int misc_init_r (void)
#define PCI0_BRDGOPT1 0x4a
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
#define plb0_acr 0x87
#define PLB0_ACR 0x87
/*
* Enable fairness and high bus utilization
*/
mtdcr(plb0_acr, 0x98000000);
mtdcr(PLB0_ACR, 0x98000000);
free(dst);
return (0);
@ -313,14 +313,14 @@ int checkboard (void)
printf(" (Rev 1.%ld", gd->board_type);
if (gd->board_type >= 2) {
unsigned long cntrl0Reg;
unsigned long CPC0_CR0Reg;
unsigned long value;
/*
* Setup GPIO pins (Trace/GPIO1 to GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
udelay(1000); /* wait some time before reading input */

8
board/esd/plu405/flash.c
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@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/plu405/plu405.c
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@ -90,7 +90,7 @@ int board_early_init_f(void)
* EBC Configuration Register: set ready timeout to
* 512 ebc-clks -> ca. 15 us
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

6
board/esd/pmc405/pmc405.c
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@ -60,12 +60,12 @@ int board_early_init_f (void)
* EBC Configuration Register:
* set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000);
mtebc (EBC0_CFG, 0xa8400000);
/*
* Setup GPIO pins
*/
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT |
mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
CONFIG_SYS_FPGA_DONE |
CONFIG_SYS_XEREADY |
CONFIG_SYS_NONMONARCH |
@ -73,7 +73,7 @@ int board_early_init_f (void)
if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
/* rev 1.2 boards */
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE |
mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
CONFIG_SYS_SELF_RST) << 5));
}

2
board/esd/pmc405de/pmc405de.c
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@ -127,7 +127,7 @@ int board_early_init_f(void)
* - set ready timeout to 512 ebc-clks -> ca. 15 us
* - EBC lines are always driven
*/
mtebc(epcr, 0xa8400000);
mtebc(EBC0_CFG, 0xa8400000);
return 0;
}

66
board/esd/pmc440/pmc440.c
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@ -64,7 +64,7 @@ struct serial_device *default_serial_console(void)
* Use default console on P4 when strapping jumper
* is installed (bootstrap option != 'H').
*/
mfsdr(SDR_PINSTP, val);
mfsdr(SDR0_PINSTP, val);
if (((val & 0xf0000000) >> 29) != 7)
return &serial1_device;
@ -100,8 +100,8 @@ int board_early_init_f(void)
u32 reg;
/* general EBC configuration (disable EBC timeouts) */
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xf8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xf8400000);
/*
* Setup the GPIO pins
@ -134,13 +134,13 @@ int board_early_init_f(void)
out_be32((void *)GPIO1_ISR3H, 0x00000000);
/* patch PLB:PCI divider for 66MHz PCI */
mfcpr(clk_spcid, reg);
mfcpr(CPR0_SPCID, reg);
if (pci_is_66mhz() && (reg != 0x02000000)) {
mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
mfcpr(clk_icfg, reg);
mfcpr(CPR0_ICFG, reg);
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(clk_icfg, reg);
mtcpr(CPR0_ICFG, reg);
mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
}
@ -240,19 +240,19 @@ int misc_init_r(void)
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb2cr);
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
pbcr = mfdcr(ebccfgd);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb2cr);
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
@ -424,8 +424,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
#ifdef CONFIG_FPGA
pmc440_init_fpga();
@ -507,35 +507,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#ifdef CONFIG_PCI_PNP
hose->fixup_irq = pmc440_pci_fixup_irq;

8
board/esd/voh405/flash.c
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@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/voh405/voh405.c
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@ -99,7 +99,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

8
board/esd/vom405/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/vom405/vom405.c
Unescape View File

@ -56,7 +56,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* Reset CPLD via GPIO12 (CS3) pin

8
board/esd/wuh405/flash.c
Unescape View File

@ -65,9 +65,9 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
@ -87,7 +87,7 @@ unsigned long flash_init (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,

2
board/esd/wuh405/wuh405.c
Unescape View File

@ -75,7 +75,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

16
board/exbitgen/exbitgen.c
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@ -94,29 +94,29 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb1cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb2cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb3cf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;

104
board/exbitgen/init.S
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@ -109,10 +109,10 @@
#define WDCR_EBC(reg,val) addi r4,0,reg;\
mtdcr ebccfga,r4;\
mtdcr EBC0_CFGADDR,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
/*---------------------------------------------------------------------
* Function: ext_bus_cntlr_init
@ -164,22 +164,22 @@ ext_bus_cntlr_init:
* Memory Bank 0 (Boot Flash) initialization
*---------------------------------------------------------------
*/
WDCR_EBC(pb0ap, FLASH_32bit_AP)
WDCR_EBC(pb0cr, 0xffe38000)
/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */
WDCR_EBC(PB1AP, FLASH_32bit_AP)
WDCR_EBC(PB0CR, 0xffe38000)
/*pnc WDCR_EBC(PB0CR, FLASH_32bit_CR) */
/*---------------------------------------------------------------
* Memory Bank 5 (CPLD) initialization
*---------------------------------------------------------------
*/
WDCR_EBC(pb5ap, 0x01010040)
/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
WDCR_EBC(pb5cr, 0x10038000)
WDCR_EBC(PB5AP, 0x01010040)
/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */
WDCR_EBC(PB5CR, 0x10038000)
/*--------------------------------------------------------------- */
/* Memory Bank 6 (not used) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb6cr, 0x00000000)
WDCR_EBC(PB6CR, 0x00000000)
/* Read HW ID to determine whether old H2 board or new generic CPU board */
addis r3, 0, HW_ID_ADDR@h
@ -196,24 +196,24 @@ setup_genieboard:
/*--------------------------------------------------------------- */
/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
/*--------------------------------------------------------------- */
/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */
/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */
/* WDCR_EBC(PB1AP, 0x7b015480) /###* T.B.M. */
/* WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(PB1AP, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */
/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */
WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */
/* WDCR_EBC(PB1CR, 0x20098000) /###* 16 MB */
WDCR_EBC(PB1CR, 0x200B8000) /* 32 MB */
/*--------------------------------------------------------------- */
/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
/*--------------------------------------------------------------- */
WDCR_EBC(pb4ap, 0x01010000) /* */
WDCR_EBC(pb4cr, 0x1021c000) /* */
WDCR_EBC(PB4AP, 0x01010000) /* */
WDCR_EBC(PB4CR, 0x1021c000) /* */
/*--------------------------------------------------------------- */
/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */
WDCR_EBC(pb7cr, 0X4001A000)
WDCR_EBC(PB7AP, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */
WDCR_EBC(PB7CR, 0X4001A000)
bl setup_continue
@ -222,36 +222,36 @@ setup_h2evalboard:
/*--------------------------------------------------------------- */
/* Memory Bank 1 (Application Flash) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(pb1cr, 0x20058000)
WDCR_EBC(PB1AP, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(PB1CR, 0x20058000)
/*--------------------------------------------------------------- */
/* Memory Bank 2 (Application Flash) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(pb2cr, 0x20458000)
WDCR_EBC(PB2AP, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(PB2AP, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(PB2CR, 0x20458000)
/*--------------------------------------------------------------- */
/* Memory Bank 3 (Application Flash) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(pb3cr, 0x20858000)
WDCR_EBC(PB3AP, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(PB3AP, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(PB3CR, 0x20858000)
/*--------------------------------------------------------------- */
/* Memory Bank 4 (Application Flash) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(pb4cr, 0x20C58000)
WDCR_EBC(PB4AP, 0x7b015480) /* T.B.M. */
/*3010 WDCR_EBC(PB4AP, 0x7F8FFE80) /###* T.B.M. */
WDCR_EBC(PB4CR, 0x20C58000)
/*--------------------------------------------------------------- */
/* Memory Bank 7 (Heathrow chip) initialization */
/*--------------------------------------------------------------- */
WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */
WDCR_EBC(pb7cr, 0X4001A000)
WDCR_EBC(PB7AP, 0x02000280) /* No Ready, 4 wait states */
WDCR_EBC(PB7CR, 0X4001A000)
setup_continue:
@ -294,7 +294,7 @@ sdram_init:
/* Read PLL feedback divider and calculate clock period of local bus in */
/* granularity of 10 ps. Save clock period in r30 */
/*-------------------------------------------------------------- */
mfdcr r4, pllmd
mfdcr r4, CPC0_PLLMR
addi r9, 0, 25
srw r4, r4, r9
andi. r4, r4, 0x07
@ -383,8 +383,8 @@ sdram_init:
/* Set SDTR1 */
/*----------------------------------------------------------- */
addi r5,0,mem_sdtr1
mtdcr memcfga,r5
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGADDR,r5
mtdcr SDRAM0_CFGDATA,r4
/*----------------------------------------------------------- */
/* */
@ -414,8 +414,8 @@ sdram_init:
/* Set SDRAM bank 0 register and adjust r6 for next bank */
/*------------------------------------------------------ */
addi r7,0,mem_mb0cf
mtdcr memcfga,r7
mtdcr memcfgd,r6
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
add r6, r6, r15 /* add bank size to base address for next bank */
@ -425,16 +425,16 @@ sdram_init:
bne b1skip
addi r7,0,mem_mb1cf
mtdcr memcfga,r7
mtdcr memcfgd,r6
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
add r6, r6, r15 /* add bank size to base address for next bank */
/* Set SDRAM bank 2 register and adjust r6 for next bank */
/*------------------------------------------------------ */
b1skip: addi r7,0,mem_mb2cf
mtdcr memcfga,r7
mtdcr memcfgd,r6
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
add r6, r6, r15 /* add bank size to base address for next bank */
@ -444,8 +444,8 @@ b1skip: addi r7,0,mem_mb2cf
bne b3skip
addi r7,0,mem_mb3cf
mtdcr memcfga,r7
mtdcr memcfgd,r6
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
b3skip:
/*----------------------------------------------------------- */
@ -457,8 +457,8 @@ b3skip:
bl rtr_2
rtr_1: addis r7, 0, 0x03F8
rtr_2: addi r4,0,mem_rtr
mtdcr memcfga,r4
mtdcr memcfgd,r7
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
/*----------------------------------------------------------- */
/* Delay to ensure 200usec have elapsed since reset. Assume worst */
@ -477,10 +477,10 @@ rtr_2: addi r4,0,mem_rtr
/* read/prefetch. */
/*----------------------------------------------------------- */
addi r4,0,mem_mcopt1
mtdcr memcfga,r4
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x80C0 /* set DC_EN=1 */
ori r4,r4,0x0000
mtdcr memcfgd,r4
mtdcr SDRAM0_CFGDATA,r4
/*----------------------------------------------------------- */
@ -980,9 +980,9 @@ fc07:
/* For CPLD */
/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
/* WDCR_EBC(pb5ap, 0x01010040) */
/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
/* WDCR_EBC(pb5cr, 0X10018000) */
/* WDCR_EBC(PB5AP, 0x01010040) */
/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */
/* WDCR_EBC(PB5CR, 0X10018000) */
/* Access parms */
/* 100 3 8 0 0 0 */
/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
@ -1003,9 +1003,9 @@ fc07:
/* Usage: read/write */
/* Width: 32 bit */
/* Walnut fpga pb7ap */
/* Walnut fpga PB7AP */
/* 0 1 8 1 5 2 8 0 */
/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
/* Walnut fpga pb7cr */
/* Walnut fpga PB7CR */
/* 0xF0318000 */
/* */

14
board/g2000/g2000.c
Unescape View File

@ -58,7 +58,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
#endif
return 0;
@ -114,7 +114,7 @@ int checkboard (void)
long int init_sdram_static_settings(void)
{
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
@ -154,15 +154,15 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong ap, cr;
printf("\nEBC registers for PPC405GP:\n");
mfebc(pb0ap, ap); mfebc(pb0cr, cr);
mfebc(PB0AP, ap); mfebc(PB0CR, cr);
printf("0: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb1ap, ap); mfebc(pb1cr, cr);
mfebc(PB1AP, ap); mfebc(PB1CR, cr);
printf("1: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb2ap, ap); mfebc(pb2cr, cr);
mfebc(PB2AP, ap); mfebc(PB2CR, cr);
printf("2: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb3ap, ap); mfebc(pb3cr, cr);
mfebc(PB3AP, ap); mfebc(PB3CR, cr);
printf("3: AP=%08lx CP=%08lx\n", ap, cr);
mfebc(pb4ap, ap); mfebc(pb4cr, cr);
mfebc(PB4AP, ap); mfebc(PB4CR, cr);
printf("4: AP=%08lx CP=%08lx\n", ap, cr);
printf("\n");

2
board/gdsys/dlvision/dlvision.c
Unescape View File

@ -48,7 +48,7 @@ int board_early_init_f(void)
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* setup io-latches

52
board/gdsys/gdppc440etx/gdppc440etx.c
Unescape View File

@ -42,8 +42,8 @@ int board_early_init_f(void)
/*
* Setup the external bus controller/chip selects
*/
mfebc(xbcfg, reg);
mtebc(xbcfg, reg | 0x04000000); /* Set ATC */
mfebc(EBC0_CFG, reg);
mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */
/*
* Setup the GPIO pins
@ -102,10 +102,10 @@ int board_early_init_f(void)
/*
* Setup other serial configuration
*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
return 0;
}
@ -117,7 +117,7 @@ int misc_init_r(void)
uint sz;
/* Re-do sizing to get full correct info */
mfebc(pb0cr, pbcr);
mfebc(PB0CR, pbcr);
if (gd->bd->bi_flashsize > 0x08000000)
panic("Max. flash banksize is 128 MB!\n");
@ -127,7 +127,7 @@ int misc_init_r(void)
sz <<= 1;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(pb0cr, pbcr);
mtebc(PB0CR, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -178,35 +178,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
/* enable 66 MHz ext. Clock */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);

0
board/gdsys/compactcenter/Makefile → board/gdsys/intip/Makefile
Unescape View File

0
board/gdsys/compactcenter/chip_config.c → board/gdsys/intip/chip_config.c
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0
board/gdsys/compactcenter/config.mk → board/gdsys/intip/config.mk
Unescape View File

0
board/gdsys/compactcenter/init.S → board/gdsys/intip/init.S
Unescape View File

4
board/gdsys/compactcenter/compactcenter.c → board/gdsys/intip/intip.c
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@ -129,7 +129,7 @@ int checkboard(void)
#ifdef CONFIG_DEVCONCENTER
printf("Board: DevCon-Center");
#else
printf("Board: CompactCenter");
printf("Board: Intip");
#endif
if (s != NULL) {
@ -215,7 +215,7 @@ int board_early_init_r(void)
EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
| bxcr_bw
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_16BIT);

2
board/gdsys/compactcenter/u-boot.lds → board/gdsys/intip/u-boot.lds
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@ -66,7 +66,7 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/gdsys/compactcenter/init.o (.text)
board/gdsys/intip/init.o (.text)
*(.text)
*(.fixup)

2
board/gdsys/neo/neo.c
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@ -43,7 +43,7 @@ int board_early_init_f(void)
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}

14
board/jse/init.S
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@ -52,8 +52,6 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#define cpc0_cr0 0xB1
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
@ -84,16 +82,16 @@ ext_bus_cntlr_init:
/* Memory Bank 0 (Flash) initialization */
/*----------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
blr

8
board/jse/jse.c
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@ -62,12 +62,12 @@ int board_early_init_f (void)
/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, 0x01011000);
mtdcr (EBC0_CFGADDR, PB1AP);
mtdcr (EBC0_CFGDATA, 0x01011000);
/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
/* CPC0_CR1 |= PCIPW */

80
board/jse/sdram.c
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@ -35,60 +35,60 @@ phys_size_t initdram (int board_type)
/* Configure the SDRAMS */
/* disable memory controller */
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, 0x00000000);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtdcr (memcfga, mem_besra);
mtdcr (memcfgd, 0xffffffff);
mtdcr (SDRAM0_CFGADDR, mem_besra);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtdcr (memcfga, mem_besrb);
mtdcr (memcfgd, 0xffffffff);
mtdcr (SDRAM0_CFGADDR, mem_besrb);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
mtdcr (memcfga, mem_ecccf);
mtdcr (memcfgd, 0x00000000);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtdcr (memcfga, mem_eccerr);
mtdcr (memcfgd, 0xffffffff);
mtdcr (SDRAM0_CFGADDR, mem_eccerr);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, 0x010a4016);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGDATA, 0x010a4016);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
mtdcr (memcfga, mem_mb0cf);
mtdcr (memcfgd, 0x00084001);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGDATA, 0x00084001);
/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
mtdcr (memcfga, mem_mb1cf);
mtdcr (memcfgd, 0x04084001);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGDATA, 0x04084001);
/* Memory Bank 2 Config == BE=0 */
mtdcr (memcfga, mem_mb2cf);
mtdcr (memcfgd, 0x00000000);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Memory Bank 3 Config == BE=0 */
mtdcr (memcfga, mem_mb3cf);
mtdcr (memcfgd, 0x00000000);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* refresh timer = 0x400 */
mtdcr (memcfga, mem_rtr);
mtdcr (memcfgd, 0x04000000);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGDATA, 0x04000000);
/* Power management idle timer set to the default. */
mtdcr (memcfga, mem_pmit);
mtdcr (memcfgd, 0x07c00000);
mtdcr (SDRAM0_CFGADDR, mem_pmit);
mtdcr (SDRAM0_CFGDATA, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, 0x80e00000);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, 0x80e00000);
return SDRAM_LEN;
}
@ -108,28 +108,28 @@ int testdram (void)
#ifdef DEBUG
printf ("SDRAM Controller Registers --\n");
mtdcr (memcfga, mem_mcopt1);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_CFG : 0x%08x\n", val);
mtdcr (memcfga, 0x24);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, 0x24);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_STATUS: 0x%08x\n", val);
mtdcr (memcfga, mem_mb0cf);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B0CR : 0x%08x\n", val);
mtdcr (memcfga, mem_mb1cf);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B1CR : 0x%08x\n", val);
mtdcr (memcfga, mem_sdtr1);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_TR : 0x%08x\n", val);
mtdcr (memcfga, mem_rtr);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_RTR : 0x%08x\n", val);
#endif
@ -137,8 +137,8 @@ int testdram (void)
bit. Really, there should already have been plenty of time,
given it was started long ago. But, best to check. */
for (idx = 0; idx < 1000000; idx += 1) {
mtdcr (memcfga, 0x24);
val = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, 0x24);
val = mfdcr (SDRAM0_CFGDATA);
if (val & 0x80000000)
break;
}

64
board/korat/korat.c
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@ -81,8 +81,8 @@ int board_early_init_f(void)
korat_buzzer(0);
#endif
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the interrupt controller polarities, triggers, etc.
@ -157,8 +157,8 @@ int board_early_init_f(void)
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg);
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg);
return 0;
}
@ -359,12 +359,12 @@ int misc_init_r(void)
gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
gd->bd->bi_flashoffset = 0;
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(flash1_size) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB1CR);
mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
@ -378,12 +378,12 @@ int misc_init_r(void)
gd->bd->bi_flashoffset =
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB1CR);
mtdcr(EBC0_CFGDATA, pbcr);
/* Monitor protection ON by default */
#if defined(CONFIG_KORAT_PERMANENT)
@ -552,8 +552,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
set_serial_number();
set_mac_addresses();
@ -620,35 +620,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
#if defined(CONFIG_PCI_PNP)
hose->fixup_irq = korat_pci_fixup_irq;

52
board/lwmon5/lwmon5.c
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@ -38,8 +38,8 @@ int board_early_init_f(void)
u32 reg;
/* PLB Write pipelining disabled. Denali Core workaround */
mtdcr(plb0_acr, 0xDE000000);
mtdcr(plb1_acr, 0xDE000000);
mtdcr(PLB0_ACR, 0xDE000000);
mtdcr(PLB1_ACR, 0xDE000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@ -90,9 +90,9 @@ int board_early_init_f(void)
/* PCI arbiter disabled */
/* PCI Host Configuration disbaled */
mfsdr(sdr_pci0, reg);
mfsdr(SDR0_PCI0, reg);
reg = 0;
mtsdr(sdr_pci0, 0x00000000 | reg);
mtsdr(SDR0_PCI0, 0x00000000 | reg);
gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
@ -157,7 +157,7 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mfebc(pb0cr, pbcr);
mfebc(PB0CR, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
@ -185,7 +185,7 @@ int misc_init_r(void)
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(pb0cr, pbcr);
mtebc(PB0CR, pbcr);
/*
* Re-check to get correct base address
@ -249,8 +249,8 @@ int misc_init_r(void)
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
mtdcr(PLB4_ACR, reg);
/*
* Init matrix keyboard
@ -296,35 +296,35 @@ int pci_pre_init(struct pci_controller *hose)
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}

58
board/mpl/common/flash.c
Unescape View File

@ -97,7 +97,7 @@ int get_boot_mode(void)
{
unsigned long pbcr;
int res = 0;
pbcr = mfdcr (strap);
pbcr = mfdcr (CPC0_PSR);
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
/* boot via MPS or MPS mapping */
res = BOOT_MPS;
@ -123,29 +123,29 @@ void setup_cs_reloc(void)
/* first findout on which cs the flash is */
if(mode & BOOT_MPS) {
/* map flash high on CS1 and MPS on CS0 */
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, MPS_CR);
mtdcr (EBC0_CFGADDR, PB0AP);
mtdcr (EBC0_CFGDATA, MPS_AP);
mtdcr (EBC0_CFGADDR, PB0CR);
mtdcr (EBC0_CFGDATA, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, FLASH_CR_B);
mtdcr (EBC0_CFGADDR, PB1AP);
mtdcr (EBC0_CFGDATA, FLASH_AP);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, FLASH_CR_B);
}
else {
/* map flash high on CS0 and MPS on CS1 */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, MPS_CR);
mtdcr (EBC0_CFGADDR, PB1AP);
mtdcr (EBC0_CFGDATA, MPS_AP);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, FLASH_CR_B);
mtdcr (EBC0_CFGADDR, PB0AP);
mtdcr (EBC0_CFGDATA, FLASH_AP);
mtdcr (EBC0_CFGADDR, PB0CR);
mtdcr (EBC0_CFGDATA, FLASH_CR_B);
}
}
@ -217,34 +217,34 @@ unsigned long flash_init (void)
}
if(mode & BOOT_MPS) {
/* flash is on CS1 */
mtdcr(ebccfga, pb1cr);
flashcr = mfdcr (ebccfgd);
mtdcr(EBC0_CFGADDR, PB1CR);
flashcr = mfdcr (EBC0_CFGDATA);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (i << 17); /* size addr */
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, flashcr);
mtdcr(EBC0_CFGADDR, PB1CR);
mtdcr(EBC0_CFGDATA, flashcr);
}
else {
/* flash is on CS0 */
mtdcr(ebccfga, pb0cr);
flashcr = mfdcr (ebccfgd);
mtdcr(EBC0_CFGADDR, PB0CR);
flashcr = mfdcr (EBC0_CFGDATA);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (i << 17); /* size addr */
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, flashcr);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, flashcr);
}
#if 0
/* enable this (PIP405/MIP405 only) if you want to test if
the relocation has be done ok.
This will disable both Chipselects */
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, 0L);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, 0L);
mtdcr (EBC0_CFGADDR, PB0CR);
mtdcr (EBC0_CFGDATA, 0L);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, 0L);
printf("CS0 & CS1 switched off for test\n");
#endif
/* patch version_string */

74
board/mpl/mip405/init.S
Unescape View File

@ -55,7 +55,7 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
mfdcr r3,strap /* get strapping reg */
mfdcr r3,CPC0_PSR /* get strapping reg */
andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
bnelr /* jump back if PCI boot */
@ -84,9 +84,9 @@ ext_bus_cntlr_init:
/*-----------------------------------------------------------------------
* decide boot up mode
*----------------------------------------------------------------------- */
addi r4,0,pb0cr
mtdcr ebccfga,r4
mfdcr r4,ebccfgd
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
mfdcr r4,EBC0_CFGDATA
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
@ -96,18 +96,18 @@ ext_bus_cntlr_init:
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
b 1f
0:
@ -117,66 +117,66 @@ ext_bus_cntlr_init:
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
1:
/*-----------------------------------------------------------------------
* Memory Bank 2-3-4-5-6 (not used) initialization
*-----------------------------------------------------------------------*/
addi r4,0,pb1cr
mtdcr ebccfga,r4
addi r4,0,PB1CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb2cr
mtdcr ebccfga,r4
addi r4,0,PB2CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb3cr
mtdcr ebccfga,r4
addi r4,0,PB3CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb4cr
mtdcr ebccfga,r4
addi r4,0,PB4CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb5cr
mtdcr ebccfga,r4
addi r4,0,PB5CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb6cr
mtdcr ebccfga,r4
addi r4,0,PB6CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb7cr
mtdcr ebccfga,r4
addi r4,0,PB7CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
nop /* pass2 DCR errata #8 */
blr

132
board/mpl/mip405/mip405.c
Unescape View File

@ -256,16 +256,16 @@ int init_sdram (void)
gd->baudrate = 9600;
serial_init ();
/* set up the pld */
mtdcr (ebccfga, pb7ap);
mtdcr (ebccfgd, PLD_AP);
mtdcr (ebccfga, pb7cr);
mtdcr (ebccfgd, PLD_CR);
mtdcr (EBC0_CFGADDR, PB7AP);
mtdcr (EBC0_CFGDATA, PLD_AP);
mtdcr (EBC0_CFGADDR, PB7CR);
mtdcr (EBC0_CFGDATA, PLD_CR);
/* THIS IS OBSOLETE */
/* set up the board rev reg*/
mtdcr (ebccfga, pb5ap);
mtdcr (ebccfgd, BOARD_AP);
mtdcr (ebccfga, pb5cr);
mtdcr (ebccfgd, BOARD_CR);
mtdcr (EBC0_CFGADDR, PB5AP);
mtdcr (EBC0_CFGDATA, BOARD_AP);
mtdcr (EBC0_CFGADDR, PB5CR);
mtdcr (EBC0_CFGDATA, BOARD_CR);
#ifdef SDRAM_DEBUG
/* get all informations from PLD */
serial_puts ("\nPLD Part 0x");
@ -289,30 +289,30 @@ int init_sdram (void)
SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
#endif
/* set-up the chipselect machine */
mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
tmp = mfdcr (ebccfgd);
mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
tmp = mfdcr (EBC0_CFGDATA);
if ((tmp & 0x00002000) == 0) {
/* MPS Boot, set up the flash */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, FLASH_CR);
mtdcr (EBC0_CFGADDR, PB1AP);
mtdcr (EBC0_CFGDATA, FLASH_AP);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, FLASH_CR);
} else {
/* Flash boot, set up the MPS */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, MPS_CR);
mtdcr (EBC0_CFGADDR, PB1AP);
mtdcr (EBC0_CFGDATA, MPS_AP);
mtdcr (EBC0_CFGADDR, PB1CR);
mtdcr (EBC0_CFGDATA, MPS_CR);
}
/* set up UART0 (CS2) and UART1 (CS3) */
mtdcr (ebccfga, pb2ap);
mtdcr (ebccfgd, UART0_AP);
mtdcr (ebccfga, pb2cr);
mtdcr (ebccfgd, UART0_CR);
mtdcr (ebccfga, pb3ap);
mtdcr (ebccfgd, UART1_AP);
mtdcr (ebccfga, pb3cr);
mtdcr (ebccfgd, UART1_CR);
mtdcr (EBC0_CFGADDR, PB2AP);
mtdcr (EBC0_CFGDATA, UART0_AP);
mtdcr (EBC0_CFGADDR, PB2CR);
mtdcr (EBC0_CFGDATA, UART0_CR);
mtdcr (EBC0_CFGADDR, PB3AP);
mtdcr (EBC0_CFGDATA, UART1_AP);
mtdcr (EBC0_CFGADDR, PB3CR);
mtdcr (EBC0_CFGDATA, UART1_CR);
bc = in8 (PLD_BOARD_CFG_REG);
#ifdef SDRAM_DEBUG
serial_puts ("\nstart SDRAM Setup\n");
@ -348,8 +348,8 @@ int init_sdram (void)
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
sdram_tim |= ((unsigned long) (cal_val)) << 23;
/* insert PTA value */
@ -369,8 +369,8 @@ int init_sdram (void)
/* insert SZ value; */
tmp |= ((unsigned long) sdram_table[i].sz << 17);
/* get SDRAM bank 0 register */
mtdcr (memcfga, mem_mb0cf);
sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
@ -380,8 +380,8 @@ int init_sdram (void)
#endif
/* write SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, sdram_tim);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGDATA, sdram_tim);
#ifdef SDRAM_DEBUG
serial_puts ("mb0cf: ");
@ -390,23 +390,23 @@ int init_sdram (void)
#endif
/* write SDRAM bank 0 register */
mtdcr (memcfga, mem_mb0cf);
mtdcr (memcfgd, sdram_bank);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGDATA, sdram_bank);
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
/* get SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
tmp = mfdcr (memcfgd) & ~0x3FF80000;
mtdcr (SDRAM0_CFGADDR, mem_rtr);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x07F00000;
} else {
/* get SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
tmp = mfdcr (memcfgd) & ~0x3FF80000;
mtdcr (SDRAM0_CFGADDR, mem_rtr);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x05F00000;
}
/* write SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
if (sdram_table[i].ecc) {
@ -415,19 +415,19 @@ int init_sdram (void)
#ifdef SDRAM_DEBUG
serial_puts ("disable ECC.. ");
#endif
mtdcr (memcfga, mem_ecccf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; /* disable all banks */
mtdcr (memcfga, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
/* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG
serial_puts ("setup SDRAM Controller.. ");
#endif
mtdcr (memcfgd, tmp);
mtdcr (memcfga, mem_mcopt1);
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGDATA, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
#ifdef SDRAM_DEBUG
serial_puts ("fill the memory..\n");
@ -447,19 +447,19 @@ int init_sdram (void)
serial_puts ("enable ECC\n");
#endif
udelay (400);
mtdcr (memcfga, mem_ecccf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; /* enable bank 0 */
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
} else
#endif
{
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (memcfga, mem_mcopt1);
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
}
serial_puts ("\n");
@ -631,14 +631,14 @@ phys_size_t initdram (int board_type)
ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the
bank registers */
mtdcr (memcfga, mem_mb0cf);
bank_reg[0] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb1cf);
bank_reg[1] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb2cf);
bank_reg[2] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb3cf);
bank_reg[3] = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
if ((bank_reg[i] & 0x1) == 0x1) {
@ -648,8 +648,8 @@ phys_size_t initdram (int board_type)
} else
ds = 1;
}
mtdcr (memcfga, mem_ecccf);
tmp = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
tmp = mfdcr (SDRAM0_CFGDATA);
if (!tmp)
printf ("No ");
@ -687,7 +687,7 @@ int misc_init_r (void)
rtc_get (&tm);
start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);

74
board/mpl/pip405/init.S
Unescape View File

@ -54,7 +54,7 @@
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
mfdcr r3,strap /* get strapping reg */
mfdcr r3,CPC0_PSR /* get strapping reg */
andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
bnelr /* jump back if PCI boot */
@ -83,9 +83,9 @@
/*-----------------------------------------------------------------------
* decide boot up mode
*----------------------------------------------------------------------- */
addi r4,0,pb0cr
mtdcr ebccfga,r4
mfdcr r4,ebccfgd
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
mfdcr r4,EBC0_CFGDATA
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
@ -95,18 +95,18 @@
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
b 1f
0:
@ -115,65 +115,65 @@
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addi r4,0,PB1AP
mtdcr EBC0_CFGADDR,r4
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
addi r4,0,PB0CR
mtdcr EBC0_CFGADDR,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
1:
/*-----------------------------------------------------------------------
* Memory Bank 2-3-4-5-6 (not used) initialization
*-----------------------------------------------------------------------*/
addi r4,0,pb1cr
mtdcr ebccfga,r4
addi r4,0,PB1CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb2cr
mtdcr ebccfga,r4
addi r4,0,PB2CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb3cr
mtdcr ebccfga,r4
addi r4,0,PB3CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb4cr
mtdcr ebccfga,r4
addi r4,0,PB4CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb5cr
mtdcr ebccfga,r4
addi r4,0,PB5CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb6cr
mtdcr ebccfga,r4
addi r4,0,PB6CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
addi r4,0,pb7cr
mtdcr ebccfga,r4
addi r4,0,PB7CR
mtdcr EBC0_CFGADDR,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
mtdcr EBC0_CFGDATA,r4
nop /* pass2 DCR errata #8 */
blr

82
board/mpl/pip405/pip405.c
Unescape View File

@ -193,10 +193,10 @@ int board_early_init_f (void)
unsigned char cal_index, cal_val, spd_version, spd_chksum;
unsigned char buf[8];
/* set up the config port */
mtdcr (ebccfga, pb7ap);
mtdcr (ebccfgd, CONFIG_PORT_AP);
mtdcr (ebccfga, pb7cr);
mtdcr (ebccfgd, CONFIG_PORT_CR);
mtdcr (EBC0_CFGADDR, PB7AP);
mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
mtdcr (EBC0_CFGADDR, PB7CR);
mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
memclk = get_bus_freq (tmemclk);
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
@ -361,8 +361,8 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
/* get SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
tmp = mfdcr (memcfgd) & ~0x018FC01F;
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
/* tmp |= ((unsigned long)cal_val) << 23; */
tmp |= ((unsigned long) cal_val) << 23;
@ -385,8 +385,8 @@ int board_early_init_f (void)
#endif
/* write SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGDATA, tmp);
baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
/* insert AM value */
@ -418,8 +418,8 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
} /* endswitch */
/* get SDRAM bank 0 register */
mtdcr (memcfga, mem_mb0cf);
bank = mfdcr (memcfgd) & ~0xFFCEE001;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
serial_puts ("bank0: baseaddr: ");
@ -434,12 +434,12 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 0 register */
mtdcr (memcfga, mem_mb0cf);
mtdcr (memcfgd, bank);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 1 register */
mtdcr (memcfga, mem_mb1cf);
bank = mfdcr (memcfgd) & ~0xFFCEE001;
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_size = 0;
#ifdef SDRAM_DEBUG
@ -459,12 +459,12 @@ int board_early_init_f (void)
serial_puts ("\n");
#endif
/* write SDRAM bank 1 register */
mtdcr (memcfga, mem_mb1cf);
mtdcr (memcfgd, bank);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 2 register */
mtdcr (memcfga, mem_mb2cf);
bank = mfdcr (memcfgd) & ~0xFFCEE001;
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
@ -482,12 +482,12 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 2 register */
mtdcr (memcfga, mem_mb2cf);
mtdcr (memcfgd, bank);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 3 register */
mtdcr (memcfga, mem_mb3cf);
bank = mfdcr (memcfgd) & ~0xFFCEE001;
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
#ifdef SDRAM_DEBUG
serial_puts ("bank3: baseaddr: ");
@ -509,13 +509,13 @@ int board_early_init_f (void)
#endif
/* write SDRAM bank 3 register */
mtdcr (memcfga, mem_mb3cf);
mtdcr (memcfgd, bank);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
tmp = mfdcr (memcfgd) & ~0x3FF80000;
mtdcr (SDRAM0_CFGADDR, mem_rtr);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
if (tmemclk < NSto10PS (16))
tmp |= 0x05F00000;
@ -523,14 +523,14 @@ int board_early_init_f (void)
tmp |= 0x03F80000;
/* write SDRAM refresh interval register */
mtdcr (memcfga, mem_rtr);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (memcfga, mem_mcopt1);
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGDATA, tmp);
/*-------------------------------------------------------------------------+
@ -619,14 +619,14 @@ phys_size_t initdram (int board_type)
/* since the DRAM controller is allready set up,
* calculate the size with the bank registers
*/
mtdcr (memcfga, mem_mb0cf);
bank_reg[0] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb1cf);
bank_reg[1] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb2cf);
bank_reg[2] = mfdcr (memcfgd);
mtdcr (memcfga, mem_mb3cf);
bank_reg[3] = mfdcr (memcfgd);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
if ((bank_reg[i] & 0x1) == 0x1) {
@ -668,7 +668,7 @@ int misc_init_r (void)
gd->bd->bi_flashoffset=0;
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);

2
board/netstal/hcu4/hcu4.c
Unescape View File

@ -92,7 +92,7 @@ int checkboard (void)
u16 index = boardVersReg & 0x0f;
/* Cannot be done in board_early_init */
mtdcr(cntrl0, CPC0_CR0_VALUE);
mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
/* Force /RTS to active. The board it not wired quite
* correctly to use cts/rtc flow control, so just force the

30
board/netstal/hcu5/hcu5.c
Unescape View File

@ -94,8 +94,8 @@ int board_early_init_f(void)
}
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
#endif
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the GPIO pins
@ -152,8 +152,8 @@ int board_early_init_f(void)
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
/* setup BOOT FLASH */
mtsdr(SDR0_CUST0, 0xC0082350);
@ -324,7 +324,7 @@ int board_with_pci(void)
{
u32 reg;
mfsdr(sdr_pci0, reg);
mfsdr(SDR0_PCI0, reg);
return (reg & SDR0_XCR_PAE_MASK);
}
@ -350,28 +350,28 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr); /* Sequoia */
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr); /* Sequoia */
/*
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
* Workaround: Disable write pipelining to DDR SDRAM by setting
* PLB0_ACR[WRP] = 0.
*/
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
return board_with_pci();
}

4
board/netstal/hcu5/sdram.c
Unescape View File

@ -89,11 +89,11 @@ static int wait_for_dlllock(void)
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(memcfga, DDR0_17);
mtdcr(SDRAM0_CFGADDR, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(memcfgd);
val = mfdcr(SDRAM0_CFGDATA);
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */

6
board/netstal/mcu25/mcu25.c
Unescape View File

@ -71,8 +71,8 @@ int board_early_init_f (void)
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(cntrl1, CPC0_CR1_VALUE);
mtdcr(ecr, 0x60606000);
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
mtdcr(CPC0_ECR, 0x60606000);
mtdcr(CPC0_EIRR, 0x7C000000);
out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
@ -103,7 +103,7 @@ int checkboard (void)
u16 index = boardVersReg & 0xf0;
/* Cannot be done in board_early_init */
mtdcr(cntrl0, CPC0_CR0_VALUE);
mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
/* Force /RTS to active. The board it not wired quite
* correctly to use cts/rtc flow control, so just force the

58
board/pcs440ep/pcs440ep.c
Unescape View File

@ -143,9 +143,9 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
* GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
@ -174,10 +174,10 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
return 0;
}
@ -444,8 +444,8 @@ int misc_init_r (void)
load_ethaddr();
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
@ -473,8 +473,8 @@ int misc_init_r (void)
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -571,35 +571,35 @@ int pci_pre_init(struct pci_controller *hose)
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}

6
board/prodrive/alpr/alpr.c
Unescape View File

@ -39,7 +39,7 @@ int board_early_init_f (void)
/*-------------------------------------------------------------------------
* Initialize EBC CONFIG
*-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
@ -96,7 +96,7 @@ int board_early_init_f (void)
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
/* Setup GPIO/IRQ multiplexing */
mtsdr(sdr_pfc0, 0x01a33e00);
mtsdr(SDR0_PFC0, 0x01a33e00);
return 0;
}
@ -165,7 +165,7 @@ int pci_pre_init(struct pci_controller * hose )
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;

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