Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
Vaibhav Hiremath
15 years ago
committed by
Tom
parent
d11212e377
commit
cae377b59a
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/*
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* Functions related to OMAP3 SDRC. |
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* |
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* This file has been created after exctracting and consolidating |
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* the SDRC related content from mem.c and board.c, also created |
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* generic init function (mem_init). |
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* |
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* Copyright (C) 2004-2010 |
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* Texas Instruments Incorporated - http://www.ti.com/
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* |
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* Author : |
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* Vaibhav Hiremath <hvaibhav@ti.com> |
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* |
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* Original implementation by (mem.c, board.c) : |
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* Sunil Kumar <sunilsaini05@gmail.com> |
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* Shashi Ranjan <shashiranjanmca05@gmail.com> |
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* Manikandan Pillai <mani.pillai@ti.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/sys_proto.h> |
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extern omap3_sysinfo sysinfo; |
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; |
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/*
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* is_mem_sdr - |
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* - Return 1 if mem type in use is SDR |
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*/ |
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u32 is_mem_sdr(void) |
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{ |
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if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) |
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return 1; |
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return 0; |
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} |
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/*
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* make_cs1_contiguous - |
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* - For es2 and above remap cs1 behind cs0 to allow command line |
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* mem=xyz use all memory with out discontinuous support compiled in. |
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* Could do it at the ATAG, but there really is two banks... |
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* - Called as part of 2nd phase DDR init. |
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*/ |
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void make_cs1_contiguous(void) |
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{ |
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u32 size, a_add_low, a_add_high; |
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size = get_sdr_cs_size(CS0); |
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size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ |
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a_add_high = (size & 3) << 8; /* set up low field */ |
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a_add_low = (size & 0x3C) >> 2; /* set up high field */ |
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writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); |
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} |
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/*
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* get_sdr_cs_size - |
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* - Get size of chip select 0/1 |
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*/ |
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u32 get_sdr_cs_size(u32 cs) |
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{ |
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u32 size; |
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/* get ram size field */ |
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size = readl(&sdrc_base->cs[cs].mcfg) >> 8; |
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size &= 0x3FF; /* remove unwanted bits */ |
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size <<= 21; /* multiply by 2 MiB to find size in MB */ |
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return size; |
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} |
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/*
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* get_sdr_cs_offset - |
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* - Get offset of cs from cs0 start |
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*/ |
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u32 get_sdr_cs_offset(u32 cs) |
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{ |
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u32 offset; |
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if (!cs) |
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return 0; |
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offset = readl(&sdrc_base->cs_cfg); |
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offset = (offset & 15) << 27 | (offset & 0x30) >> 17; |
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return offset; |
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} |
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/*
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* do_sdrc_init - |
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* - Initialize the SDRAM for use. |
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* - Sets up SDRC timings for CS0 |
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* - code called once in C-Stack only context for CS0 and a possible 2nd |
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* time depending on memory configuration from stack+global context |
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*/ |
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void do_sdrc_init(u32 cs, u32 early) |
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{ |
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struct sdrc_actim *sdrc_actim_base; |
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if (cs) |
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; |
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else |
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; |
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if (early) { |
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/* reset sdrc controller */ |
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writel(SOFTRESET, &sdrc_base->sysconfig); |
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wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, |
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12000000); |
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writel(0, &sdrc_base->sysconfig); |
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/* setup sdrc to ball mux */ |
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writel(SDRC_SHARING, &sdrc_base->sharing); |
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/* Disable Power Down of CKE cuz of 1 CKE on combo part */ |
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writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, |
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&sdrc_base->power); |
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writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); |
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sdelay(0x20000); |
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} |
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writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | |
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RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | |
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DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); |
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writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); |
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writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); |
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writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); |
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writel(CMD_NOP, &sdrc_base->cs[cs].manual); |
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writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); |
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); |
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); |
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/*
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* CAS latency 3, Write Burst = Read Burst, Serial Mode, |
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* Burst length = 4 |
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*/ |
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writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); |
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if (!mem_ok(cs)) |
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writel(0, &sdrc_base->cs[cs].mcfg); |
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} |
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/*
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* dram_init - |
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* - Sets uboots idea of sdram size |
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*/ |
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int dram_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned int size0 = 0, size1 = 0; |
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size0 = get_sdr_cs_size(CS0); |
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/*
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* If a second bank of DDR is attached to CS1 this is |
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* where it can be started. Early init code will init |
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* memory on CS0. |
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*/ |
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if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { |
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do_sdrc_init(CS1, NOT_EARLY); |
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make_cs1_contiguous(); |
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size1 = get_sdr_cs_size(CS1); |
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} |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = size0; |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); |
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gd->bd->bi_dram[1].size = size1; |
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return 0; |
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} |
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/*
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* mem_init - |
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* - Init the sdrc chip, |
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* - Selects CS0 and CS1, |
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*/ |
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void mem_init(void) |
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{ |
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/* only init up first bank here */ |
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do_sdrc_init(CS0, EARLY_INIT); |
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} |
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