Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>master
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/*
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* Copyright (C) 2018 Microhip / Atmel Corporation |
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* Wenyou.Yang <wenyou.yang@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm/device.h> |
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#include <linux/io.h> |
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#include <mach/at91_pmc.h> |
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#include "pmc.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define AT91_USB_CLK_SOURCE_MAX 2 |
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#define AT91_USB_CLK_MAX_DIV 15 |
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struct at91_usb_clk_priv { |
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u32 num_clksource; |
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}; |
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static ulong at91_usb_clk_get_rate(struct clk *clk) |
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{ |
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struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
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struct at91_pmc *pmc = plat->reg_base; |
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struct clk source; |
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u32 tmp, usbdiv; |
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u8 source_index; |
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int ret; |
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tmp = readl(&pmc->pcr); |
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source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) & |
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AT91_PMC_USB_USBS_MASK; |
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usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK; |
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ret = clk_get_by_index(clk->dev, source_index, &source); |
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if (ret) |
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return 0; |
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return clk_get_rate(&source) / (usbdiv + 1); |
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} |
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static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
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struct at91_pmc *pmc = plat->reg_base; |
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struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev); |
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struct clk source, best_source; |
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ulong tmp_rate, best_rate = rate, source_rate; |
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int tmp_diff, best_diff = -1; |
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u32 div, best_div = 0; |
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u8 best_source_index = 0; |
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u8 i; |
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u32 tmp; |
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int ret; |
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for (i = 0; i < priv->num_clksource; i++) { |
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ret = clk_get_by_index(clk->dev, i, &source); |
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if (ret) |
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return ret; |
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source_rate = clk_get_rate(&source); |
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if (IS_ERR_VALUE(source_rate)) |
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return source_rate; |
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for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) { |
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tmp_rate = DIV_ROUND_CLOSEST(source_rate, div); |
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tmp_diff = abs(rate - tmp_rate); |
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if (best_diff < 0 || best_diff > tmp_diff) { |
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best_rate = tmp_rate; |
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best_diff = tmp_diff; |
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best_div = div - 1; |
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best_source = source; |
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best_source_index = i; |
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} |
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if (!best_diff || tmp_rate < rate) |
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break; |
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} |
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if (!best_diff) |
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break; |
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} |
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debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n", |
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best_source.dev->name, best_rate, best_div); |
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ret = clk_enable(&best_source); |
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if (ret) |
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return ret; |
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tmp = AT91_PMC_USB_USBS_(best_source_index) | |
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AT91_PMC_USB_DIV_(best_div); |
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writel(tmp, &pmc->usb); |
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return 0; |
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} |
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static struct clk_ops at91_usb_clk_ops = { |
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.get_rate = at91_usb_clk_get_rate, |
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.set_rate = at91_usb_clk_set_rate, |
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}; |
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static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct at91_usb_clk_priv *priv = dev_get_priv(dev); |
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u32 cells[AT91_USB_CLK_SOURCE_MAX]; |
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u32 num_clksource; |
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num_clksource = fdtdec_get_int_array_count(gd->fdt_blob, |
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dev_of_offset(dev), |
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"clocks", cells, |
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AT91_USB_CLK_SOURCE_MAX); |
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if (!num_clksource) |
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return -1; |
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priv->num_clksource = num_clksource; |
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return 0; |
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} |
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static int at91_usb_clk_probe(struct udevice *dev) |
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{ |
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return at91_pmc_core_probe(dev); |
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} |
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static const struct udevice_id at91_usb_clk_match[] = { |
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{ .compatible = "atmel,at91sam9x5-clk-usb" }, |
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{} |
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}; |
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U_BOOT_DRIVER(at91_usb_clk) = { |
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.name = "at91-usb-clk", |
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.id = UCLASS_CLK, |
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.of_match = at91_usb_clk_match, |
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.probe = at91_usb_clk_probe, |
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.ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata, |
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.priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv), |
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.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
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.ops = &at91_usb_clk_ops, |
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}; |
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