|
|
|
@ -51,6 +51,31 @@ void reset_cpu(ulong addr) |
|
|
|
|
{ |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int board_eth_init(bd_t *bis) |
|
|
|
|
{ |
|
|
|
|
u32 ret = 0; |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ZYNQ_GEM) |
|
|
|
|
# if defined(CONFIG_ZYNQ_GEM0) |
|
|
|
|
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, |
|
|
|
|
CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); |
|
|
|
|
# endif |
|
|
|
|
# if defined(CONFIG_ZYNQ_GEM1) |
|
|
|
|
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, |
|
|
|
|
CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); |
|
|
|
|
# endif |
|
|
|
|
# if defined(CONFIG_ZYNQ_GEM2) |
|
|
|
|
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, |
|
|
|
|
CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); |
|
|
|
|
# endif |
|
|
|
|
# if defined(CONFIG_ZYNQ_GEM3) |
|
|
|
|
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, |
|
|
|
|
CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); |
|
|
|
|
# endif |
|
|
|
|
#endif |
|
|
|
|
return ret; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_CMD_MMC |
|
|
|
|
int board_mmc_init(bd_t *bd) |
|
|
|
|
{ |
|
|
|
|