This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Syed Mohammed Khasim <sm.khasim@gmail.com> Acked-by: Marek Vasut <marex@denx.de>master
Masahiro Yamada
9 years ago
committed by
Tom Rini
parent
50b82c4b70
commit
cb957cda2b
@ -1,92 +0,0 @@ |
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Summary |
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======= |
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The README is for the boot procedure used for TI's OMAP-L138 based |
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hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB |
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DDR SDRAM along with a host of other controllers. |
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|
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The hawkboard is booted in three stages. The initial bootloader which |
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executes upon reset is the Rom Boot Loader(RBL) which sits in the |
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internal ROM of the omap. The RBL initialises the memory and the nand |
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controller, and copies the image stored at a predefined location(block |
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1) of the nand flash. The image loaded by the RBL to the memory is the |
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AIS signed spl image. This, in turns copies the u-boot binary from the |
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nand flash to the memory and jumps to the u-boot entry point. |
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|
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AIS is an image format defined by TI for the images that are to be |
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loaded to memory by the RBL. The image is divided into a series of |
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sections and the image's entry point is specified. Each section comes |
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with meta data like the target address the section is to be copied to |
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and the size of the section, which is used by the RBL to load the |
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image. At the end of the image the RBL jumps to the image entry |
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point. |
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|
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The secondary stage bootloader(spl) which is loaded by the RBL then |
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loads the u-boot from a predefined location in the nand to the memory |
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and jumps to the u-boot entry point. |
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|
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The reason a secondary stage bootloader is used is because the ECC |
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layout expected by the RBL is not the same as that used by |
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u-boot/linux. This also implies that for flashing the spl image,we |
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need to use the u-boot which uses the ECC layout expected by the |
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RBL[1]. Booting u-boot over UART(UART boot) is explained here[2]. |
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|
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|
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Compilation |
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=========== |
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Three images might be needed |
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|
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* spl - This is the secondary bootloader which boots the u-boot |
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binary. |
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|
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* u-boot binary - This is the image flashed to the nand and copied to |
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the memory by the spl. |
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|
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Both the images get compiled with hawkboard_config, with the TOPDIR |
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containing the u-boot images, and the spl image under the spl |
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directory. |
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|
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The spl image needs to be processed with the AISGen tool for |
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generating the AIS signed image to be flashed. Steps for generating |
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the AIS image are explained here[3]. |
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|
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* u-boot for uart boot - This is same as the u-boot binary generated |
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above, with the sole difference of the CONFIG_SYS_TEXT_BASE being |
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0xc1080000, as expected by the RBL. |
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|
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hawkboard_uart_config |
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|
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|
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Flashing the images to Nand |
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=========================== |
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The spl AIS image needs to be flashed to the block 1 of the Nand |
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flash, as that is the location the RBL expects the image[4]. For |
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flashing the spl, boot over the u-boot specified in [1], and flash the |
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image |
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|
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=> tftpboot 0xc0700000 <nand_spl_ais.bin> |
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=> nand erase 0x20000 0x20000 |
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=> nand write.e 0xc0700000 0x20000 <nand_spl_size> |
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|
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The u-boot binary is flashed at location 0xe0000(block 6) of the nand |
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flash. The spl loader expects the u-boot at this location. For |
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flashing the u-boot binary |
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|
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=> tftpboot 0xc0700000 u-boot.bin |
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=> nand erase 0xe0000 0x40000 |
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=> nand write.e 0xc0700000 0xe0000 <u-boot-size> |
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|
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|
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Links |
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===== |
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|
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[1] |
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http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin |
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|
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[2] |
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http://elinux.org/Hawkboard#Booting_u-boot_over_UART |
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|
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[3] |
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http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot |
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|
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[4] |
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http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks |
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@ -1,4 +0,0 @@ |
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# PLL0CFG0 PLL0CFG1 |
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PLL0 0x00180001 0x00000205 |
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# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC |
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DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000 |
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@ -1,120 +0,0 @@ |
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/*
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* Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org> |
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* |
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* Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com> |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* Copyright (C) 2004 Texas Instruments. |
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* Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>. |
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* |
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* ---------------------------------------------------------------------------- |
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* SPDX-License-Identifier: GPL-2.0+ |
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* ---------------------------------------------------------------------------- |
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*/ |
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|
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#include <common.h> |
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#include <asm/errno.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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#include <asm/arch/davinci_misc.h> |
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#include <asm/arch/pinmux_defs.h> |
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#include <asm/arch/da8xx-usb.h> |
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#include <ns16550.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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const struct pinmux_resource pinmuxes[] = { |
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PINMUX_ITEM(emac_pins_mii), |
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PINMUX_ITEM(emac_pins_mdio), |
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PINMUX_ITEM(emifa_pins_cs3), |
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PINMUX_ITEM(emifa_pins_cs4), |
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PINMUX_ITEM(emifa_pins_nand), |
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PINMUX_ITEM(uart2_pins_txrx), |
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PINMUX_ITEM(uart2_pins_rtscts), |
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}; |
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|
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes); |
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|
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const struct lpsc_resource lpsc[] = { |
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ |
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{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */ |
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{ DAVINCI_LPSC_EMAC }, /* image download */ |
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{ DAVINCI_LPSC_UART2 }, /* console */ |
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{ DAVINCI_LPSC_GPIO }, |
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}; |
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|
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const int lpsc_size = ARRAY_SIZE(lpsc); |
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|
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int board_init(void) |
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{ |
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/* arch number of the board */ |
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gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD; |
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|
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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return 0; |
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} |
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|
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int board_early_init_f(void) |
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{ |
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/*
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* Kick Registers need to be set to allow access to Pin Mux registers |
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*/ |
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writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); |
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writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); |
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|
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/* set cfgchip3 to select mii */ |
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writel(readl(&davinci_syscfg_regs->cfgchip3) & |
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~(1 << 8), &davinci_syscfg_regs->cfgchip3); |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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char buf[32]; |
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printf("ARM Clock : %s MHz\n", |
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strmhz(buf, clk_get(DAVINCI_ARM_CLKID))); |
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return 0; |
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} |
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int usb_phy_on(void) |
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{ |
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u32 timeout; |
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u32 cfgchip2; |
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cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); |
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cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | |
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CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ | |
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CFGCHIP2_USB1PHYCLKMUX); |
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cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | |
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CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX | |
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CFGCHIP2_USB1SUSPENDM; |
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writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); |
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/* wait until the usb phy pll locks */ |
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timeout = DA8XX_USB_OTG_TIMEOUT; |
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while (timeout--) |
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if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) |
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return 1; |
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/* USB phy was not turned on */ |
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return 0; |
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} |
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void usb_phy_off(void) |
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{ |
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u32 cfgchip2; |
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/*
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* Power down the on-chip PHY. |
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*/ |
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cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); |
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cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM); |
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cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET; |
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writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); |
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} |
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@ -1,69 +0,0 @@ |
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/* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* (C) Copyright 2008 |
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0xc1080000; |
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. = ALIGN(4); |
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.text : |
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{ |
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*(.vectors) |
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arch/arm/cpu/arm926ejs/start.o (.text*) |
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arch/arm/cpu/arm926ejs/built-in.o (.text*) |
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drivers/mtd/nand/built-in.o (.text*) |
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { *(.rodata*) } |
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. = ALIGN(4); |
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.data : { |
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*(.data) |
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__datarel_start = .; |
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*(.data.rel) |
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__datarelrolocal_start = .; |
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*(.data.rel.ro.local) |
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__datarellocal_start = .; |
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*(.data.rel.local) |
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__datarelro_start = .; |
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*(.data.rel.ro) |
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} |
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. = ALIGN(4); |
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__image_copy_end = .; |
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__rel_dyn_start = .; |
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__rel_dyn_end = .; |
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__got_start = .; |
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. = ALIGN(4); |
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.got : { *(.got) } |
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__got_end = .; |
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.bss : |
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{ |
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. = ALIGN(4); |
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__bss_start = .; |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_end = .; |
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} |
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.end : |
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{ |
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*(.__end) |
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} |
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} |
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@ -1,4 +0,0 @@ |
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CONFIG_SPL=y |
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+S:CONFIG_ARM=y |
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+S:CONFIG_ARCH_DAVINCI=y |
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+S:CONFIG_TARGET_HAWKBOARD=y |
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@ -1,5 +0,0 @@ |
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CONFIG_SPL=y |
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CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT" |
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+S:CONFIG_ARM=y |
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+S:CONFIG_ARCH_DAVINCI=y |
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+S:CONFIG_TARGET_HAWKBOARD=y |
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@ -1,220 +0,0 @@ |
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/*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* |
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* Based on davinci_dvevm.h. Original Copyrights follow: |
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* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* Board |
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*/ |
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#define CONFIG_SYS_USE_NAND 1 |
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|
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/*
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* SoC Configuration |
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*/ |
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#define CONFIG_MACH_DAVINCI_HAWK |
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
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#define CONFIG_SYS_OSCIN_FREQ 24000000 |
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg" |
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|
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2) |
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|
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#if defined(CONFIG_UART_U_BOOT) |
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#define CONFIG_SYS_TEXT_BASE 0xc1080000 |
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#elif !defined(CONFIG_SPL_BUILD) |
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#define CONFIG_SYS_TEXT_BASE 0xc1180000 |
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#endif |
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|
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/* Spl */ |
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#define CONFIG_SPL_FRAMEWORK |
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#define CONFIG_SPL_BOARD_INIT |
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#define CONFIG_SPL_NAND_SUPPORT |
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#define CONFIG_SPL_NAND_BASE |
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#define CONFIG_SPL_NAND_DRIVERS |
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#define CONFIG_SPL_NAND_ECC |
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#define CONFIG_SPL_NAND_SIMPLE |
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#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */ |
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#define CONFIG_SPL_SERIAL_SUPPORT |
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#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds" |
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#define CONFIG_SPL_TEXT_BASE 0xc1080000 |
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#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
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|
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/*
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* Memory Info |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */ |
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE |
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\ |
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_MONITOR_LEN 0x60000 |
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|
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/* memtest start addr */ |
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) |
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|
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/* memtest will be run on 16MB */ |
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) |
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|
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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|
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/*
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* Serial Driver info |
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*/ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE -4 |
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE |
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_BAUDRATE 115200 |
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|
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/*
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* Network & Ethernet Configuration |
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*/ |
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#define CONFIG_DRIVER_TI_EMAC |
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#define CONFIG_MII |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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#define CONFIG_NET_RETRY_COUNT 10 |
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|
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/*
|
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* Nand Flash |
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*/ |
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#ifdef CONFIG_SYS_USE_NAND |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_SIZE (128 << 10) |
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
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#define CONFIG_CLE_MASK 0x10 |
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#define CONFIG_ALE_MASK 0x8 |
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#define CONFIG_SYS_NAND_USE_FLASH_BBT |
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#define CONFIG_NAND_DAVINCI |
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */ |
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#define CFG_DAVINCI_STD_NAND_LAYOUT |
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#define CONFIG_SYS_NAND_CS 3 |
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#define CONFIG_SYS_NAND_PAGE_2K |
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/* Max number of NAND devices */ |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, } |
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/* Block 0--not used by bootcode */ |
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#define CONFIG_ENV_OFFSET 0x0 |
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|
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#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) |
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) |
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000 |
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000 |
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ |
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CONFIG_SYS_NAND_U_BOOT_SIZE - \
|
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CONFIG_SYS_MALLOC_LEN - \
|
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_NAND_ECCPOS { \ |
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24, 25, 26, 27, 28, \
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
|
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59, 60, 61, 62, 63 } |
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#define CONFIG_SYS_NAND_PAGE_COUNT 64 |
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
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#define CONFIG_SYS_NAND_ECCSIZE 512 |
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#define CONFIG_SYS_NAND_ECCBYTES 10 |
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#define CONFIG_SYS_NAND_OOBSIZE 64 |
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|
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#endif /* CONFIG_SYS_USE_NAND */ |
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|
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/* USB Configs */ |
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#define CONFIG_SYS_USB_OHCI_CPU_INIT |
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#define CONFIG_USB_OHCI_NEW |
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#define CONFIG_USB_OHCI_DA8XX |
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#define CONFIG_USB_STORAGE |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000 |
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard" |
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|
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/*
|
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* U-Boot general configuration |
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*/ |
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#define CONFIG_MISC_INIT_R |
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
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#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) |
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#define CONFIG_VERSION_VARIABLE |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
|
||||
/*
|
||||
* Linux Information |
||||
*/ |
||||
#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS \ |
||||
"mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
|
||||
"4M ip=static" |
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* U-Boot commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_CMD_EXT2 |
||||
|
||||
#ifdef CONFIG_CMD_BDI |
||||
#define CONFIG_CLOCKS |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_USE_NAND |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_NAND |
||||
#endif |
||||
|
||||
#ifndef CONFIG_DRIVER_TI_EMAC |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_DHCP |
||||
#undef CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_PING |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
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Reference in new issue