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rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK

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The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
master
Philipp Tomsich 7 years ago
parent 5f104178bf
commit cd401abcd5
1 changed files with 1 additions and 1 deletions
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  1. 2
      arch/arm/include/asm/arch-rockchip/cru_rk3128.h

2
arch/arm/include/asm/arch-rockchip/cru_rk3128.h
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@ -136,7 +136,7 @@ enum {
/* CRU_CLK_SEL2_CON */
NANDC_PLL_SEL_SHIFT = 14,
NANDC_PLL_SEL_MASK = 7 << NANDC_PLL_SEL_SHIFT,
NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
NANDC_PLL_SEL_CPLL = 0,
NANDC_PLL_SEL_GPLL,
NANDC_CLK_DIV_SHIFT = 8,

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