wdenk
23 years ago
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b6d12c1077
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ce23b153d8
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/*
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* (C) Copyright 2000-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
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#define CONFIG_R360MPI 1 |
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#define CONFIG_LCD |
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#undef CONFIG_EDT32F10 |
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#define CONFIG_SHARP_LQ057Q3DC02 |
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#define MPC8XX_FACT 1 /* Multiply by 1 */ |
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#define MPC8XX_XIN 50000000 /* 50 MHz in */ |
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#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */ |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ |
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#if 0 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_BOOTCOMMAND \ |
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm" |
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#undef CONFIG_SCC1_ENET |
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#define CONFIG_SCC2_ENET |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#if 0 |
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#ifdef CONFIG_LCD |
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# undef CONFIG_STATUS_LED /* disturbs display */ |
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#else |
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# define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
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#endif /* CONFIG_LCD */ |
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#endif |
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
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#define CONFIG_MAC_PARTITION |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
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#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ |
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#undef CONFIG_SORT_I2C /* To I2C with software support */ |
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#define CFG_I2C_SPEED 4700 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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/*
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* Software (bit-bang) I2C driver configuration |
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*/ |
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#define PB_SCL 0x00000020 /* PB 26 */ |
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#define PB_SDA 0x00000010 /* PB 27 */ |
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SDA |
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SCL |
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#define I2C_DELAY udelay(50) |
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#define CFG_I2C_PWM_ADDR 0x58 /* Power management coprocessor */ |
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#define CFG_I2C_KBD_ADDR 0x50 /* Keyboard coprocessor */ |
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#define CFG_I2C_TERM_ADDR 0x49 /* Temperature Sensors */ |
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_I2C | \
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CFG_CMD_IDE | \
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CFG_CMD_PCMCIA | \
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CFG_CMD_BSP ) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CFG_IMMR 0xFF000000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR CFG_IMMR |
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#define CFG_FLASH_BASE 0x40000000 |
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#if defined(DEBUG) |
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#else |
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
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#endif |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ |
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#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ |
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#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
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#else |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#ifndef CONFIG_CAN_DRIVER |
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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#else /* we must activate GPL5 in the SIUMCR for CAN */ |
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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#endif /* CONFIG_CAN_DRIVER */ |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27 |
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*----------------------------------------------------------------------- |
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*/ |
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* Reset PLL lock status sticky bit, timer expired status bit and timer |
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* interrupt status bit |
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* |
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
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*/ |
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
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#define CFG_PLPRCR \ |
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
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#else /* up to 50 MHz we use a 1:1 clock */ |
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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#endif /* CONFIG_80MHz */ |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CFG_SCCR (SCCR_TBS | \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* PCMCIA stuff |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
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*----------------------------------------------------------------------- |
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*/ |
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#if 1 |
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
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#undef CONFIG_IDE_LED /* LED for ide not supported */ |
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#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
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#define CFG_ATA_IDE0_OFFSET 0x0000 |
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
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/* Offset for data I/O */ |
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
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/* Offset for normal register accesses */ |
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
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/* Offset for alternate registers */ |
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#define CFG_ATA_ALT_OFFSET 0x0100 |
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#endif |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_DER 0x2002000F |
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/*#define CFG_DER 0*/ |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any) |
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* but not too much to meddle with FLASH accesses |
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*/ |
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
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#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ |
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/*
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* FLASH timing: |
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*/ |
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI) |
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
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/*
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* BR1 and OR1 (SDRAM) |
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* |
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*/ |
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#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ |
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
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#define CFG_PRELIM_OR1_AM 0xF8000000 /* OR addr mask */ |
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
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#define CFG_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \ |
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OR_SCY_0_CLK | OR_G5LS) |
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#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | CFG_OR_TIMING_SDRAM ) |
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#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
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/*
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* Memory Periodic Timer Prescaler |
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* |
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* The Divider for PTA (refresh timer) configuration is based on an |
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* example SDRAM configuration (64 MBit, one bank). The adjustment to |
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* the number of chip selects (NCS) and the actually needed refresh |
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* rate is done by setting MPTPR. |
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* |
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* PTA is calculated from |
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* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
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* |
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* gclk CPU clock (not bus clock!) |
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* Trefresh Refresh cycle * 4 (four word bursts used) |
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* |
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* 4096 Rows from SDRAM example configuration |
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* 1000 factor s -> ms |
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* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
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* 4 Number of refresh cycles per period |
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* 64 Refresh cycle in ms per number of rows |
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* -------------------------------------------- |
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
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* |
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* 50 MHz => 50.000.000 / Divider = 98 |
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* 66 Mhz => 66.000.000 / Divider = 129 |
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* 80 Mhz => 80.000.000 / Divider = 156 |
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*/ |
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#if defined(CONFIG_80MHz) |
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#define CFG_MAMR_PTA 156 |
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#elif defined(CONFIG_66MHz) |
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#define CFG_MAMR_PTA 129 |
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#else /* 50 MHz */ |
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#define CFG_MAMR_PTA 98 |
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#endif /*CONFIG_??MHz */ |
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|
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/*
|
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|
* For 16 MBit, refresh rates could be 31.3 us |
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|
* (= 64 ms / 2K = 125 / quad bursts). |
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* For a simpler initialization, 15.6 us is used instead. |
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* |
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* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
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* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
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|
*/ |
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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|
|
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|
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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|
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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|
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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|
|
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|
/*
|
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|
* MAMR settings for SDRAM |
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|
*/ |
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|
|
||||||
|
/* 8 column SDRAM */ |
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|
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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|
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||||
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||||
|
/* 9 column SDRAM */ |
||||||
|
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||||
|
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||||
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions |
||||||
|
* |
||||||
|
* Boot Flags |
||||||
|
*/ |
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue