Tom Rini
10 years ago
commit
cfa1bd0774
@ -0,0 +1,12 @@ |
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if TARGET_CM_T3517 |
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|
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config SYS_BOARD |
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default "cm_t3517" |
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|
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config SYS_VENDOR |
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default "compulab" |
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config SYS_CONFIG_NAME |
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default "cm_t3517" |
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endif |
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@ -0,0 +1,6 @@ |
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CM_T3517 BOARD |
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M: Igor Grinberg <grinberg@compulab.co.il> |
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S: Maintained |
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F: board/compulab/cm_t3517/ |
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F: include/configs/cm_t3517.h |
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F: configs/cm_t3517_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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#
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# Authors: Igor Grinberg <grinberg@compulab.co.il>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cm_t3517.o mux.o
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@ -0,0 +1,231 @@ |
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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
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* |
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* Authors: Igor Grinberg <grinberg@compulab.co.il> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <status_led.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <usb.h> |
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#include <mmc.h> |
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#include <linux/compiler.h> |
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#include <linux/usb/musb.h> |
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|
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/am35x_def.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/musb.h> |
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#include <asm/omap_musb.h> |
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#include <asm/ehci-omap.h> |
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#include "../common/common.h" |
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#include "../common/eeprom.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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const omap3_sysinfo sysinfo = { |
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DDR_DISCRETE, |
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"CM-T3517 board", |
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"NAND 128/512M", |
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}; |
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|
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#ifdef CONFIG_USB_MUSB_AM35X |
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static struct musb_hdrc_config cm_t3517_musb_config = { |
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.multipoint = 1, |
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.dyn_fifo = 1, |
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.num_eps = 16, |
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.ram_bits = 12, |
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}; |
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static struct omap_musb_board_data cm_t3517_musb_board_data = { |
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.set_phy_power = am35x_musb_phy_power, |
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.clear_irq = am35x_musb_clear_irq, |
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.reset = am35x_musb_reset, |
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}; |
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static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { |
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#if defined(CONFIG_MUSB_HOST) |
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.mode = MUSB_HOST, |
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#elif defined(CONFIG_MUSB_GADGET) |
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.mode = MUSB_PERIPHERAL, |
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#else |
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#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" |
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#endif |
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.config = &cm_t3517_musb_config, |
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.power = 250, |
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.platform_ops = &am35x_ops, |
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.board_data = &cm_t3517_musb_board_data, |
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}; |
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static void cm_t3517_musb_init(void) |
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{ |
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/*
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* Set up USB clock/mode in the DEVCONF2 register. |
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* USB2.0 PHY reference clock is 13 MHz |
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*/ |
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clrsetbits_le32(&am35x_scm_general_regs->devconf2, |
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CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, |
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CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | |
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CONF2_VBDTCTEN | CONF2_DATPOL); |
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if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, |
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(void *)AM35XX_IPSS_USBOTGSS_BASE)) |
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printf("Failed initializing AM35x MUSB!\n"); |
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} |
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#else |
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static inline void am3517_evm_musb_init(void) {} |
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#endif |
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int board_init(void) |
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{ |
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
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/* boot param addr */ |
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); |
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#endif |
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cm_t3517_musb_init(); |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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cl_print_pcb_info(); |
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dieid_num_r(); |
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return 0; |
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} |
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) |
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#define SB_T35_CD_GPIO 144 |
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#define SB_T35_WP_GPIO 59 |
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int board_mmc_init(bd_t *bis) |
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{ |
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return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); |
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} |
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#endif |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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#define CONTROL_EFUSE_EMAC_LSB 0x48002380 |
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#define CONTROL_EFUSE_EMAC_MSB 0x48002384 |
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static int am3517_get_efuse_enetaddr(u8 *enetaddr) |
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{ |
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u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); |
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u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); |
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enetaddr[0] = (u8)((msb >> 16) & 0xff); |
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enetaddr[1] = (u8)((msb >> 8) & 0xff); |
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enetaddr[2] = (u8)(msb & 0xff); |
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enetaddr[3] = (u8)((lsb >> 16) & 0xff); |
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enetaddr[4] = (u8)((lsb >> 8) & 0xff); |
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enetaddr[5] = (u8)(lsb & 0xff); |
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return is_valid_ether_addr(enetaddr); |
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} |
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static inline int cm_t3517_init_emac(bd_t *bis) |
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{ |
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int ret = cpu_eth_init(bis); |
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if (ret > 0) |
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return ret; |
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printf("Failed initializing EMAC! "); |
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return 0; |
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} |
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#else /* !CONFIG_DRIVER_TI_EMAC */ |
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static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } |
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static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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/*
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* Routine: handle_mac_address |
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* Description: prepare MAC address for on-board Ethernet. |
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*/ |
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static int cm_t3517_handle_mac_address(void) |
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{ |
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unsigned char enetaddr[6]; |
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int ret; |
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ret = eth_getenv_enetaddr("ethaddr", enetaddr); |
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if (ret) |
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return 0; |
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ret = cl_eeprom_read_mac_addr(enetaddr); |
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if (ret) { |
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ret = am3517_get_efuse_enetaddr(enetaddr); |
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if (ret) |
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return ret; |
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} |
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if (!is_valid_ether_addr(enetaddr)) |
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return -1; |
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return eth_setenv_enetaddr("ethaddr", enetaddr); |
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} |
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#define SB_T35_ETH_RST_GPIO 164 |
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/*
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* Routine: board_eth_init |
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* Description: initialize module and base-board Ethernet chips |
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*/ |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0, rc1 = 0; |
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rc1 = cm_t3517_handle_mac_address(); |
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if (rc1) |
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printf("No MAC address found! "); |
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rc1 = cm_t3517_init_emac(bis); |
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if (rc1 > 0) |
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rc++; |
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rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, |
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NULL, SB_T35_ETH_RST_GPIO); |
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if (rc1 > 0) |
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rc++; |
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return rc; |
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} |
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#ifdef CONFIG_USB_EHCI_OMAP |
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static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { |
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, |
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, |
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}; |
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#define CM_T3517_USB_HUB_RESET_GPIO 152 |
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#define SB_T35_USB_HUB_RESET_GPIO 98 |
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int ehci_hcd_init(int index, enum usb_init_type init, |
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struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
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{ |
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cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); |
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cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); |
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return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); |
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} |
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int ehci_hcd_stop(void) |
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{ |
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cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); |
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cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); |
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return omap_ehci_hcd_stop(); |
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} |
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#endif /* CONFIG_USB_EHCI_OMAP */ |
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@ -0,0 +1,236 @@ |
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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
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* |
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* Authors: Igor Grinberg <grinberg@compulab.co.il> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mux.h> |
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#include <asm/io.h> |
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void set_muxconf_regs(void) |
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{ |
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/* SDRC */ |
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); |
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/* GPMC */ |
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); |
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/* SB-T35 Ethernet */ |
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); |
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/* DVI enable */ |
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ |
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/* DataImage backlight */ |
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MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ |
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/* SB-T35 SD/MMC WP GPIO59 */ |
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MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ |
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); |
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/* SB-T35 Audio Enable GPIO61 */ |
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MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ |
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); |
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/* SB-T35 Ethernet IRQ GPIO65 */ |
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ |
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|
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/* UART3 Console */ |
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); |
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); |
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/* RTC V3020 nCS GPIO163 */ |
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ |
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/* SB-T35 Ethernet nRESET GPIO164 */ |
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ |
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|
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/* SB-T35 SD/MMC CD GPIO144 */ |
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MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ |
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/* WIFI nRESET GPIO145 */ |
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MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ |
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/* USB1 PHY Reset GPIO 146 */ |
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MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ |
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/* USB2 PHY Reset GPIO 147 */ |
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MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ |
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|
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/* MMC1 */ |
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); |
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); |
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); |
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|
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/* DSS */ |
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); |
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); |
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); |
||||
|
||||
/* I2C */ |
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); |
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); |
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); |
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); |
||||
|
||||
/* SB-T35 USB HUB Reset GPIO98 */ |
||||
MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ |
||||
/* CM-T3517 USB HUB Reset GPIO152 */ |
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ |
||||
|
||||
/* RMII */ |
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); |
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)); |
||||
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); |
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); |
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); |
||||
MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); |
||||
MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); |
||||
MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); |
||||
MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); |
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); |
||||
|
||||
/* Green LED GPIO186 */ |
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ |
||||
|
||||
/* SPI */ |
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ |
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ |
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ |
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ |
||||
/* LCD reset GPIO157 */ |
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ |
||||
|
||||
/* RTC V3020 CS Enable GPIO160 */ |
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ |
||||
/* SB-T35 LVDS Transmitter SHDN GPIO162 */ |
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ |
||||
|
||||
/* USB0 - mUSB */ |
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); |
||||
/* USB1 EHCI */ |
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ |
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ |
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ |
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ |
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ |
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ |
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ |
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ |
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ |
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ |
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ |
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ |
||||
/* USB2 EHCI */ |
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ |
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ |
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ |
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ |
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ |
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ |
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ |
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ |
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ |
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ |
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ |
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ |
||||
|
||||
/* SYS_BOOT */ |
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ |
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ |
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ |
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ |
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ |
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ |
||||
} |
||||
@ -0,0 +1,59 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/bootm.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
#include "common.h" |
||||
#include "eeprom.h" |
||||
|
||||
void cl_print_pcb_info(void) |
||||
{ |
||||
u32 board_rev = get_board_rev(); |
||||
u32 rev_major = board_rev / 100; |
||||
u32 rev_minor = board_rev - (rev_major * 100); |
||||
|
||||
if ((rev_minor / 10) * 10 == rev_minor) |
||||
rev_minor = rev_minor / 10; |
||||
|
||||
printf("PCB: %u.%u\n", rev_major, rev_minor); |
||||
} |
||||
|
||||
#ifdef CONFIG_SERIAL_TAG |
||||
void __weak get_board_serial(struct tag_serialnr *serialnr) |
||||
{ |
||||
/*
|
||||
* This corresponds to what happens when we can communicate with the |
||||
* eeprom but don't get a valid board serial value. |
||||
*/ |
||||
serialnr->low = 0; |
||||
serialnr->high = 0; |
||||
}; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_USB |
||||
int cl_usb_hub_init(int gpio, const char *label) |
||||
{ |
||||
if (gpio_request(gpio, label)) { |
||||
printf("Error: can't obtain GPIO%d for %s", gpio, label); |
||||
return -1; |
||||
} |
||||
|
||||
gpio_direction_output(gpio, 0); |
||||
udelay(10); |
||||
gpio_set_value(gpio, 1); |
||||
udelay(1000); |
||||
return 0; |
||||
} |
||||
|
||||
void cl_usb_hub_deinit(int gpio) |
||||
{ |
||||
gpio_free(gpio); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _CL_COMMON_ |
||||
#define _CL_COMMON_ |
||||
|
||||
#include <asm/errno.h> |
||||
|
||||
void cl_print_pcb_info(void); |
||||
|
||||
#ifdef CONFIG_CMD_USB |
||||
int cl_usb_hub_init(int gpio, const char *label); |
||||
void cl_usb_hub_deinit(int gpio); |
||||
#else /* !CONFIG_CMD_USB */ |
||||
static inline int cl_usb_hub_init(int gpio, const char *label) |
||||
{ |
||||
return -ENOSYS; |
||||
} |
||||
static inline void cl_usb_hub_deinit(int gpio) {} |
||||
#endif /* CONFIG_CMD_USB */ |
||||
|
||||
#ifdef CONFIG_SPLASH_SCREEN |
||||
int cl_splash_screen_prepare(int nand_offset); |
||||
#else /* !CONFIG_SPLASH_SCREEN */ |
||||
static inline int cl_splash_screen_prepare(int nand_offset) |
||||
{ |
||||
return -ENOSYS; |
||||
} |
||||
#endif /* CONFIG_SPLASH_SCREEN */ |
||||
|
||||
#ifdef CONFIG_SMC911X |
||||
int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, |
||||
int (*reset)(int), int rst_gpio); |
||||
#else /* !CONFIG_SMC911X */ |
||||
static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, |
||||
int (*reset)(int), int rst_gpio) |
||||
{ |
||||
return -ENOSYS; |
||||
} |
||||
#endif /* CONFIG_SMC911X */ |
||||
|
||||
#endif /* _CL_COMMON_ */ |
||||
@ -0,0 +1,93 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/mem.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
#include "common.h" |
||||
|
||||
static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { |
||||
NET_GPMC_CONFIG1, |
||||
NET_GPMC_CONFIG2, |
||||
NET_GPMC_CONFIG3, |
||||
NET_GPMC_CONFIG4, |
||||
NET_GPMC_CONFIG5, |
||||
NET_GPMC_CONFIG6, |
||||
0 |
||||
}; |
||||
|
||||
static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) |
||||
{ |
||||
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
||||
|
||||
enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, |
||||
&gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); |
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
||||
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
||||
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
||||
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
||||
&ctrl_base->gpmc_nadv_ale); |
||||
} |
||||
|
||||
#ifdef CONFIG_OMAP_GPIO |
||||
static int cl_omap3_smc911x_reset_net_chip(int gpio) |
||||
{ |
||||
int err; |
||||
|
||||
if (!gpio_is_valid(gpio)) |
||||
return -EINVAL; |
||||
|
||||
err = gpio_request(gpio, "eth rst"); |
||||
if (err) |
||||
return err; |
||||
|
||||
/* Set gpio as output and send a pulse */ |
||||
gpio_direction_output(gpio, 1); |
||||
udelay(1); |
||||
gpio_set_value(gpio, 0); |
||||
mdelay(40); |
||||
gpio_set_value(gpio, 1); |
||||
mdelay(1); |
||||
|
||||
return 0; |
||||
} |
||||
#else /* !CONFIG_OMAP_GPIO */ |
||||
static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } |
||||
#endif /* CONFIG_OMAP_GPIO */ |
||||
|
||||
int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, |
||||
int (*reset)(int), int rst_gpio) |
||||
{ |
||||
int ret; |
||||
|
||||
cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); |
||||
|
||||
if (reset) |
||||
reset(rst_gpio); |
||||
else |
||||
cl_omap3_smc911x_reset_net_chip(rst_gpio); |
||||
|
||||
ret = smc911x_initialize(id, base_addr); |
||||
if (ret > 0) |
||||
return ret; |
||||
|
||||
printf("Failed initializing SMC911x! "); |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,72 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <nand.h> |
||||
#include <bmp_layout.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) |
||||
{ |
||||
struct bmp_header *bmp_hdr; |
||||
int res; |
||||
size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); |
||||
|
||||
if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
res = nand_read_skip_bad(&nand_info[nand_curr_device], |
||||
nand_offset, &bmp_header_size, |
||||
NULL, nand_info[nand_curr_device].size, |
||||
(u_char *)bmp_load_addr); |
||||
if (res < 0) |
||||
return res; |
||||
|
||||
bmp_hdr = (struct bmp_header *)bmp_load_addr; |
||||
bmp_size = le32_to_cpu(bmp_hdr->file_size); |
||||
|
||||
if (bmp_load_addr + bmp_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
return nand_read_skip_bad(&nand_info[nand_curr_device], |
||||
nand_offset, &bmp_size, |
||||
NULL, nand_info[nand_curr_device].size, |
||||
(u_char *)bmp_load_addr); |
||||
|
||||
splash_address_too_high: |
||||
printf("Error: splashimage address too high. Data overwrites U-Boot " |
||||
"and/or placed beyond DRAM boundaries.\n"); |
||||
|
||||
return -1; |
||||
} |
||||
#else |
||||
static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) |
||||
{ |
||||
return -1; |
||||
} |
||||
#endif /* CONFIG_CMD_NAND */ |
||||
|
||||
int cl_splash_screen_prepare(int nand_offset) |
||||
{ |
||||
char *env_splashimage_value; |
||||
u32 bmp_load_addr; |
||||
|
||||
env_splashimage_value = getenv("splashimage"); |
||||
if (env_splashimage_value == NULL) |
||||
return -1; |
||||
|
||||
bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); |
||||
if (bmp_load_addr == 0) { |
||||
printf("Error: bad splashimage address specified\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return splash_load_from_nand(bmp_load_addr, nand_offset); |
||||
} |
||||
@ -1,5 +1,6 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR" |
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND" |
||||
CONFIG_CONS_INDEX=1 |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_AM335X_EVM=y |
||||
CONFIG_NOR=y |
||||
|
||||
@ -1,4 +1,5 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT" |
||||
CONFIG_CONS_INDEX=1 |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_AM335X_EVM=y |
||||
CONFIG_NOR=y |
||||
CONFIG_NOR_BOOT=y |
||||
|
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=n |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_OMAP34XX=y |
||||
+S:CONFIG_TARGET_CM_T3517=y |
||||
@ -0,0 +1,320 @@ |
||||
/*
|
||||
* (C) Copyright 2013 CompuLab, Ltd. |
||||
* Author: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* Configuration settings for the CompuLab CM-T3517 board |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_OMAP /* in a TI OMAP core */ |
||||
#define CONFIG_CM_T3517 /* working with CM-T3517 */ |
||||
#define CONFIG_OMAP_COMMON |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80008000 |
||||
|
||||
/*
|
||||
* This is needed for the DMA stuff. |
||||
* Although the default iss 64, we still define it |
||||
* to be on the safe side once the default is changed. |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 64 |
||||
|
||||
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */ |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/*
|
||||
* Display CPU and Board information |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
/*
|
||||
* The early kernel mapping on ARM currently only maps from the base of DRAM |
||||
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. |
||||
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, |
||||
* so that leaves DRAM base to DRAM base + 0x4000 available. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ 0x4000 |
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SERIAL_TAG |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 /* UART3 */ |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
||||
115200} |
||||
|
||||
#define CONFIG_OMAP_GPIO |
||||
|
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_OMAP_HSMMC |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_MUSB_AM35X |
||||
|
||||
#ifndef CONFIG_USB_MUSB_AM35X |
||||
#define CONFIG_USB_OMAP3 |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_OMAP |
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 |
||||
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 |
||||
#else /* !CONFIG_USB_MUSB_AM35X */ |
||||
#define CONFIG_MUSB_HOST |
||||
#define CONFIG_MUSB_PIO_ONLY |
||||
#endif /* CONFIG_USB_MUSB_AM35X */ |
||||
|
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_CMD_USB |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define MTDIDS_DEFAULT "nand0=nand" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ |
||||
"1920k(u-boot),256k(u-boot-env),"\
|
||||
"4m(kernel),-(fs)" |
||||
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_NAND /* NAND support */ |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_GPIO |
||||
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_OMAP34XX |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 0 |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
|
||||
/*
|
||||
* Board NAND Info. |
||||
*/ |
||||
#define CONFIG_SYS_NAND_QUIET_TEST |
||||
#define CONFIG_NAND_OMAP_GPMC |
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
||||
/* to access nand */ |
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
||||
/* to access nand at */ |
||||
/* CS0 */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
||||
/* devices */ |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loadaddr=0x82000000\0" \
|
||||
"baudrate=115200\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
"mpurate=auto\0" \
|
||||
"vram=12M\0" \
|
||||
"dvimode=1024x768MR-16@60\0" \
|
||||
"defaultdisplay=dvi\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
|
||||
"mmcrootfstype=ext4\0" \
|
||||
"nandroot=/dev/mtdblock4 rw\0" \
|
||||
"nandrootfstype=ubifs\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 2a0000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_TIMESTAMP |
||||
#define CONFIG_SYS_AUTOLOAD "no" |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT "CM-T3517 # " |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) |
||||
|
||||
/*
|
||||
* AM3517 has 12 GP timers, they can be driven by the system clock |
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
||||
* This rate is divided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define CONFIG_SYS_CS0_SIZE (256 << 20) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
/* **** PISMO SUPPORT *** */ |
||||
/* Monitor at start of flash */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
||||
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
||||
|
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
#define CONFIG_MII |
||||
#define CONFIG_SMC911X |
||||
#define CONFIG_SMC911X_32_BIT |
||||
#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
/* additions for new relocation code, must be added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/* Status LED */ |
||||
#define CONFIG_STATUS_LED /* Status LED enabled */ |
||||
#define CONFIG_BOARD_SPECIFIC_LED |
||||
#define CONFIG_GPIO_LED |
||||
#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ |
||||
#define GREEN_LED_DEV 0 |
||||
#define STATUS_LED_BIT GREEN_LED_GPIO |
||||
#define STATUS_LED_STATE STATUS_LED_ON |
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BOOT GREEN_LED_DEV |
||||
|
||||
/* GPIO banks */ |
||||
#ifdef CONFIG_STATUS_LED |
||||
#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ |
||||
#endif |
||||
|
||||
/* Display Configuration */ |
||||
#define CONFIG_OMAP3_GPIO_2 |
||||
#define CONFIG_OMAP3_GPIO_5 |
||||
#define CONFIG_VIDEO_OMAP3 |
||||
#define LCD_BPP LCD_COLOR16 |
||||
|
||||
#define CONFIG_LCD |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_SPLASHIMAGE_GUARD |
||||
#define CONFIG_CMD_BMP |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_SCF0403_LCD |
||||
|
||||
#define CONFIG_OMAP3_SPI |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue