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cpu/86xx fixes.

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Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
master
Jon Loeliger 17 years ago
parent 99c2fdab91
commit cfc7a7f5bb
6 changed files with 65 additions and 102 deletions
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  1. 4
      cpu/mpc86xx/cpu_init.c
  2. 51
      cpu/mpc86xx/interrupts.c
  3. 85
      cpu/mpc86xx/start.S
  4. 8
      cpu/mpc86xx/traps.c
  5. 16
      include/asm-ppc/immap_86xx.h
  6. 3
      include/asm-ppc/processor.h

4
cpu/mpc86xx/cpu_init.c
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@ -104,8 +104,8 @@ void cpu_init_f(void)
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
/* enable SYNCBE | ABE bits in HID1 */
set_hid1(get_hid1() | 0x00000C00);
/* enable EMCP, SYNCBE | ABE bits in HID1 */
set_hid1(get_hid1() | 0x80000C00);
}
/*

51
cpu/mpc86xx/interrupts.c
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@ -8,7 +8,7 @@
* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
* Xianghua Xiao (X.Xiao@motorola.com)
*
* (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
* (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -80,25 +80,10 @@ int interrupt_init(void)
{
int ret;
/*
* The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
* implement PEX10 errata. As INT is active high, it
* will cause core to take 0x500 interrupt.
*
* Due to the PIC's default pass through mode, as soon
* as interrupts are enabled (MSR[EE] = 1), an interrupt
* will be taken and u-boot will hang. This is due to a
* hardware change (per an errata fix) on new revisions
* of the board with Rev 2.x parts.
*
* Setting the PIC to mixed mode prevents the hang.
*/
if ((get_svr() & 0xf0) == 0x20) {
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_pic.gcr = MPC86xx_PICGCR_RST;
while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
}
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_pic.gcr = MPC86xx_PICGCR_RST;
while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
/* call cpu specific function from $(CPU)/interrupts.c */
ret = interrupt_init_cpu(&decrementer_count);
@ -119,6 +104,30 @@ int interrupt_init(void)
get_msr(),
get_dec());
#ifdef CONFIG_INTERRUPTS
volatile ccsr_pic_t *pic = &immr->im_pic;
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
#endif
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
#endif
pic->ctpr = 0; /* 40080 clear current task priority register */
#endif
return 0;
}
@ -158,8 +167,6 @@ void timer_interrupt(struct pt_regs *regs)
timestamp++;
ppcDcbf((unsigned long)&timestamp);
/* Restore Decrementer Count */
set_dec(decrementer_count);

85
cpu/mpc86xx/start.S
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@ -1,5 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2004, 2007 Freescale Semiconductor.
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@ -44,11 +44,9 @@
#define CONFIG_IDENT_STRING ""
#endif
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
/* Machine Check and Recoverable Interr. */
#define MSR_KERNEL ( MSR_ME | MSR_RI )
/*
* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
*/
/*
* Set up GOT: Global Offset Table
@ -195,17 +193,21 @@ boot_warm:
bl secondary_cpu_setup
#endif
1:
#ifdef CFG_RAMBOOT
/* disable everything */
1: li r0, 0
li r0, 0
mtspr HID0, r0
sync
mtmsr 0
#endif
bl invalidate_bats
sync
#ifdef CFG_L2
/* init the L2 cache */
addis r3, r0, L2_INIT@h
lis r3, L2_INIT@h
ori r3, r3, L2_INIT@l
mtspr l2cr, r3
/* invalidate the L2 cache */
@ -241,69 +243,9 @@ in_flash:
bl setup_ccsrbar
#endif
/* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
/* skip fixups if not Rev 1.0 */
mfspr r4, SVR
rlwinm r4,r4,0,24,31
cmpwi r4,0x10
bne 1f
lis r3,MCM_ABCR@ha
lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */
/* set ABCR[A_STRM_CNT] = 0 */
rlwinm r4,r4,0,0,29
/* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
addi r0,r0,1
rlwimi r4,r0,12,18,19
stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */
sync
/* Set DBCR[ERD_DIS] */
lis r3,MCM_DBCR@ha
lwz r4,MCM_DBCR@l(r3)
oris r4, r4, 0x4000
stw r4,MCM_DBCR@l(r3)
sync
1:
/* setup the law entries */
bl law_entry
sync
#if (EMULATOR_RUN == 1)
/* On the emulator we want to adjust these ASAP */
/* otherwise things are sloooow */
/* Setup OR0 (LALE FIX)*/
lis r3, CFG_CCSRBAR@h
ori r3, r3, 0x5004
li r4, 0x0FF3
stw r4, 0(r3)
sync
/* Setup LCRR */
lis r3, CFG_CCSRBAR@h
ori r3, r3, 0x50D4
lis r4, 0x8000
ori r4, r4, 0x0002
stw r4, 0(r3)
sync
#endif
#if 1
/* make sure timer enabled in guts register too */
lis r3, CFG_CCSRBAR@h
oris r3,r3, 0xE
ori r3,r3,0x0070
lwz r4, 0(r3)
lis r5,0xFFFC
ori r5,r5,0x5FFF
and r4,r4,r5
stw r4,0(r3)
#endif
/*
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
@ -346,8 +288,6 @@ in_flash:
#ifdef RUN_DIAG
/* Sri: Code to run the diagnostic automatically */
/* Load PX_AUX register address in r4 */
lis r4, 0xf810
ori r4, r4, 0x6
@ -392,6 +332,7 @@ diag_done:
.globl invalidate_bats
invalidate_bats:
li r0, 0
/* invalidate BATs */
mtspr IBAT0U, r0
mtspr IBAT1U, r0
@ -1040,6 +981,7 @@ trap_init:
mfmsr r7
li r8,MSR_IP
andc r7,r7,r8
ori r7,r7,MSR_ME /* Enable Machine Check */
mtmsr r7
mtlr r4 /* restore link register */
@ -1224,8 +1166,9 @@ secondary_cpu_setup:
sync
isync
/*SYNCBE|ABE in HID1*/
/* MCP|SYNCBE|ABE in HID1 */
mfspr r4, HID1
oris r4, r4, 0x8000
ori r4, r4, 0x0C00
mtspr HID1, r4
sync

8
cpu/mpc86xx/traps.c
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@ -130,8 +130,11 @@ MachineCheckException(struct pt_regs *regs)
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ", regs);
switch (regs->msr & 0x000F0000) {
case (0x80000000 >> 12):
switch ( regs->msr & 0x001F0000) {
case (0x80000000>>11):
printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
break;
case (0x80000000>>12):
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
@ -209,6 +212,7 @@ UnknownException(struct pt_regs *regs)
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
return;
#endif
printf("UnknownException regs@%x\n", regs);
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);

16
include/asm-ppc/immap_86xx.h
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@ -1257,9 +1257,12 @@ typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@ -1273,8 +1276,11 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCIEX1 0x80000000
#define MPC86xx_DEVDISR_PCIEX2 0x40000000
#define MPC86xx_DEVDISR_PCI1 0x80000000
#define MPC86xx_DEVDISR_PCIE1 0x40000000
#define MPC86xx_DEVDISR_PCIE2 0x20000000
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@ -1282,7 +1288,9 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
char res10[3416];
char res10a[1880];
uint clkdvdr; /* 0xe0800 - Clock Divide register */
char res10b[1532];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */

3
include/asm-ppc/processor.h
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@ -464,7 +464,8 @@
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
#define SPRN_MSSCRO 0x3f6
#define SPRN_MSSCR0 0x3f6
#define SPRN_MSSSR0 0x3f7
#endif

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