From d0a5023a356ff1ca98b800af61f338691234fbf6 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Fri, 25 May 2018 20:22:23 +0300 Subject: [PATCH] ARC: Cache: Don't compare I$ and D$ line lengths We don't care much about I$ line length really as there're no per-line ops on I$ instead we only do full invalidation of it on occasion of relocation and right before jumping to the OS. Also as compared to Linux kernel where we don't support different lengths of I$ and D$ lines in U-Boot we have to deal with such an exotic configs if the target board is not supposed to run Linux kernel. Signed-off-by: Alexey Brodkin --- arch/arc/lib/cache.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 6f52877..8c1cb6e 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -432,9 +432,16 @@ void read_decode_cache_bcr(void) int dc_line_sz = 0, ic_line_sz = 0; union bcr_di_cache ibcr, dbcr; + /* + * We don't care much about I$ line length really as there're + * no per-line ops on I$ instead we only do full invalidation of it + * on occasion of relocation and right before jumping to the OS. + * Still we check insane config with zero-encoded line length in + * presense of version field in I$ BCR. Just in case. + */ ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; + ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); } @@ -445,9 +452,6 @@ void read_decode_cache_bcr(void) if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); } - - if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) - panic("Instruction and data cache line lengths differ\n"); } void cache_init(void)