@ -68,6 +68,34 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL ( UART_PAD_CTRL ) ,
} ;
static iomux_v3_cfg_t const usdhc2_pads [ ] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
} ;
static iomux_v3_cfg_t const usdhc3_pads [ ] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
/* CD pin */
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL ( NO_PAD_CTRL ) ,
/* RST_B, used for power reset cycle */
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL ( NO_PAD_CTRL ) ,
} ;
static iomux_v3_cfg_t const usdhc4_pads [ ] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
@ -249,23 +277,84 @@ int board_early_init_f(void)
return 0 ;
}
static struct fsl_esdhc_cfg usdhc_cfg [ 1 ] = {
static struct fsl_esdhc_cfg usdhc_cfg [ 3 ] = {
{ USDHC2_BASE_ADDR , 0 , 4 } ,
{ USDHC3_BASE_ADDR } ,
{ USDHC4_BASE_ADDR } ,
} ;
# define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
# define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
# define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
int board_mmc_getcd ( struct mmc * mmc )
{
return 1 ; /* Assume boot SD always present */
struct fsl_esdhc_cfg * cfg = ( struct fsl_esdhc_cfg * ) mmc - > priv ;
int ret = 0 ;
switch ( cfg - > esdhc_base ) {
case USDHC2_BASE_ADDR :
ret = 1 ; /* Assume uSDHC2 is always present */
break ;
case USDHC3_BASE_ADDR :
ret = ! gpio_get_value ( USDHC3_CD_GPIO ) ;
break ;
case USDHC4_BASE_ADDR :
ret = ! gpio_get_value ( USDHC4_CD_GPIO ) ;
break ;
}
return ret ;
}
int board_mmc_init ( bd_t * bis )
{
imx_iomux_v3_setup_multiple_pads ( usdhc4_pads , ARRAY_SIZE ( usdhc4_pads ) ) ;
int i , ret ;
usdhc_cfg [ 0 ] . sdhc_clk = mxc_get_clock ( MXC_ESDHC4_CLK ) ;
return fsl_esdhc_initialize ( bis , & usdhc_cfg [ 0 ] ) ;
/*
* According to the board_mmc_init ( ) the following map is done :
* ( U - boot device node ) ( Physical Port )
* mmc0 USDHC2
* mmc1 USDHC3
* mmc2 USDHC4
*/
for ( i = 0 ; i < CONFIG_SYS_FSL_USDHC_NUM ; i + + ) {
switch ( i ) {
case 0 :
imx_iomux_v3_setup_multiple_pads (
usdhc2_pads , ARRAY_SIZE ( usdhc2_pads ) ) ;
usdhc_cfg [ 0 ] . sdhc_clk = mxc_get_clock ( MXC_ESDHC2_CLK ) ;
break ;
case 1 :
imx_iomux_v3_setup_multiple_pads (
usdhc3_pads , ARRAY_SIZE ( usdhc3_pads ) ) ;
gpio_direction_input ( USDHC3_CD_GPIO ) ;
gpio_direction_output ( USDHC3_PWR_GPIO , 1 ) ;
usdhc_cfg [ 1 ] . sdhc_clk = mxc_get_clock ( MXC_ESDHC3_CLK ) ;
break ;
case 2 :
imx_iomux_v3_setup_multiple_pads (
usdhc4_pads , ARRAY_SIZE ( usdhc4_pads ) ) ;
gpio_direction_input ( USDHC4_CD_GPIO ) ;
usdhc_cfg [ 2 ] . sdhc_clk = mxc_get_clock ( MXC_ESDHC4_CLK ) ;
break ;
default :
printf ( " Warning: you configured more USDHC controllers "
" (%d) than supported by the board \n " , i + 1 ) ;
return - EINVAL ;
}
ret = fsl_esdhc_initialize ( bis , & usdhc_cfg [ i ] ) ;
if ( ret ) {
printf ( " Warning: failed to initialize mmc dev %d \n " , i ) ;
return ret ;
}
}
return 0 ;
}
int board_init ( void )
{
/* Address of boot parameters */