Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_CRU_RK3368_H |
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#define _ASM_ARCH_CRU_RK3368_H |
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#include <common.h> |
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/* RK3368 clock numbers */ |
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enum rk3368_pll_id { |
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APLLB, |
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APLLL, |
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DPLL, |
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CPLL, |
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GPLL, |
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NPLL, |
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PLL_COUNT, |
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}; |
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struct rk3368_cru { |
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struct rk3368_pll { |
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unsigned int con0; |
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unsigned int con1; |
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unsigned int con2; |
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unsigned int con3; |
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} pll[6]; |
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unsigned int reserved[0x28]; |
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unsigned int clksel_con[56]; |
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unsigned int reserved1[8]; |
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unsigned int clkgate_con[25]; |
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unsigned int reserved2[7]; |
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unsigned int glb_srst_fst_val; |
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unsigned int glb_srst_snd_val; |
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unsigned int reserved3[0x1e]; |
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unsigned int softrst_con[15]; |
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unsigned int reserved4[0x11]; |
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unsigned int misc_con; |
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unsigned int glb_cnt_th; |
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unsigned int glb_rst_con; |
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unsigned int glb_rst_st; |
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unsigned int reserved5[0x1c]; |
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unsigned int sdmmc_con[2]; |
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unsigned int sdio0_con[2]; |
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unsigned int sdio1_con[2]; |
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unsigned int emmc_con[2]; |
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}; |
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check_member(rk3368_cru, emmc_con[1], 0x41c); |
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struct rk3368_clk_priv { |
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struct rk3368_cru *cru; |
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ulong rate; |
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bool has_bwadj; |
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}; |
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enum { |
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/* PLL CON0 */ |
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PLL_NR_SHIFT = 8, |
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PLL_NR_MASK = GENMASK(13, 8), |
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PLL_OD_SHIFT = 0, |
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PLL_OD_MASK = GENMASK(3, 0), |
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/* PLL CON1 */ |
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PLL_LOCK_STA = BIT(31), |
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PLL_NF_SHIFT = 0, |
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PLL_NF_MASK = GENMASK(12, 0), |
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/* PLL CON2 */ |
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PLL_BWADJ_SHIFT = 0, |
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PLL_BWADJ_MASK = GENMASK(11, 0), |
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/* PLL CON3 */ |
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PLL_MODE_SHIFT = 8, |
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PLL_MODE_MASK = GENMASK(9, 8), |
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PLL_MODE_SLOW = 0, |
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PLL_MODE_NORMAL = 1, |
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PLL_MODE_DEEP_SLOW = 3, |
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PLL_RESET_SHIFT = 5, |
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PLL_RESET = 1, |
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PLL_RESET_MASK = GENMASK(5, 5), |
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/* CLKSEL12_CON */ |
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MCU_STCLK_DIV_SHIFT = 8, |
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MCU_STCLK_DIV_MASK = GENMASK(10, 8), |
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MCU_PLL_SEL_SHIFT = 7, |
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MCU_PLL_SEL_MASK = BIT(7), |
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MCU_PLL_SEL_CPLL = 0, |
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MCU_PLL_SEL_GPLL = 1, |
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MCU_CLK_DIV_SHIFT = 0, |
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MCU_CLK_DIV_MASK = GENMASK(4, 0), |
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/* CLKSEL51_CON */ |
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MMC_PLL_SEL_SHIFT = 8, |
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MMC_PLL_SEL_MASK = GENMASK(9, 8), |
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MMC_PLL_SEL_CPLL = 0, |
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MMC_PLL_SEL_GPLL, |
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MMC_PLL_SEL_USBPHY_480M, |
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MMC_PLL_SEL_24M, |
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MMC_CLK_DIV_SHIFT = 0, |
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MMC_CLK_DIV_MASK = GENMASK(6, 0), |
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/* SOFTRST1_CON */ |
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MCU_PO_SRST_MASK = BIT(13), |
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MCU_SYS_SRST_MASK = BIT(12), |
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/* GLB_RST_CON */ |
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PMU_GLB_SRST_CTRL_SHIFT = 2, |
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PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), |
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PMU_RST_BY_FST_GLB_SRST = 0, |
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PMU_RST_BY_SND_GLB_SRST = 1, |
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PMU_RST_DISABLE = 2, |
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WDT_GLB_SRST_CTRL_SHIFT = 1, |
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WDT_GLB_SRST_CTRL_MASK = BIT(1), |
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WDT_TRIGGER_SND_GLB_SRST = 0, |
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WDT_TRIGGER_FST_GLB_SRST = 1, |
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TSADC_GLB_SRST_CTRL_SHIFT = 0, |
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TSADC_GLB_SRST_CTRL_MASK = BIT(0), |
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TSADC_TRIGGER_SND_GLB_SRST = 0, |
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TSADC_TRIGGER_FST_GLB_SRST = 1, |
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}; |
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#endif |
@ -0,0 +1,291 @@ |
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3368.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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#include <dm/lists.h> |
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#include <dt-bindings/clock/rk3368-cru.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct pll_div { |
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u32 nr; |
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u32 nf; |
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u32 no; |
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}; |
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#define OSC_HZ (24 * 1000 * 1000) |
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#define APLL_L_HZ (800 * 1000 * 1000) |
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#define APLL_B_HZ (816 * 1000 * 1000) |
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#define GPLL_HZ (576 * 1000 * 1000) |
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#define CPLL_HZ (400 * 1000 * 1000) |
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#define RATE_TO_DIV(input_rate, output_rate) \ |
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((input_rate) / (output_rate) - 1); |
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) |
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#define PLL_DIVISORS(hz, _nr, _no) { \ |
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.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
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_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
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"divisors on line " __stringify(__LINE__)); |
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static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); |
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static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); |
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); |
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); |
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/* Get pll rate by id */ |
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static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, |
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enum rk3368_pll_id pll_id) |
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{ |
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uint32_t nr, no, nf; |
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uint32_t con; |
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struct rk3368_pll *pll = &cru->pll[pll_id]; |
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con = readl(&pll->con3); |
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switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { |
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case PLL_MODE_SLOW: |
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return OSC_HZ; |
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case PLL_MODE_NORMAL: |
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con = readl(&pll->con0); |
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no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; |
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nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; |
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con = readl(&pll->con1); |
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nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; |
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return (24 * nf / (nr * no)) * 1000000; |
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case PLL_MODE_DEEP_SLOW: |
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default: |
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return 32768; |
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} |
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} |
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static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, |
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const struct pll_div *div, bool has_bwadj) |
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{ |
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struct rk3368_pll *pll = &cru->pll[pll_id]; |
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/* All PLLs have same VCO and output frequency range restrictions*/ |
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uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; |
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uint output_hz = vco_hz / div->no; |
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debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", |
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pll, div->nf, div->nr, div->no, vco_hz, output_hz); |
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/* enter slow mode and reset pll */ |
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rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, |
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PLL_RESET << PLL_RESET_SHIFT); |
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rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, |
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((div->nr - 1) << PLL_NR_SHIFT) | |
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((div->no - 1) << PLL_OD_SHIFT)); |
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writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); |
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udelay(10); |
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/* return from reset */ |
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rk_clrreg(&pll->con3, PLL_RESET_MASK); |
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/* waiting for pll lock */ |
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while (!(readl(&pll->con1) & PLL_LOCK_STA)) |
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udelay(1); |
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rk_clrsetreg(&pll->con3, PLL_MODE_MASK, |
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PLL_MODE_NORMAL << PLL_MODE_SHIFT); |
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return 0; |
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} |
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static void rkclk_init(struct rk3368_cru *cru) |
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{ |
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u32 apllb, aplll, dpll, cpll, gpll; |
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rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false); |
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rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false); |
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rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false); |
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rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false); |
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apllb = rkclk_pll_get_rate(cru, APLLB); |
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aplll = rkclk_pll_get_rate(cru, APLLL); |
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dpll = rkclk_pll_get_rate(cru, DPLL); |
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cpll = rkclk_pll_get_rate(cru, CPLL); |
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gpll = rkclk_pll_get_rate(cru, GPLL); |
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debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", |
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__func__, apllb, aplll, dpll, cpll, gpll); |
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} |
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static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) |
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{ |
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u32 div, con, con_id, rate; |
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u32 pll_rate; |
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switch (clk_id) { |
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case SCLK_SDMMC: |
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con_id = 50; |
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break; |
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case SCLK_EMMC: |
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con_id = 51; |
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break; |
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case SCLK_SDIO0: |
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con_id = 48; |
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break; |
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default: |
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return -EINVAL; |
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} |
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con = readl(&cru->clksel_con[con_id]); |
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switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) { |
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case MMC_PLL_SEL_GPLL: |
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pll_rate = rkclk_pll_get_rate(cru, GPLL); |
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break; |
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case MMC_PLL_SEL_24M: |
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pll_rate = OSC_HZ; |
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break; |
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case MMC_PLL_SEL_CPLL: |
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case MMC_PLL_SEL_USBPHY_480M: |
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default: |
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return -EINVAL; |
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} |
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div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT; |
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rate = DIV_TO_RATE(pll_rate, div); |
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return rate >> 1; |
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} |
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static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru, |
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ulong clk_id, ulong rate) |
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{ |
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u32 div; |
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u32 con_id; |
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u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL); |
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div = RATE_TO_DIV(gpll_rate, rate << 1); |
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switch (clk_id) { |
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case SCLK_SDMMC: |
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con_id = 50; |
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break; |
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case SCLK_EMMC: |
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con_id = 51; |
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break; |
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case SCLK_SDIO0: |
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con_id = 48; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (div > 0x3f) { |
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div = RATE_TO_DIV(OSC_HZ, rate); |
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rk_clrsetreg(&cru->clksel_con[con_id], |
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MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, |
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(MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) | |
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(div << MMC_CLK_DIV_SHIFT)); |
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} else { |
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rk_clrsetreg(&cru->clksel_con[con_id], |
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MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, |
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(MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) | |
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div << MMC_CLK_DIV_SHIFT); |
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} |
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return rk3368_mmc_get_clk(cru, clk_id); |
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} |
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static ulong rk3368_clk_get_rate(struct clk *clk) |
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{ |
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struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); |
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ulong rate = 0; |
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debug("%s id:%ld\n", __func__, clk->id); |
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switch (clk->id) { |
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case HCLK_SDMMC: |
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case HCLK_EMMC: |
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rate = rk3368_mmc_get_clk(priv->cru, clk->id); |
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break; |
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default: |
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return -ENOENT; |
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} |
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return rate; |
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} |
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static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); |
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ulong ret = 0; |
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debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate); |
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switch (clk->id) { |
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case SCLK_SDMMC: |
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case SCLK_EMMC: |
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ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate); |
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break; |
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default: |
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return -ENOENT; |
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} |
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return ret; |
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} |
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static struct clk_ops rk3368_clk_ops = { |
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.get_rate = rk3368_clk_get_rate, |
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.set_rate = rk3368_clk_set_rate, |
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}; |
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static int rk3368_clk_probe(struct udevice *dev) |
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{ |
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struct rk3368_clk_priv *priv = dev_get_priv(dev); |
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rkclk_init(priv->cru); |
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return 0; |
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} |
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static int rk3368_clk_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct rk3368_clk_priv *priv = dev_get_priv(dev); |
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priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev); |
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return 0; |
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} |
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static int rk3368_clk_bind(struct udevice *dev) |
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{ |
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int ret; |
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/* The reset driver does not have a device node, so bind it here */ |
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ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev); |
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if (ret) |
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error("bind RK3368 reset driver failed: ret=%d\n", ret); |
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return ret; |
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} |
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static const struct udevice_id rk3368_clk_ids[] = { |
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{ .compatible = "rockchip,rk3368-cru" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(rockchip_rk3368_cru) = { |
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.name = "rockchip_rk3368_cru", |
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.id = UCLASS_CLK, |
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.of_match = rk3368_clk_ids, |
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.priv_auto_alloc_size = sizeof(struct rk3368_cru), |
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.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata, |
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.ops = &rk3368_clk_ops, |
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.bind = rk3368_clk_bind, |
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.probe = rk3368_clk_probe, |
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}; |
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