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@ -56,7 +56,7 @@ static void sunxi_de2_composer_init(void) |
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} |
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static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, |
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int bpp, ulong address) |
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int bpp, ulong address, bool is_composite) |
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{ |
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ulong de_mux_base = (mux == 0) ? |
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SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE; |
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@ -72,6 +72,9 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, |
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(struct de_ui *)(de_mux_base + |
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SUNXI_DE2_MUX_CHAN_REGS + |
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SUNXI_DE2_MUX_CHAN_SZ * 1); |
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struct de_csc * const de_csc_regs = |
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(struct de_csc *)(de_mux_base + |
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SUNXI_DE2_MUX_DCSC_REGS); |
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u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); |
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int channel; |
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u32 format; |
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@ -128,7 +131,27 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, |
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writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS); |
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writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS); |
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS); |
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writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS); |
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if (is_composite) { |
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/* set CSC coefficients */ |
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writel(0x107, &de_csc_regs->coef11); |
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writel(0x204, &de_csc_regs->coef12); |
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writel(0x64, &de_csc_regs->coef13); |
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writel(0x4200, &de_csc_regs->coef14); |
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writel(0x1f68, &de_csc_regs->coef21); |
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writel(0x1ed6, &de_csc_regs->coef22); |
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writel(0x1c2, &de_csc_regs->coef23); |
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writel(0x20200, &de_csc_regs->coef24); |
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writel(0x1c2, &de_csc_regs->coef31); |
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writel(0x1e87, &de_csc_regs->coef32); |
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writel(0x1fb7, &de_csc_regs->coef33); |
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writel(0x20200, &de_csc_regs->coef34); |
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/* enable CSC unit */ |
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writel(1, &de_csc_regs->csc_ctl); |
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} else { |
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writel(0, &de_csc_regs->csc_ctl); |
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} |
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switch (bpp) { |
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case 16: |
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@ -153,7 +176,7 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, |
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static int sunxi_de2_init(struct udevice *dev, ulong fbbase, |
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enum video_log2_bpp l2bpp, |
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struct udevice *disp, int mux) |
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struct udevice *disp, int mux, bool is_composite) |
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{ |
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struct video_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct display_timing timing; |
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@ -183,7 +206,7 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, |
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} |
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sunxi_de2_composer_init(); |
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase); |
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); |
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ret = display_enable(disp, 1 << l2bpp, &timing); |
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if (ret) { |
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@ -204,7 +227,6 @@ static int sunxi_de2_probe(struct udevice *dev) |
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); |
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struct udevice *disp; |
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int ret; |
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int mux; |
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/* Before relocation we don't need to do anything */ |
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if (!(gd->flags & GD_FLG_RELOC)) |
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@ -212,17 +234,31 @@ static int sunxi_de2_probe(struct udevice *dev) |
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ret = uclass_find_device_by_name(UCLASS_DISPLAY, |
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"sunxi_dw_hdmi", &disp); |
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if (!ret) { |
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int mux; |
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) |
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mux = 0; |
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else |
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mux = 1; |
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, |
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false); |
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if (!ret) { |
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video_set_flush_dcache(dev, 1); |
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return 0; |
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} |
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} |
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); |
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ret = uclass_find_device_by_name(UCLASS_DISPLAY, |
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"sunxi_tve", &disp); |
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if (ret) { |
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); |
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debug("%s: tv not found (ret=%d)\n", __func__, ret); |
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return ret; |
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} |
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) |
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mux = 0; |
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else |
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mux = 1; |
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux); |
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); |
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if (ret) |
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return ret; |
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