This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The driver supports probing and basic register access. It supports the standard device tree binding and supports driver model. A regulator driver can be provided also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>master
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/*
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* Copyright (C) 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fdtdec.h> |
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#include <errno.h> |
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#include <dm.h> |
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#include <i2c.h> |
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#include <power/pmic.h> |
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#include <power/regulator.h> |
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#include <power/s5m8767.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct pmic_child_info pmic_children_info[] = { |
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{ .prefix = "LDO", .driver = S5M8767_LDO_DRIVER }, |
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{ .prefix = "BUCK", .driver = S5M8767_BUCK_DRIVER }, |
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{ }, |
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}; |
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static int s5m8767_reg_count(struct udevice *dev) |
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{ |
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return S5M8767_NUM_OF_REGS; |
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} |
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static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff, |
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int len) |
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{ |
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if (dm_i2c_write(dev, reg, buff, len)) { |
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error("write error to device: %p register: %#x!", dev, reg); |
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return -EIO; |
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} |
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return 0; |
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} |
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static int s5m8767_read(struct udevice *dev, uint reg, uint8_t *buff, int len) |
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{ |
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if (dm_i2c_read(dev, reg, buff, len)) { |
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error("read error from device: %p register: %#x!", dev, reg); |
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return -EIO; |
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} |
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return 0; |
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} |
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int s5m8767_enable_32khz_cp(struct udevice *dev) |
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{ |
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return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1); |
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} |
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static int s5m8767_bind(struct udevice *dev) |
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{ |
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int node; |
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const void *blob = gd->fdt_blob; |
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int children; |
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node = fdt_subnode_offset(blob, dev->of_offset, "regulators"); |
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if (node <= 0) { |
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debug("%s: %s regulators subnode not found!", __func__, |
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dev->name); |
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return -ENXIO; |
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} |
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debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); |
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children = pmic_bind_children(dev, node, pmic_children_info); |
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if (!children) |
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debug("%s: %s - no child found\n", __func__, dev->name); |
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/* Always return success for this device */ |
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return 0; |
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} |
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static struct dm_pmic_ops s5m8767_ops = { |
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.reg_count = s5m8767_reg_count, |
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.read = s5m8767_read, |
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.write = s5m8767_write, |
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}; |
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static const struct udevice_id s5m8767_ids[] = { |
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{ .compatible = "samsung,s5m8767-pmic" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(pmic_s5m8767) = { |
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.name = "s5m8767_pmic", |
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.id = UCLASS_PMIC, |
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.of_match = s5m8767_ids, |
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.bind = s5m8767_bind, |
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.ops = &s5m8767_ops, |
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}; |
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/*
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* Copyright (c) 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __S5M8767_H_ |
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#define __S5M8767_H_ |
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enum s5m8767_regnum { |
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S5M8767_BUCK1 = 0, |
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S5M8767_BUCK2, |
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S5M8767_BUCK3, |
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S5M8767_BUCK4, |
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S5M8767_BUCK5, |
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S5M8767_BUCK6, |
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S5M8767_BUCK7, |
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S5M8767_BUCK8, |
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S5M8767_BUCK9, |
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S5M8767_LDO1, |
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S5M8767_LDO2, |
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S5M8767_LDO3, |
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S5M8767_LDO4, |
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S5M8767_LDO5, |
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S5M8767_LDO6, |
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S5M8767_LDO7, |
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S5M8767_LDO8, |
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S5M8767_LDO9, |
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S5M8767_LDO10, |
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S5M8767_LDO11, |
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S5M8767_LDO12, |
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S5M8767_LDO13, |
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S5M8767_LDO14, |
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S5M8767_LDO15, |
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S5M8767_LDO16, |
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S5M8767_LDO17, |
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S5M8767_LDO18, |
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S5M8767_LDO19, |
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S5M8767_LDO20, |
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S5M8767_LDO21, |
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S5M8767_LDO22, |
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S5M8767_LDO23, |
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S5M8767_LDO24, |
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S5M8767_LDO25, |
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S5M8767_LDO26, |
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S5M8767_LDO27, |
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S5M8767_LDO28, |
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S5M8767_EN32KHZ_CP, |
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S5M8767_NUM_OF_REGS, |
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}; |
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struct sec_voltage_desc { |
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int max; |
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int min; |
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int step; |
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}; |
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/**
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* struct s5m8767_para - s5m8767 register parameters |
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* @param vol_addr i2c address of the given buck/ldo register |
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* @param vol_bitpos bit position to be set or clear within register |
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* @param vol_bitmask bit mask value |
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* @param reg_enaddr control register address, which enable the given |
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* given buck/ldo. |
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* @param reg_enbiton value to be written to buck/ldo to make it ON |
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* @param vol Voltage information |
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*/ |
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struct s5m8767_para { |
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enum s5m8767_regnum regnum; |
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u8 vol_addr; |
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u8 vol_bitpos; |
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u8 vol_bitmask; |
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u8 reg_enaddr; |
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u8 reg_enbiton; |
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const struct sec_voltage_desc *vol; |
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}; |
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/* Drivers name */ |
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#define S5M8767_LDO_DRIVER "s5m8767_ldo" |
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#define S5M8767_BUCK_DRIVER "s5m8767_buck" |
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int s5m8767_enable_32khz_cp(struct udevice *dev); |
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#endif /* __S5M8767_PMIC_H_ */ |
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