This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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Sandbox SPMI emulated arbiter. |
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This is bus driver for Sandbox. It includes part of emulated pm8916 pmic. |
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Required properties: |
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- compatible: "sandbox,spmi" |
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- #address-cells: 0x1 - childs slave ID address |
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- #size-cells: 0x1 |
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Example: |
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spmi: spmi@0 { |
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compatible = "sandbox,spmi"; |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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pm8916@0 { |
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compatible = "qcom,spmi-pmic"; |
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reg = <0x0 0x1>; |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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spmi_gpios: gpios@c000 { |
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compatible = "qcom,pm8916-gpio"; |
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reg = <0xc000 0x400>; |
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gpio-controller; |
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gpio-count = <4>; |
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#gpio-cells = <2>; |
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gpio-bank-name="spmi"; |
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}; |
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}; |
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}; |
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/*
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* Sample SPMI bus driver |
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* |
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* It emulates bus with single pm8916-like pmic that has only GPIO reigsters. |
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* |
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <spmi/spmi.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define EMUL_GPIO_PID_START 0xC0 |
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#define EMUL_GPIO_PID_END 0xC3 |
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#define EMUL_GPIO_COUNT 4 |
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#define EMUL_GPIO_REG_END 0x46 /* Last valid register */ |
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#define EMUL_PERM_R 0x1 |
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#define EMUL_PERM_W 0x2 |
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#define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W) |
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struct sandbox_emul_fake_regs { |
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u8 value; |
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u8 access_mask; |
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u8 perms; /* Access permissions */ |
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}; |
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struct sandbox_emul_gpio { |
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struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END]; /* Fake registers */ |
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}; |
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struct sandbox_spmi_priv { |
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struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT]; |
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}; |
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/* Check if valid register was requested */ |
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static bool check_address_valid(int usid, int pid, int off) |
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{ |
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if (usid != 0) |
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return false; |
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if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END) |
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return false; |
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if (off > EMUL_GPIO_REG_END) |
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return false; |
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return true; |
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} |
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static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off, |
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uint8_t val) |
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{ |
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struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
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struct sandbox_emul_fake_regs *regs; |
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if (!check_address_valid(usid, pid, off)) |
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return -EIO; |
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regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ |
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switch (off) { |
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case 0x40: /* Control */ |
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val &= regs[off].access_mask; |
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if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) { |
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/* out/inout - set status register */ |
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regs[0x8].value &= ~0x1; |
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regs[0x8].value |= val & 0x1; |
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} |
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break; |
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default: |
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if (regs[off].perms & EMUL_PERM_W) |
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regs[off].value = val & regs[off].access_mask; |
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} |
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return 0; |
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} |
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static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off) |
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{ |
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struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
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struct sandbox_emul_fake_regs *regs; |
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if (!check_address_valid(usid, pid, off)) |
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return -EIO; |
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regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ |
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if (regs[0x46].value == 0) /* Block disabled */ |
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return 0; |
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switch (off) { |
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case 0x8: /* Status */ |
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if (regs[0x46].value == 0) /* Block disabled */ |
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return 0; |
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return regs[off].value; |
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default: |
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if (regs[off].perms & EMUL_PERM_R) |
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return regs[off].value; |
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else |
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return 0; |
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} |
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} |
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static struct dm_spmi_ops sandbox_spmi_ops = { |
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.read = sandbox_spmi_read, |
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.write = sandbox_spmi_write, |
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}; |
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static int sandbox_spmi_probe(struct udevice *dev) |
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{ |
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struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
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int i; |
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for (i = 0; i < EMUL_GPIO_COUNT; ++i) { |
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struct sandbox_emul_fake_regs *regs = priv->gpios[i].r; |
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regs[4].perms = EMUL_PERM_R; |
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regs[4].value = 0x10; |
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regs[5].perms = EMUL_PERM_R; |
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regs[5].value = 0x5; |
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regs[8].access_mask = 0x81; |
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regs[8].perms = EMUL_PERM_RW; |
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regs[0x40].access_mask = 0x7F; |
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regs[0x40].perms = EMUL_PERM_RW; |
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regs[0x41].access_mask = 7; |
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regs[0x41].perms = EMUL_PERM_RW; |
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regs[0x42].access_mask = 7; |
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regs[0x42].perms = EMUL_PERM_RW; |
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regs[0x42].value = 0x4; |
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regs[0x45].access_mask = 0x3F; |
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regs[0x45].perms = EMUL_PERM_RW; |
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regs[0x45].value = 0x1; |
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regs[0x46].access_mask = 0x80; |
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regs[0x46].perms = EMUL_PERM_RW; |
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regs[0x46].value = 0x80; |
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} |
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return 0; |
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} |
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static const struct udevice_id sandbox_spmi_ids[] = { |
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{ .compatible = "sandbox,spmi" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(msm_spmi) = { |
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.name = "sandbox_spmi", |
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.id = UCLASS_SPMI, |
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.of_match = sandbox_spmi_ids, |
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.ops = &sandbox_spmi_ops, |
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.probe = sandbox_spmi_probe, |
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.priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv), |
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}; |
@ -0,0 +1,114 @@ |
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/*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <fdtdec.h> |
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#include <dm.h> |
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#include <dm/device.h> |
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#include <dm/root.h> |
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#include <dm/test.h> |
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#include <dm/util.h> |
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#include <power/pmic.h> |
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#include <spmi/spmi.h> |
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#include <asm/gpio.h> |
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#include <test/ut.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Test if bus childs got probed propperly*/ |
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static int dm_test_spmi_probe(struct unit_test_state *uts) |
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{ |
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const char *name = "spmi@0"; |
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struct udevice *bus, *dev; |
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ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus)); |
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/* Check bus name */ |
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ut_asserteq_str(name, bus->name); |
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/* Check that it has some devices */ |
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ut_asserteq(device_has_children(bus), true); |
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ut_assertok(device_find_first_child(bus, &dev)); |
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/* There should be at least one child */ |
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ut_assertnonnull(dev); |
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/* Check that only PMICs are connected to the bus */ |
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while (dev) { |
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ut_asserteq(device_get_uclass_id(dev), UCLASS_PMIC); |
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device_find_next_child(&dev); |
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} |
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return 0; |
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} |
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DM_TEST(dm_test_spmi_probe, DM_TESTF_SCAN_FDT); |
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/* Test if it's possible to read bus directly and indirectly */ |
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static int dm_test_spmi_access(struct unit_test_state *uts) |
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{ |
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const char *pmic_name = "pm8916@0"; |
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struct udevice *bus, *pmic; |
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ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus)); |
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ut_assertok(device_get_child(bus, 0, &pmic)); |
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/* Sanity check if it's proper PMIC */ |
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ut_asserteq_str(pmic_name, pmic->name); |
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/* Read PMIC ID reg using SPMI bus - it assumes it has slaveID == 0*/ |
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ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x4), 0x10); |
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ut_asserteq(spmi_reg_read(bus, 0, 0xC0, 0x5), 0x5); |
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/* Read ID reg via pmic interface */ |
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ut_asserteq(pmic_reg_read(pmic, 0xC004), 0x10); |
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ut_asserteq(pmic_reg_read(pmic, 0xC005), 0x5); |
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return 0; |
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} |
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DM_TEST(dm_test_spmi_access, DM_TESTF_SCAN_FDT); |
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/* Test if it's possible to access GPIO that should be in pmic */ |
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static int dm_test_spmi_access_peripheral(struct unit_test_state *uts) |
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{ |
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struct udevice *dev; |
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unsigned int offset, gpio; |
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const char *name; |
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int offset_count; |
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/* Get second pin of PMIC GPIO */ |
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ut_assertok(gpio_lookup_name("spmi1", &dev, &offset, &gpio)); |
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/* Check if PMIC is parent */ |
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ut_asserteq(device_get_uclass_id(dev->parent), UCLASS_PMIC); |
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/* This should be second gpio */ |
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ut_asserteq(1, offset); |
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name = gpio_get_bank_info(dev, &offset_count); |
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/* Check bank name */ |
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ut_asserteq_str("spmi", name); |
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/* Check pin count */ |
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ut_asserteq(4, offset_count); |
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ut_assertok(gpio_request(gpio, "testing")); |
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/* Try to set/clear gpio */ |
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ut_assertok(gpio_direction_output(gpio, 0)); |
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ut_asserteq(gpio_get_value(gpio), 0); |
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ut_assertok(gpio_direction_output(gpio, 1)); |
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ut_asserteq(gpio_get_value(gpio), 1); |
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ut_assertok(gpio_direction_input(gpio)); |
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ut_asserteq(gpio_get_value(gpio), 1); |
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ut_assertok(gpio_free(gpio)); |
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return 0; |
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} |
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DM_TEST(dm_test_spmi_access_peripheral, DM_TESTF_SCAN_FDT); |
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