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mvgbe: support SoCs other than kirkwood

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Rename all references to kirkwood in mvgbe symbols
throughout the whole codebase.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
master
Albert Aribaud 15 years ago committed by Ben Warren
parent 9b6bcdcb93
commit d44265ad78
12 changed files with 439 additions and 416 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/arm/cpu/arm926ejs/kirkwood/cpu.c
  2. 3
      arch/arm/include/asm/arch-kirkwood/kirkwood.h
  3. 2
      drivers/net/Makefile
  4. 346
      drivers/net/mvgbe.c
  5. 474
      drivers/net/mvgbe.h
  6. 4
      include/configs/guruplug.h
  7. 4
      include/configs/km_arm.h
  8. 4
      include/configs/mv88f6281gtw_ge.h
  9. 4
      include/configs/openrd_base.h
  10. 4
      include/configs/rd6281a.h
  11. 4
      include/configs/sheevaplug.h
  12. 2
      include/netdev.h

4
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
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@ -378,10 +378,10 @@ int arch_misc_init(void)
}
#endif /* CONFIG_ARCH_MISC_INIT */
#ifdef CONFIG_KIRKWOOD_EGIGA
#ifdef CONFIG_MVGBE
int cpu_eth_init(bd_t *bis)
{
kirkwood_egiga_initialize(bis);
mvgbe_initialize(bis);
return 0;
}
#endif

3
arch/arm/include/asm/arch-kirkwood/kirkwood.h
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@ -60,6 +60,9 @@
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
#define MVGBE0_BASE KW_EGIGA0_BASE
#define MVGBE1_BASE KW_EGIGA1_BASE
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)

2
drivers/net/Makefile
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@ -53,7 +53,7 @@ COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
COBJS-$(CONFIG_KIRKWOOD_EGIGA) += mvgbe.o
COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o

346
drivers/net/mvgbe.c
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@ -35,13 +35,17 @@
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#if defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#endif
#include "mvgbe.h"
DECLARE_GLOBAL_DATA_PTR;
#define KIRKWOOD_PHY_ADR_REQUEST 0xee
#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
/*
* smi_reg_read - miiphy_read callback function.
@ -51,16 +55,16 @@ DECLARE_GLOBAL_DATA_PTR;
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
/* */
*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
*data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
@ -75,42 +79,43 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
return -EFAULT;
}
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
| KWGBE_PHY_SMI_OPCODE_READ;
smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
| MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
/*wait till read value is ready */
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
} while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
;
*data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
*data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
@ -127,15 +132,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
KWGBEREG_WR(regs->phyadr, data);
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
MVGBE_REG_WR(regs->phyadr, data);
return 0;
}
@ -150,24 +155,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* wait till the SMI is not busy */
timeout = KWGBE_PHY_SMI_TIMEOUT;
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
return 0;
}
@ -204,46 +209,46 @@ static void stop_queue(u32 * qreg)
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
static void set_access_control(struct kwgbe_registers *regs,
struct kwgbe_winparam *param)
static void set_access_control(struct mvgbe_registers *regs,
struct mvgbe_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
access_prot_reg = KWGBEREG_RD(regs->epap);
access_prot_reg = MVGBE_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
KWGBEREG_WR(regs->epap, access_prot_reg);
MVGBE_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
KWGBEREG_WR(regs->barsz[param->win].size,
MVGBE_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
KWGBEREG_WR(regs->barsz[param->win].bar,
MVGBE_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
else
KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
}
static void set_dram_access(struct kwgbe_registers *regs)
static void set_dram_access(struct mvgbe_registers *regs)
{
struct kwgbe_winparam win_param;
struct mvgbe_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
win_param.target = KWGBE_TARGET_DRAM;
win_param.target = MVGBE_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
@ -286,19 +291,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
static void port_init_mac_tables(struct kwgbe_registers *regs)
static void port_init_mac_tables(struct mvgbe_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
KWGBEREG_WR(regs->dfut[table_index], 0);
MVGBE_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
KWGBEREG_WR(regs->dfsmt[table_index], 0);
MVGBE_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
KWGBEREG_WR(regs->dfomt[table_index], 0);
MVGBE_REG_WR(regs->dfomt[table_index], 0);
}
}
@ -316,7 +321,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
@ -336,16 +341,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
* Clear accepts frame bit at specified unicast
* DA table entry
*/
unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
@ -356,7 +361,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
@ -365,94 +370,95 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
KWGBEREG_WR(regs->macal, mac_l);
KWGBEREG_WR(regs->macah, mac_h);
MVGBE_REG_WR(regs->macal, mac_l);
MVGBE_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
* kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
* mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
{
struct kwgbe_rxdesc *p_rx_desc;
struct mvgbe_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
p_rx_desc = dkwgbe->p_rxdesc;
p_rx_desc = dmvgbe->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
else {
p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
}
static int kwgbe_init(struct eth_device *dev)
static int mvgbe_init(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
kwgbe_init_rx_desc_ring(dkwgbe);
mvgbe_init_rx_desc_ring(dmvgbe);
/* Clear the ethernet port interrupts */
KWGBEREG_WR(regs->ic, 0);
KWGBEREG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
/* Assign port configuration and command. */
KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
MVGBE_REG_WR(regs->tqx[0].tqxtbc,
(QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
KWGBEREG_WR(regs->pmtu, 0);
MVGBE_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
| (KWGBEREG_RD(regs->psc0) & MRU_MASK));
MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
| (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
KWGBEREG_WR(regs->pmtu, 0);
MVGBE_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
/* ensure previous write is done before enabling Rx DMA */
isb();
/* Enable port Rx. */
KWGBEREG_WR(regs->rqc, (1 << RXUQ));
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@ -460,8 +466,8 @@ static int kwgbe_init(struct eth_device *dev)
for (i = 0; i < 5; i++) {
u16 phyadr;
miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
@ -474,50 +480,50 @@ static int kwgbe_init(struct eth_device *dev)
return 0;
}
static int kwgbe_halt(struct eth_device *dev)
static int mvgbe_halt(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Disable all gigE address decoder */
KWGBEREG_WR(regs->bare, 0x3f);
MVGBE_REG_WR(regs->bare, 0x3f);
stop_queue(&regs->tqc);
stop_queue(&regs->rqc);
/* Disable port */
KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/* Set port is not reset */
KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
KWGBEREG_WR(regs->ic, 0);
KWGBEREG_WR(regs->ice, 0);
KWGBEREG_WR(regs->pim, 0);
KWGBEREG_WR(regs->peim, 0);
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->pim, 0);
MVGBE_REG_WR(regs->peim, 0);
return 0;
}
static int kwgbe_write_hwaddr(struct eth_device *dev)
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
return 0;
}
static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
static int mvgbe_send(struct eth_device *dev, void *dataptr,
int datasize)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
@ -529,35 +535,35 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return -1;
}
memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
p = dkwgbe->p_aligned_txbuf;
memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
p = dmvgbe->p_aligned_txbuf;
}
p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Set this tc desc as zeroth TXUQ */
KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
/* ensure tx desc writes above are performed before we start Tx DMA */
isb();
/* Apply send command using zeroth TXUQ */
KWGBEREG_WR(regs->tqc, (1 << TXUQ));
MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
(KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
@ -566,22 +572,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return 0;
}
static int kwgbe_recv(struct eth_device *dev)
static int mvgbe_recv(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
if (timeout < KWGBE_PHY_SMI_TIMEOUT)
if (timeout < MVGBE_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
} while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
} while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@ -598,13 +604,13 @@ static int kwgbe_recv(struct eth_device *dev)
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
(MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
!= (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
} else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
} else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
@ -622,62 +628,72 @@ static int kwgbe_recv(struct eth_device *dev)
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
writel((unsigned)p_rxdesc_curr->nxtdesc_p,
(u32) &dmvgbe->p_rxdesc_curr);
return 0;
}
int kirkwood_egiga_initialize(bd_t * bis)
int mvgbe_initialize(bd_t *bis)
{
struct kwgbe_device *dkwgbe;
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
char *s;
u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
dmvgbe = malloc(sizeof(struct mvgbe_device));
if (!dmvgbe)
goto error1;
memset(dkwgbe, 0, sizeof(struct kwgbe_device));
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
if (!(dkwgbe->p_rxdesc =
(struct kwgbe_rxdesc *)memalign(PKTALIGN,
KW_RXQ_DESC_ALIGNED_SIZE
* RINGSZ + 1)))
dmvgbe->p_rxdesc =
(struct mvgbe_rxdesc *)memalign(PKTALIGN,
MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
if (!dmvgbe->p_rxdesc)
goto error2;
if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
* PKTSIZE_ALIGN + 1)))
dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
RINGSZ*PKTSIZE_ALIGN + 1);
if (!dmvgbe->p_rxbuf)
goto error3;
if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
if (!dmvgbe->p_aligned_txbuf)
goto error4;
if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
free(dkwgbe->p_aligned_txbuf);
error4:
free(dkwgbe->p_rxbuf);
error3:
free(dkwgbe->p_rxdesc);
error2:
free(dkwgbe);
error1:
dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
if (!dmvgbe->p_txdesc) {
free(dmvgbe->p_aligned_txbuf);
error4:
free(dmvgbe->p_rxbuf);
error3:
free(dmvgbe->p_rxdesc);
error2:
free(dmvgbe);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
dev = &dkwgbe->dev;
dev = &dmvgbe->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
@ -685,13 +701,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
dkwgbe->regs = (void *)KW_EGIGA0_BASE;
dmvgbe->regs = (void *)MVGBE0_BASE;
s = "ethaddr";
break;
#if defined(MVGBE1_BASE)
case 1:
dkwgbe->regs = (void *)KW_EGIGA1_BASE;
dmvgbe->regs = (void *)MVGBE1_BASE;
s = "eth1addr";
break;
#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
@ -717,19 +735,19 @@ int kirkwood_egiga_initialize(bd_t * bis)
eth_setenv_enetaddr(s, dev->enetaddr);
}
dev->init = (void *)kwgbe_init;
dev->halt = (void *)kwgbe_halt;
dev->send = (void *)kwgbe_send;
dev->recv = (void *)kwgbe_recv;
dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
dev->init = (void *)mvgbe_init;
dev->halt = (void *)mvgbe_halt;
dev->send = (void *)mvgbe_send;
dev->recv = (void *)mvgbe_recv;
dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;

474
drivers/net/mvgbe.h
Unescape View File

@ -25,10 +25,10 @@
* MA 02110-1301 USA
*/
#ifndef __EGIGA_H__
#define __EGIGA_H__
#ifndef __MVGBE_H__
#define __MVGBE_H__
#define MAX_KWGBE_DEVS 2 /*controller has two ports */
#define MAX_MVGBE_DEVS 2 /*controller has two ports */
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
@ -49,60 +49,60 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
#define KWGBEREG_WR(adr, val) writel(val, &adr)
#define KWGBEREG_RD(adr) readl(&adr)
#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
KWGBE_UCAST_MOD_NRML | \
KWGBE_DFLT_RXQ(RXUQ) | \
KWGBE_DFLT_RX_ARPQ(RXUQ) | \
KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
KWGBE_RX_BC_IF_IP | \
KWGBE_RX_BC_IF_ARP | \
KWGBE_CPTR_TCP_FRMS_DIS | \
KWGBE_CPTR_UDP_FRMS_DIS | \
KWGBE_DFLT_RX_TCPQ(RXUQ) | \
KWGBE_DFLT_RX_UDPQ(RXUQ) | \
KWGBE_DFLT_RX_BPDUQ(RXUQ))
MVGBE_UCAST_MOD_NRML | \
MVGBE_DFLT_RXQ(RXUQ) | \
MVGBE_DFLT_RX_ARPQ(RXUQ) | \
MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
MVGBE_RX_BC_IF_IP | \
MVGBE_RX_BC_IF_ARP | \
MVGBE_CPTR_TCP_FRMS_DIS | \
MVGBE_CPTR_UDP_FRMS_DIS | \
MVGBE_DFLT_RX_TCPQ(RXUQ) | \
MVGBE_DFLT_RX_UDPQ(RXUQ) | \
MVGBE_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
KWGBE_PARTITION_DIS | \
KWGBE_TX_CRC_GENERATION_EN
MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
MVGBE_PARTITION_DIS | \
MVGBE_TX_CRC_GENERATION_EN
#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
KWGBE_RX_BURST_SIZE_16_64BIT | \
KWGBE_BLM_RX_NO_SWAP | \
KWGBE_BLM_TX_NO_SWAP | \
GT_KWGBE_IPG_INT_RX(RXUQ) | \
KWGBE_TX_BURST_SIZE_16_64BIT)
MVGBE_RX_BURST_SIZE_16_64BIT | \
MVGBE_BLM_RX_NO_SWAP | \
MVGBE_BLM_TX_NO_SWAP | \
GT_MVGBE_IPG_INT_RX(RXUQ) | \
MVGBE_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
KWGBE_FORCE_LINK_PASS | \
KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
KWGBE_ADV_NO_FLOW_CTRL | \
KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
KWGBE_FORCE_BP_MODE_NO_JAM | \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
KWGBE_DO_NOT_FORCE_LINK_FAIL | \
KWGBE_EN_AUTO_NEG_SPEED_GMII | \
KWGBE_DTE_ADV_0 | \
KWGBE_MIIPHY_MAC_MODE | \
KWGBE_AUTO_NEG_NO_CHANGE | \
KWGBE_MAX_RX_PACKET_1552BYTE | \
KWGBE_CLR_EXT_LOOPBACK | \
KWGBE_SET_FULL_DUPLEX_MODE | \
KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_EN_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
@ -112,187 +112,189 @@
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define KW_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
#define MV_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
#define KWGBE_INTERFACE_GMII_MII 0
#define KWGBE_INTERFACE_PCM 1
#define KWGBE_LINK_IS_DOWN 0
#define KWGBE_LINK_IS_UP (1 << 1)
#define KWGBE_PORT_AT_HALF_DUPLEX 0
#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
#define KWGBE_RX_FLOW_CTRL_DISD 0
#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
#define KWGBE_GMII_SPEED_100_10 0
#define KWGBE_GMII_SPEED_1000 (1 << 4)
#define KWGBE_MII_SPEED_10 0
#define KWGBE_MII_SPEED_100 (1 << 5)
#define KWGBE_NO_TX 0
#define KWGBE_TX_IN_PROGRESS (1 << 7)
#define KWGBE_BYPASS_NO_ACTIVE 0
#define KWGBE_BYPASS_ACTIVE (1 << 8)
#define KWGBE_PORT_NOT_AT_PARTN_STT 0
#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
#define MVGBE_INTERFACE_GMII_MII 0
#define MVGBE_INTERFACE_PCM 1
#define MVGBE_LINK_IS_DOWN 0
#define MVGBE_LINK_IS_UP (1 << 1)
#define MVGBE_PORT_AT_HALF_DUPLEX 0
#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
#define MVGBE_RX_FLOW_CTRL_DISD 0
#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
#define MVGBE_GMII_SPEED_100_10 0
#define MVGBE_GMII_SPEED_1000 (1 << 4)
#define MVGBE_MII_SPEED_10 0
#define MVGBE_MII_SPEED_100 (1 << 5)
#define MVGBE_NO_TX 0
#define MVGBE_TX_IN_PROGRESS (1 << 7)
#define MVGBE_BYPASS_NO_ACTIVE 0
#define MVGBE_BYPASS_ACTIVE (1 << 8)
#define MVGBE_PORT_NOT_AT_PARTN_STT 0
#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
#define KWGBE_UCAST_MOD_NRML 0
#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
#define KWGBE_DFLT_RXQ(_x) (_x << 1)
#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define KWGBE_RX_BC_IF_IP 0
#define KWGBE_REJECT_BC_IF_IP (1 << 8)
#define KWGBE_RX_BC_IF_ARP 0
#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
#define KWGBE_CPTR_TCP_FRMS_DIS 0
#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
#define KWGBE_CPTR_UDP_FRMS_DIS 0
#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
#define MVGBE_UCAST_MOD_NRML 0
#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
#define MVGBE_DFLT_RXQ(_x) (_x << 1)
#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define MVGBE_RX_BC_IF_IP 0
#define MVGBE_REJECT_BC_IF_IP (1 << 8)
#define MVGBE_RX_BC_IF_ARP 0
#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
#define MVGBE_CPTR_TCP_FRMS_DIS 0
#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
#define MVGBE_CPTR_UDP_FRMS_DIS 0
#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define KWGBE_CLASSIFY_EN 1
#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
#define KWGBE_PARTITION_DIS 0
#define KWGBE_PARTITION_EN (1 << 2)
#define KWGBE_TX_CRC_GENERATION_EN 0
#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
#define MVGBE_CLASSIFY_EN 1
#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
#define MVGBE_PARTITION_DIS 0
#define MVGBE_PARTITION_EN (1 << 2)
#define MVGBE_TX_CRC_GENERATION_EN 0
#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define KWGBE_RIFB 1
#define KWGBE_RX_BURST_SIZE_1_64BIT 0
#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
#define KWGBE_BLM_RX_BYTE_SWAP 0
#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
#define KWGBE_BLM_TX_BYTE_SWAP 0
#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
#define KWGBE_DESCRIPTORS_NO_SWAP 0
#define KWGBE_TX_BURST_SIZE_1_64BIT 0
#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
#define MVGBE_RIFB 1
#define MVGBE_RX_BURST_SIZE_1_64BIT 0
#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
#define MVGBE_BLM_RX_BYTE_SWAP 0
#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
#define MVGBE_BLM_TX_BYTE_SWAP 0
#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
#define MVGBE_DESCRIPTORS_NO_SWAP 0
#define MVGBE_TX_BURST_SIZE_1_64BIT 0
#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
#define KWGBE_SERIAL_PORT_DIS 0
#define KWGBE_SERIAL_PORT_EN 1
#define KWGBE_FORCE_LINK_PASS (1 << 1)
#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define KWGBE_ADV_NO_FLOW_CTRL 0
#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define KWGBE_FORCE_BP_MODE_NO_JAM 0
#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
#define KWGBE_FORCE_LINK_FAIL 0
#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
#define KWGBE_DTE_ADV_0 0
#define KWGBE_DTE_ADV_1 (1 << 14)
#define KWGBE_MIIPHY_MAC_MODE 0
#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
#define KWGBE_AUTO_NEG_NO_CHANGE 0
#define KWGBE_RESTART_AUTO_NEG (1 << 16)
#define KWGBE_MAX_RX_PACKET_1518BYTE 0
#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
#define KWGBE_CLR_EXT_LOOPBACK 0
#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
#define KWGBE_SET_HALF_DUPLEX_MODE 0
#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define KWGBE_SET_GMII_SPEED_TO_10_100 0
#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
#define KWGBE_SET_MII_SPEED_TO_10 0
#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
#define MVGBE_SERIAL_PORT_DIS 0
#define MVGBE_SERIAL_PORT_EN 1
#define MVGBE_FORCE_LINK_PASS (1 << 1)
#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define MVGBE_ADV_NO_FLOW_CTRL 0
#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define MVGBE_FORCE_BP_MODE_NO_JAM 0
#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
#define MVGBE_FORCE_LINK_FAIL 0
#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
#define MVGBE_DTE_ADV_0 0
#define MVGBE_DTE_ADV_1 (1 << 14)
#define MVGBE_MIIPHY_MAC_MODE 0
#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
#define MVGBE_AUTO_NEG_NO_CHANGE 0
#define MVGBE_RESTART_AUTO_NEG (1 << 16)
#define MVGBE_MAX_RX_PACKET_1518BYTE 0
#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
#define MVGBE_CLR_EXT_LOOPBACK 0
#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
#define MVGBE_SET_HALF_DUPLEX_MODE 0
#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define MVGBE_SET_GMII_SPEED_TO_10_100 0
#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
#define MVGBE_SET_MII_SPEED_TO_10 0
#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
#define KWGBE_PHY_SMI_TIMEOUT 10000
#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
#define MVGBE_PHY_SMI_TIMEOUT 10000
#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
#define MVGBE_SMI_REG_ADDR_MASK \
(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define KWGBE_ERROR_SUMMARY 1
#define MVGBE_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
#define KWGBE_LC_ERROR 0
#define KWGBE_UR_ERROR (1 << 1)
#define KWGBE_RL_ERROR (1 << 2)
#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
#define KWGBE_TX_LAST_FRAME (1 << 20)
#define MVGBE_LC_ERROR 0
#define MVGBE_UR_ERROR (1 << 1)
#define MVGBE_RL_ERROR (1 << 2)
#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
#define MVGBE_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
#define KWGBE_CRC_ERROR 0
#define KWGBE_OVERRUN_ERROR (1 << 1)
#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
#define KWGBE_VLAN_TAGGED (1 << 19)
#define KWGBE_BPDU_FRAME (1 << 20)
#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
#define KWGBE_FRAME_HEADER_OK (1 << 25)
#define KWGBE_RX_LAST_DESC (1 << 26)
#define KWGBE_RX_FIRST_DESC (1 << 27)
#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
#define KWGBE_RX_EN_INTERRUPT (1 << 29)
#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
#define MVGBE_CRC_ERROR 0
#define MVGBE_OVERRUN_ERROR (1 << 1)
#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
#define MVGBE_VLAN_TAGGED (1 << 19)
#define MVGBE_BPDU_FRAME (1 << 20)
#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
#define MVGBE_FRAME_HEADER_OK (1 << 25)
#define MVGBE_RX_LAST_DESC (1 << 26)
#define MVGBE_RX_FIRST_DESC (1 << 27)
#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
#define MVGBE_RX_EN_INTERRUPT (1 << 29)
#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
#define KWGBE_FRAME_FRAGMENTED (1 << 2)
#define MVGBE_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
#define KWGBE_TCP_FRAME 0
#define KWGBE_UDP_FRAME (1 << 16)
#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
#define KWGBE_ZERO_PADDING (1 << 19)
#define KWGBE_TX_LAST_DESC (1 << 20)
#define KWGBE_TX_FIRST_DESC (1 << 21)
#define KWGBE_GEN_CRC (1 << 22)
#define KWGBE_TX_EN_INTERRUPT (1 << 23)
#define KWGBE_AUTO_MODE (1 << 30)
#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
#define MVGBE_TCP_FRAME 0
#define MVGBE_UDP_FRAME (1 << 16)
#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
#define MVGBE_ZERO_PADDING (1 << 19)
#define MVGBE_TX_LAST_DESC (1 << 20)
#define MVGBE_TX_FIRST_DESC (1 << 21)
#define MVGBE_GEN_CRC (1 << 22)
#define MVGBE_TX_EN_INTERRUPT (1 << 23)
#define MVGBE_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
@ -341,24 +343,24 @@
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
struct kwgbe_barsz {
struct mvgbe_barsz {
u32 bar;
u32 size;
};
struct kwgbe_rxcdp {
struct kwgbe_rxdesc *rxcdp;
struct mvgbe_rxcdp {
struct mvgbe_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
struct kwgbe_tqx {
struct mvgbe_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
struct kwgbe_registers {
struct mvgbe_registers {
u32 phyadr;
u32 smi;
u32 euda;
@ -372,7 +374,7 @@ struct kwgbe_registers {
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
struct kwgbe_barsz barsz[6];
struct mvgbe_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
@ -417,14 +419,14 @@ struct kwgbe_registers {
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
struct kwgbe_rxcdp rxcdp[7];
struct kwgbe_rxdesc *rxcdp7;
struct mvgbe_rxcdp rxcdp[7];
struct mvgbe_rxdesc *rxcdp7;
u32 rqc;
struct kwgbe_txdesc *tcsdp;
struct mvgbe_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
struct kwgbe_txdesc *tcqdp[8];
struct mvgbe_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
struct kwgbe_tqx tqx[8];
struct mvgbe_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
@ -447,26 +449,26 @@ struct kwgbe_registers {
};
/* structures/enums needed by driver */
enum kwgbe_adrwin {
KWGBE_WIN0,
KWGBE_WIN1,
KWGBE_WIN2,
KWGBE_WIN3,
KWGBE_WIN4,
KWGBE_WIN5
enum mvgbe_adrwin {
MVGBE_WIN0,
MVGBE_WIN1,
MVGBE_WIN2,
MVGBE_WIN3,
MVGBE_WIN4,
MVGBE_WIN5
};
enum kwgbe_target {
KWGBE_TARGET_DRAM,
KWGBE_TARGET_DEV,
KWGBE_TARGET_CBS,
KWGBE_TARGET_PCI0,
KWGBE_TARGET_PCI1
enum mvgbe_target {
MVGBE_TARGET_DRAM,
MVGBE_TARGET_DEV,
MVGBE_TARGET_CBS,
MVGBE_TARGET_PCI0,
MVGBE_TARGET_PCI1
};
struct kwgbe_winparam {
enum kwgbe_adrwin win; /* Window number */
enum kwgbe_target target; /* System targets */
struct mvgbe_winparam {
enum mvgbe_adrwin win; /* Window number */
enum mvgbe_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
@ -475,31 +477,31 @@ struct kwgbe_winparam {
u16 access_ctrl; /*Access ctrl register. see above macros */
};
struct kwgbe_rxdesc {
struct mvgbe_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct kwgbe_txdesc {
struct mvgbe_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
struct kwgbe_device {
struct mvgbe_device {
struct eth_device dev;
struct kwgbe_registers *regs;
struct kwgbe_txdesc *p_txdesc;
struct kwgbe_rxdesc *p_rxdesc;
struct kwgbe_rxdesc *p_rxdesc_curr;
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
#endif /* __EGIGA_H__ */
#endif /* __MVGBE_H__ */

4
include/configs/guruplug.h
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@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */

4
include/configs/km_arm.h
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@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */

4
include/configs/mv88f6281gtw_ge.h
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@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */

4
include/configs/openrd_base.h
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@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */

4
include/configs/rd6281a.h
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@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */

4
include/configs/sheevaplug.h
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@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */

2
include/netdev.h
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@ -63,7 +63,6 @@ int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
@ -72,6 +71,7 @@ int mpc512x_fec_initialize(bd_t *bis);
int mpc5xxx_fec_initialize(bd_t *bis);
int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
int mvgbe_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
int npe_initialize(bd_t *bis);
int ns8382x_initialize(bd_t *bis);

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